Artificial Intelligence and Microsystems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: 15 August 2026 | Viewed by 5459

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Guest Editor
School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: gate driver design for SiC MOSFET; high-temperature integrated circuits based on SiC
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Guest Editor
School of Integrated Circuits, Peking University, Beijing 100084, China
Interests: power electronics systems; microsystem technology

Special Issue Information

Dear Colleagues,

The rapid development of artificial intelligence has fuelled technological innovations in various fields, which have resulted in the development of many advanced, application-driven solutions. These technological solutions have reduced labour requirements, increased productivity and supported innovative development.

The purpose of this Special Issue is to provide a comprehensive overview of the latest applications and advances in AI and microsystem technology and related areas. It especially seeks to highlight innovative research and development efforts in microsystem design and the integration of microsystems and AI technology for end-side applications. Contributions to this Special Issue will explore the characteristics and trends of these technologies in end-side applications and how they can be utilised to address contemporary challenges in various fields.

We welcome the submission of original research articles and reviews. The research areas covered may include (but are not limited to) the following:

  • End-side lightweight artificial intelligence deployment techniques;
  • The application of microsystem verification techniques;
  • Techniques for artificial intelligence-assisted microsystem design;
  • Techniques to improve microsystems’ architectures, integration, and reliability;
  • High-speed optical link devices for the interconnection of AI systems;
  • Multi-agent autonomous control and decision-making;
  • Artificial intelligence-based image recognition technology.

Prof. Dr. Yimeng Zhang
Dr. Shikai Sun
Guest Editors

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Keywords

  • microsystem
  • artificial intelligence
  • image recognition

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Published Papers (5 papers)

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Research

13 pages, 3658 KB  
Article
TR-ABFT: Tile-Resilient Fault Detection for Neural Processing Units
by Yang Hua, Yunhong Bai, Bo Wang, Wei Zhuang and Yuanfu Zhao
Electronics 2026, 15(12), 2715; https://doi.org/10.3390/electronics15122715 - 19 Jun 2026
Viewed by 319
Abstract
Spaceborne neural processing units (NPUs) increasingly support real-time deep-learning inference, but their dense multiply-accumulate arrays are vulnerable to radiation-induced soft errors. Conventional radiation-hardening methods improve reliability through hardware redundancy, but they incur substantial area, performance and compiler-mapping overheads. This paper proposes tile-resilient algorithm-based [...] Read more.
Spaceborne neural processing units (NPUs) increasingly support real-time deep-learning inference, but their dense multiply-accumulate arrays are vulnerable to radiation-induced soft errors. Conventional radiation-hardening methods improve reliability through hardware redundancy, but they incur substantial area, performance and compiler-mapping overheads. This paper proposes tile-resilient algorithm-based fault tolerance (TR-ABFT), a software-scheduled, detection-oriented scheme for quantized NPU inference. TR-ABFT generates checksum information at tile granularity and maps checking tasks onto the original processing element (PE) array without changing the hardware topology. To make ABFT compatible with INT8 datapaths, we design two checksum-coding strategies: checksum decomposition and modulo-239 checksum coding. The modulo-239 scheme removes structural missed detections for two-bit flips with bit-position spacings in (1, 31), while preserving compatibility with signed INT8 inputs. Evaluations on ResNet, YOLOv8, and RT-DETR show that, on a 16×16 array, TR-ABFT introduces only 6.37% to 24.61% additional computational overhead. By converting spatial redundancy into schedulable temporal redundancy, TR-ABFT preserves systolic-array regularity and provides a low-overhead reliability-enhancement mechanism for space-grade neural-network accelerators. Full article
(This article belongs to the Special Issue Artificial Intelligence and Microsystems)
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12 pages, 4146 KB  
Article
The Analyses of Radiation Effects on SiGe HBT Devices for High-Speed Mixed-Signal Processing in Aerospace
by Zhibin Qin, Changlei Feng, Yue Zhang, Fan Zhang, Chen Lyu, Shanshan Sun and Ji Zhou
Electronics 2026, 15(7), 1479; https://doi.org/10.3390/electronics15071479 - 2 Apr 2026
Viewed by 703
Abstract
This study presents a TCAD model of a SiGe HBT designed for high-speed data transfer, with a cutoff frequency of 246.5 GHz and a β-value up to 416.7. Comprehensive single-event transient (SET) irradiation simulations were performed by injecting charges at different junctions with [...] Read more.
This study presents a TCAD model of a SiGe HBT designed for high-speed data transfer, with a cutoff frequency of 246.5 GHz and a β-value up to 416.7. Comprehensive single-event transient (SET) irradiation simulations were performed by injecting charges at different junctions with various angles. The influence of SET on data transfer was further evaluated at circuit level by loading the SET model from TCAD simulation into a high-speed laser diode driver circuit. Hence, this work employed a collector dummy structure in the designed HBT to build radiation-hardened devices. Simulation results indicate significant mitigation of the single-event transient current, which could be reduced to 10%, compared with non-hardened devices. Full article
(This article belongs to the Special Issue Artificial Intelligence and Microsystems)
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13 pages, 1144 KB  
Article
NPU-Aware Fault Injection and Statistical Sensitivity Analysis for CNN Reliability Evaluation
by Yang Hua, Jianyu Zhang, Quanyu Piao, Wei Zhuang and Yuanfu Zhao
Electronics 2026, 15(6), 1295; https://doi.org/10.3390/electronics15061295 - 20 Mar 2026
Viewed by 634
Abstract
Artificial intelligence (AI) is propelling space exploration into a new era. Synergistic breakthroughs in chip design and high-speed communications have facilitated the large-scale deployment of on-board satellite computing. Assessing the reliability of these systems via fault injection (FI) remains difficult due to the [...] Read more.
Artificial intelligence (AI) is propelling space exploration into a new era. Synergistic breakthroughs in chip design and high-speed communications have facilitated the large-scale deployment of on-board satellite computing. Assessing the reliability of these systems via fault injection (FI) remains difficult due to the massive computational demands of Convolutional Neural Networks (CNNs) and the complex architectures of Neural Processing Units (NPUs). This research presents a high-precision, efficient FI methodology specifically tailored for NPU architectures to optimize both evaluation accuracy and execution efficiency. Implementing a hierarchical injection strategy to identify fault-sensitive layers minimizes computational overhead while ensuring statistical validity. Experimental results on the ResNet-50 network demonstrate that the proposed methodology constrains accuracy degradation to less than 0.1% while achieving a 60.80% reduction in total execution time. Full article
(This article belongs to the Special Issue Artificial Intelligence and Microsystems)
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29 pages, 29485 KB  
Article
FPGA-Based Dual Learning Model for Wheel Speed Sensor Fault Detection in ABS Systems Using HIL Simulations
by Farshideh Kordi, Paul Fortier and Amine Miled
Electronics 2026, 15(1), 58; https://doi.org/10.3390/electronics15010058 - 23 Dec 2025
Cited by 1 | Viewed by 1046
Abstract
The rapid evolution of modern vehicles into intelligent and interconnected systems presents new complexities in both functional safety and cybersecurity. In this context, ensuring the reliability and integrity of critical sensor data, such as wheel speed inputs for anti-lock brake systems (ABS), is [...] Read more.
The rapid evolution of modern vehicles into intelligent and interconnected systems presents new complexities in both functional safety and cybersecurity. In this context, ensuring the reliability and integrity of critical sensor data, such as wheel speed inputs for anti-lock brake systems (ABS), is essential. Effective detection of wheel speed sensor faults not only improves functional safety, but also plays a vital role in keeping system resilience against potential cyber–physical threats. Although data-driven approaches have gained popularity for system development due to their ability to extract meaningful patterns from historical data, a major limitation is the lack of diverse and representative faulty datasets. This study proposes a novel dual learning model, based on Temporal Convolutional Networks (TCN), designed to accurately distinguish between normal and faulty wheel speed sensor behavior within a hardware-in-the-loop (HIL) simulation platform implemented on an FPGA. To address dataset limitations, a TruckSim–MATLAB/Simulink co-simulation environment is used to generate realistic datasets under normal operation and eight representative fault scenarios, yielding up to 5000 labeled sequences (balanced between normal and faulty behaviors) at a sampling rate of 60 Hz. Two TCN models are trained independently to learn normal and faulty dynamics, and fault decisions are made by comparing the reconstruction errors (MSE and MAE) of both models, thus avoiding manually tuned thresholds. On a test set of 1000 sequences (500 normal and 500 faulty) from the 5000 sample configuration, the proposed dual TCN framework achieves a detection accuracy of 97.8%, a precision of 96.5%, a recall of 98.2%, and an F1-score of 97.3%, outperforming a single TCN baseline, which achieves 91.4% accuracy and an 88.9% F1-score. The complete dual TCN architecture is implemented on a Xilinx ZCU102 FPGA evaluation kit (AMD, Santa Clara, CA, USA), while supporting real-time inference in the HIL loop. These results demonstrate that the proposed approach provides accurate, low-latency fault detection suitable for safety-critical ABS applications and contributes to improving both functional safety and cyber-resilience of braking systems. Full article
(This article belongs to the Special Issue Artificial Intelligence and Microsystems)
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20 pages, 2508 KB  
Article
An Attention-Enhanced Network for Person Re-Identification via Appearance–Gait Fusion
by Zelong Yu, Yixiang Cai, Hanming Xu, Lei Chen, Mingqian Yang, Huabo Sun and Xiangyu Zhao
Electronics 2025, 14(21), 4142; https://doi.org/10.3390/electronics14214142 - 22 Oct 2025
Cited by 4 | Viewed by 1155
Abstract
The objective of person re-identification (Re-ID) is to recognize a given target pedestrian across different cameras. However, perspective variations, resulting from differences in shooting angles, often significantly impact the accuracy of person Re-ID. To address this issue, this paper presents an attention-enhanced person [...] Read more.
The objective of person re-identification (Re-ID) is to recognize a given target pedestrian across different cameras. However, perspective variations, resulting from differences in shooting angles, often significantly impact the accuracy of person Re-ID. To address this issue, this paper presents an attention-enhanced person Re-ID algorithm based on appearance–gait information interaction. Specifically, appearance features and gait features are first extracted from RGB images and gait energy images (GEIs), respectively, using two ResNet-50 networks. Then, a multimodal information exchange module based on the attention mechanism is designed to build a bridge for information exchange between the two modalities during the feature extraction process. This module aims to enhance the feature extraction ability through mutual guidance and reinforcement between the two modalities, thereby improving the model’s effectiveness in integrating the two types of modal information. Subsequently, to further balance the signal-to-noise ratio, importance weight estimation is employed to map perspective information into the importance weights of the two features. Finally, based on the autoencoder structure, the two features are weighted and fused under the guidance of importance weights to generate fused features that are robust to perspective changes. The experimental results on the CASIA-B dataset indicate that, under conditions of viewpoint variation, the method proposed in this paper achieved an average accuracy of 94.9%, which is 1.1% higher than the next best method, and obtained the smallest variance of 4.199, suggesting that the method proposed in this paper is not only more accurate but also more stable. Full article
(This article belongs to the Special Issue Artificial Intelligence and Microsystems)
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