CMOS Chips for Sensing and Communication

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 March 2023) | Viewed by 6641

Special Issue Editors


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Guest Editor
School of Microelectronics, Tianjin University, Tianjin 300072, China
Interests: RF; mm-Wave; THz integrated circuits and systems

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Co-Guest Editor
School of Microelectronics, South China University of Technology, Guangzhou 510641, China
Interests: mm-Wave; THz ICs

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Co-Guest Editor
School of Microelectronics, Tianjin University, Tianjin 300072, China
Interests: CMOS image sensors; mixed-signal integrated circuits
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Special Issue Information

Dear Colleagues, 

Since their discovery, CMOS technologies have enabled tremendous intelligent circuits and functionalities in the forms of tiny chips or chiplets, some of which are dedicated to enabling smart and pervasive sensing and wireless communications. (1) Imaging sensors: CMOS chips for image sensing are highly integrated optoelectronic chips which convert optical information into digital information that is easy to process and store. (2) Radar sensing: typical applications of radar sensing in daily life include middle- and long-range automotive radars; short-range detection, imaging, and recognition radars; and health-care radars. (3) Wireless communication: in the area of wireless communications, fifth-generation (5G) wireless communication networks are being deployed worldwide since 2020 and the research on 6G wireless communication is also ongoing, which are expected to provide global coverage, enhanced efficiency, higher data rate (Tbps), lower latency, etc.

This Special Issue encourages researchers to present theories, techniques, circuits, and systems of CMOS chips for radar/image sensing and wireless communication regarding emerging issues and challenges. The scope of this Special Issue focuses on, but is not limited to:

Imaging sensors: The development of image sensing with better performance and diverse functions, including high speed, high dynamic range, 3D imaging, low-light imaging and dynamic vision sensors, etc.

RF circuits: Building blocks at RF, mm-Wave and THz frequencies for receivers, transmitters, frequency synthesizers, transceivers, SoCs, and SiPs.

Wireless radar/communication transceivers: Circuit-level and system-architecture solutions for low-power, energy-efficient and high-performance wireless links, emerging broadband and phased-array systems, vehicle-to-everything (V2X), millimeter-wave and THz systems (radar, imaging, or communication).

Prof. Dr. Fanyi Meng
Dr. Guangyin Feng
Dr. Kaiming Nie
Guest Editors

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Keywords

  • imaging sensors
  • RF circuits
  • wireless radar/communication transceivers

Published Papers (5 papers)

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Research

9 pages, 2691 KiB  
Article
Low-Power Current Integrating Flat-Passband Infinite Impulse Response Filter for Sensor Read-Out Integrated Circuit in 65-nm CMOS Technology
by Sung-Hun Jo
Electronics 2023, 12(5), 1191; https://doi.org/10.3390/electronics12051191 - 01 Mar 2023
Viewed by 1187
Abstract
Low-power current integrating infinite impulse response filter having flat-passband for sensor read-out integrated circuit is proposed. In a current integrating filter, passband flatness degradation is inevitable due to sinc-like filtering characteristics. In this paper, by proposing a high order infinite impulse response [...] Read more.
Low-power current integrating infinite impulse response filter having flat-passband for sensor read-out integrated circuit is proposed. In a current integrating filter, passband flatness degradation is inevitable due to sinc-like filtering characteristics. In this paper, by proposing a high order infinite impulse response filter architecture, flat-passband characteristic can be achieved. By implementing a filter architecture with a flat passband, the required sampling frequency can be lowered, which in turn can reduce power consumption. Moreover, the proposed high order infinite impulse response filter architecture has a high degree of freedom on adjusting input sample weights. The proposed integrated circuit is implemented in TSMC 65-nm CMOS process and operated on 1.2 V supply voltage. Full article
(This article belongs to the Special Issue CMOS Chips for Sensing and Communication)
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9 pages, 3624 KiB  
Article
Self-Decoupled MIMO Antenna Realized by Adjusting the Feeding Positions
by Yangyang He, Yi-Feng Cheng and Jiang Luo
Electronics 2022, 11(23), 4004; https://doi.org/10.3390/electronics11234004 - 02 Dec 2022
Cited by 2 | Viewed by 1408
Abstract
This paper proposes a novel decoupling technique achieved by adjusting the position of feeding probes of antennas. Two inherent radiation modes (patch mode and monopole mode), with different patterns and polarizations, are simultaneously excited by the same feeding probe. High isolation is realized [...] Read more.
This paper proposes a novel decoupling technique achieved by adjusting the position of feeding probes of antennas. Two inherent radiation modes (patch mode and monopole mode), with different patterns and polarizations, are simultaneously excited by the same feeding probe. High isolation is realized based on manipulating the relationship of two-mode couplings by moving the feeding positions. Since the two radiation modes are generated by the same antenna element, the proposed MIMO antenna features a simple structure and compact size. For verification, a two-element array with center-to-center spacing of 0.404 λ0 (λ0 is the wavelength in the air) is prototyped and characterized. Simulation and experimental results show that the proposed novel technique can offer higher port isolation (>18.1 dB), increased efficiency (>70%), and a lower envelope correlation coefficient (ECC < 0.1) in the operating frequency band (11.61–12.49 GHz). Full article
(This article belongs to the Special Issue CMOS Chips for Sensing and Communication)
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9 pages, 5410 KiB  
Article
A Gain-Enhanced Low Hardware Complexity Charge-Domain Read-Out Integrated Circuit Using a Sampled Charge Redistribution Technique
by Sung-Hun Jo
Electronics 2022, 11(23), 3846; https://doi.org/10.3390/electronics11233846 - 22 Nov 2022
Viewed by 825
Abstract
A gain-enhanced low hardware complexity charge-domain read-out integrated circuit is implemented. By adopting a sampled charge redistribution technique, low hardware complexity is achieved, which in turn saves 10% of the die area and provides 33% gain enhancement compared to the conventional topology. In [...] Read more.
A gain-enhanced low hardware complexity charge-domain read-out integrated circuit is implemented. By adopting a sampled charge redistribution technique, low hardware complexity is achieved, which in turn saves 10% of the die area and provides 33% gain enhancement compared to the conventional topology. In particular, a charge-domain discrete-time filter with inherent reconfigurability is a key building block, which can also act as an anti-aliasing filter before the analog-to-digital converter. The measurement results show good agreement with the intended frequency response. The proposed filter is implemented using a 0.11 μm CMOS process and occupies 0.15 mm2. Full article
(This article belongs to the Special Issue CMOS Chips for Sensing and Communication)
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9 pages, 3534 KiB  
Article
A Compact 10–14.5 GHz Quadrature Hybrid with Digitally Reconfigurable I/Q Phase in SiGe BiCMOS Process
by Zhe Chen, Xiaojie Xu, Debin Hou, Peigen Zhou, Pinpin Yan and Jixin Chen
Electronics 2022, 11(22), 3803; https://doi.org/10.3390/electronics11223803 - 18 Nov 2022
Viewed by 1003
Abstract
In this article, the development of a compact 10–14.5 GHz quadrature hybrid with digitally reconfigurable I/Q phase in 130 nm SiGe BiCMOS process is presented. Thanks to the switched capacitance loaded on I/Q path of the quadrature hybrid, the I/Q phase difference can [...] Read more.
In this article, the development of a compact 10–14.5 GHz quadrature hybrid with digitally reconfigurable I/Q phase in 130 nm SiGe BiCMOS process is presented. Thanks to the switched capacitance loaded on I/Q path of the quadrature hybrid, the I/Q phase difference can be optimized and digitally reconfigured. The equivalent model is analyzed with even/odd mode theory, and the ABCD matrix is used for the circuit derivation. In order to obtain high coupling coefficient, the broadside coupled line sections are utilized, and compact hybrid size can be realized accordingly. Measured results show that the compact quadrature hybrid has optimized phase difference of 90 ± 1.0° and amplitude difference less than ±0.5 dB for 10–14.5 GHz, with an ultra-compact size of 460 µm × 151 µm, or 0.031λ0 × 0.011λ0. Meanwhile, with the seven reconfigurable phase states, the quadrature hybrid I/Q phase can be digitally reconfigured for a range of 3 degrees to compensate the I/Q phase imbalance in the quadrature system, without DC power consumption. Full article
(This article belongs to the Special Issue CMOS Chips for Sensing and Communication)
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12 pages, 4443 KiB  
Article
Real-Time Non-Uniformity Correction without TEC for Microbolometer Array
by Jun Dong Yeo and DooHyung Woo
Electronics 2022, 11(19), 3083; https://doi.org/10.3390/electronics11193083 - 27 Sep 2022
Viewed by 1458
Abstract
This paper describes a new readout integrated circuit and non-uniformity correction (NUC) method that ensures that the bolometer array has low non-uniformity over a wide operating temperature range without a thermoelectric cooler (TEC). The proposed NUC minimizes the circuit and memory required for [...] Read more.
This paper describes a new readout integrated circuit and non-uniformity correction (NUC) method that ensures that the bolometer array has low non-uniformity over a wide operating temperature range without a thermoelectric cooler (TEC). The proposed NUC minimizes the circuit and memory required for signal processing, making it suitable for compact and power-efficient portable infrared cameras. It corrects the aging phenomenon through start-up calibration and corrects non-uniformities without a TEC through calibration during operation mode. It minimizes the calibration process during operation mode and uses a pixel-level analog-to-digital converter to enable real-time NUC. A 0.18 μm standard CMOS process is applied to the proposed NUC. The frame rate for calibration during the operation mode is approximately 14.3 Hz. The proposed NUC demonstrates excellent uniformity with a non-uniformity of less than 0.12% over a wide operating temperature range (−20 to 50 °C). Full article
(This article belongs to the Special Issue CMOS Chips for Sensing and Communication)
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