Technologies, Volume 8, Issue 1 (March 2020) – 17 articles

The concept of the quantified self has gained popularity in recent years with the hype of miniaturized gadgets to monitor vital fitness levels. Smartwatches or smartphone apps and other fitness trackers are overwhelming the market. Most aerobic exercises such as walking, running, or cycling can be accurately recognized using wearable devices. However whole-body exercises such as push-ups, bridges, and sit-ups are performed on the ground and thus cannot be precisely recognized by wearing only one accelerometer. Thus, a floor-based approach is preferred for recognizing whole-body activities. Computer vision techniques on image data also report high recognition accuracy; however, the presence of a camera tends to raise privacy issues in public areas. Therefore, we focus on combining the advantages of ubiquitous proximity-sensing with non-optical sensors to preserve privacy in public areas and maintain low computation cost with a sparse sensor implementation. Our solution is the ExerTrack, an off-the-shelf sports mat equipped with eight sparsely distributed capacitive proximity sensors to recognize eight whole-body fitness exercises with a user-independent recognition accuracy of 93.5% and a user-dependent recognition accuracy of 95.1% based on a test study with 9 participants each performing 2 full sessions. We adopt a template-based approach to count repetitions and reach a user-independent counting accuracy of 93.6%. The final model can run on a Raspberry Pi 3 in real time. This work includes data-processing of our proposed system and model selection to improve the recognition accuracy and data augmentation technique to regularize the network. Full article

The purpose of this paper was to propose a complete analysis and parameter estimations of a new simplified and highly nonlinear hafnium dioxide memristor model that is appropriate for high-frequency signals. For the simulations; a nonlinear window function previously offered by the author together with a highly nonlinear memristor model was used. This model was tuned according to an experimentally recorded current–voltage relationship of a HfO₂ memristor. This study offered an estimation of the optimal model parameters using a least squares algorithm in SIMULINK and a methodology for adjusting the model by varying its parameters overbroad ranges. The optimal values of the memristor model parameters were obtained after minimizing the error between the experimental and simulated current–voltage characteristics. A comparison of the obtained errors between the simulated and experimental current–voltage relationships was made. The error derived by the optimization algorithm was a little bit lower than that obtained by the used methodology. To avoid convergence problems; the step function in the considered model was replaced by a differentiable tangent hyperbolic function. A PSpice library model of the HfO₂ memristor based on its mathematical model was created. The considered model was successfully applied and tested in a multilayer memristor neural network with bridge memristor–resistor synapses Full article

Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations. Full article

In this paper, two implementations of reconfigurable bandwidth bandpass filters (BPFs) are demonstrated both operating at a fixed center frequency of 2.4 GHz. The proposed reconfigurable bandwidth filters are based on a square ring resonator loaded with λ_g/4 open-ended stubs that are permanently connected to the ring and converted to either 3λ_g/4 open-ended stubs or λ_g/2 short-ended stubs by means of positive-intrinsic-negative(PIN) diodes to implement two reconfigurable bandwidth states for each case. Due to the symmetrical nature of the design, even- and odd-mode analysis is used to derive the closed-form to describe the reconfigurable filters’ behavior. The switching between narrowband and wideband is achieved using PIN diodes. In the first implementation (λ_g/4 open-ended stubs to 3λ_g/4 open-ended stubs), a reconfigurable bandwidth bandpass filter is proposed where additional out-of-band transmission zeros are generated by integrating a λ_g/2 open-ended stub at the input port. In the second implementation (λ_g/4 open-ended stubs to λ_g/2 short-ended stubs), further improvement in the upper stopband is achieved by utilizing a pair of parallel coupled lines (PCLs) as feeding lines and a pair of λ_g/4 high impedance short-ended stubs implemented at the input and output ports. To verify the validity of the simulated results, the prototypes of the proposed reconfigurable filters were fabricated. For the first case, measured insertion loss is less than 1.8 dB with a switchable 3-dB fractional bandwidth (FBW) range from 28% to 54%. The measured results for the second case exhibit a low insertion loss of less than 1 dB and a 3-dB fractional bandwidth that can be switched from 34% to 75%, while the center frequency is kept constant at 2.4 GHz in both cases. Full article

In this paper a number of LT Spice simulations have been carried out on an Electrical Impedance Tomography (EIT) system, which includes the whole analog and digital circuitry as well as the subject to be examined (phantom model). The aim of this study is to show how the analog and digital parts, the electrodes and the subject’s physical properties may impact the measurements and the quality of the reconstructed image. This could provide a useful tool for designing an EIT system. Special attention has been given to the current source’s output impedance and swing, to the noise produced by the circuits and to the Analog to Digital Converters (ADCs) resolution and sampling rate. Furthermore, some 3D phantom subjects have been modeled and simulated as equivalent circuits, merged with the EIT simulated hardware, in order to observe how changes on their properties interact with the whole circuitry and affect the final result. Observations show that mirrored current sources with $z_{out}$ > 350 k $\Omega$ and sufficiently high ADC acquisition sampling rate ( $f_{sample}\ge 16f_{in}$ ) can result to accurate impedance measurements and therefore quality image reconstruction within a frequency span of at least 10 to 100 kHz. Moreover, possible hardware failures (electrode disconnections and imbalanced contact impedances) can be detected with a simple examination of the first extracted image and measurement set, so that by direct modification of the reconstruction process, a corrected result can be obtained. Full article

The uncertainties present in a variety of electromagnetic (EM) problems may have important effects on the output parameters of interest. Unfortunately, deterministic schemes are not applicable in such cases, as they only utilize the nominal value of each random variable. In this work, a two-dimensional (2D) finite-difference time-domain (FDTD) algorithm is presented, which is suitable for assessing randomness in the electrical properties, as well as in the dimensions of orthogonal objects. The proposed technique is based on the stochastic FDTD method and manages to extract the mean and the standard deviation of the involved field quantities in one realization. This approach is applied to three test cases, where uncertainty exists in the electrical and geometrical parameters of various materials. The numerical results demonstrate the validity of our scheme, as similar outcomes are extracted compared to the Monte Carlo (MC) algorithm. Full article

In this work, we propose an algorithm for joint calibration and axes alignment of a 3-axis accelerometer and a 3-axis magnetometer. The proposed algorithm applies when the two sensors are fixed on the same rigid platform. It achieves accurate calibration without requiring any external piece of equipment like a turntable for the accelerometer or Gauss magnetic chamber and Maxwell coils setup for the magnetometer. The efficiency and accuracy of the proposed algorithm are evaluated using experimental data. Full article

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well. Full article

Concrete and asphalt are the primary materials used to construct roadways for motor vehicles, paths for pedestrians and bicyclists, and runways for aircraft. Solar Roadways^®, Inc. (SR) proposed a novel solar pavement technology (i.e., solar road panels (SRP)) as an alternative material and energy source. SR performed load, traction, and impact testing to use SRPs in non-critical applications like parking lots. To use SRP in public roads, engineering tests including freeze/thaw, moisture absorption, heavy vehicle, and shear testing were accomplished on “SR3” prototypes. Testing was performed at Marquette University in the Engineering Materials and Structural Testing Laboratory and the SR Pilot Project area. Moisture absorption and freeze/thaw tests showed “SR3” resistant to extreme weather and moisture environments. Heavy vehicle testing revealed no physical damage to the “SR3” after approximately 989,457 equivalent single axle loads were continuously rolled over a prototype pavement. Shear testing was conducted to investigate “SR3” laminate structure properties. In all cases, electrical failure was defined when “SR3” photovoltaic voltage dropped to zero volts. The maximum shear stress and applied torque for “SR3”’ (S/N’s Paver 1, 002B, 007C, and 004B) were 1756 kPa, 1835 kPa, 1643 kPa, 2023 kPa; and 121.2 kN·m, 131.3 kN·m, 117.6 kN·m, 144.8 kN·m, respectively. In addition, the “SR3” “heartbeat” light emitting diode (LED) remained operational (i.e., indicates computer bus traffic) in all phases of shear testing. Overall, the results show “SR3” prototypes to be robust, resilient, and functional when subjected to “real-world” test conditions. Full article

The open-circuit-time-constant (OCTC) method is an approximate analytical computationally simple approach applicable to baseband amplifiers and cascades of them. It has a dual purpose: a) to estimate the dominant pole, and the −3dB bandwidth frequency, and b) to identify actual or parasitic component values primarily responsible for this bandwidth guiding the designer in optimizing component values and circuit architecture. The present study focuses on the teaching of OCTC and the analysis of students’ depth of understanding. The OCTC module is part of the course “Electronics III” aimed towards advanced undergraduate students who are asked to solve two sets of problems analytically and simulate the circuits using LTspice and compare the results. The paper discusses students’ misconceptions and the evaluation of students’ performance via assignment grades, an anonymous sampling test and final exams (four exams during two academic years). A quantitative evaluation of the students’ perspective of the course is also presented based on two anonymous surveys, at the beginning and the end of the semester. According to the evaluation results, the proposed way of introducing the OCTC method along with the simulation exercises was beneficial for the students and improved their academic performance and attitude towards the course. Full article

The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has established Application-Specific Integrated Circuit (ASIC)-based accelerators as alternative efficient solutions. During the last five years, the development of Hardware Description Language (HDL)-based CNN accelerators, either for FPGA or ASIC, has seen huge academic interest due to their high-performance and room for optimizations. Towards this direction, we propose a library-based framework, which extends TensorFlow, the well-established machine learning framework, and automatically generates high-throughput CNN inference engines for FPGAs and ASICs. The framework allows software developers to exploit the benefits of FPGA/ASIC acceleration without requiring any expertise on HDL development and low-level design. Moreover, it provides a set of optimization knobs concerning the model architecture and the inference engine generation, allowing the developer to tune the accelerator according to the requirements of the respective use case. Our framework is evaluated by optimizing the LeNet CNN model on the MNIST dataset, and implementing FPGA- and ASIC-based accelerators using the generated inference engine. The optimal FPGA-based accelerator on Zynq-7000 delivers 93% less memory footprint and 54% less Look-Up Table (LUT) utilization, and up to 10× speedup on the inference execution vs. different Graphics Processing Unit (GPU) and Central Processing Unit (CPU) implementations of the same model, in exchange for a negligible accuracy loss, i.e., 0.89%. For the same accuracy drop, the 45 nm standard-cell-based ASIC accelerator provides an implementation which operates at 520 MHz and occupies an area of 0.059 mm ${}^2$ , while the power consumption is ∼7.5 mW. Full article

Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented. Full article

In advanced society, the existing building stock has a high demand for stock renovation, which gives existing buildings new lives, rather than building new ones. During the renovation process, it is necessary to simultaneously achieve architectural, facilities, structural, and environmental design in order to accomplish a healthy, comfortable, and energy-saving indoor environment, prevent delays in problem-solving, and achieve a timely feedback process. This study tackled the development of an integrated system for stock renovation by considering computational fluid dynamics (CFD) and mixed reality (MR) in order to allow the simultaneous design of a building plan and thermal environment. The CFD analysis enables simulation of the indoor thermal environment, including the entire thermal change process. The MR system, which can be operated by voice command and operated on head-mounted display (HMD), enables intuitive visualization of the thermal change process and, in a very efficient manner, shows how different renovation projects perform for various stakeholders. A prototype system is developed with Unity3D engine and HoloLens HMD. In the integrated system, a new CFD visualization method generating 3D CFD animation sequence for the MR system is proposed that allows stakeholders to consider the entirety of changes in the thermal environment. Full article

The performance of an underwater optical wireless communication link is investigated by taking into account—for the first time and to the best of our knowledge—the simultaneous influence of the chromatic dispersion, the time jitter and the turbulence effects, by assuming chirped longitudinal Gaussian pulse propagation as information carriers. The estimation procedure is presented and a novel probability density function is extracted in order to describe the irradiance fluctuations at the receiver side. Furthermore, the availability of the link is investigated by means of its probability of fade and various numerical results are presented using typical parameters for the underwater optical wireless communication systems. Full article

The biological activity of chitosan determines its broad application as a biopolymer for non-woven wound dressings fabricated by electrospinning. The electrospinning process is affected by a large number of different factors that complicate its optimization. In the present work, the electrospinning of chitosan lactate was carried out using a needleless technique from water solutions of different compositions. Surface response methodology was used to evaluate the effects of the concentration of chitosan, polyethylene oxide, and ethanol on solution properties, such as viscosity, surface tension, and conductivity, as well as the process characteristics and fiber quality. The viscosity of the spinning solution is determined by the polymer concentration as well as by the interpolymer interactions. The addition of ethanol to the spinning solutions effectively decreases the solution surface tension and conductivity, while increasing the volatility of the solvent, to provide more intense fiber spinning. Atomic force microscopy revealed that the chitosan lactate fibers were obtained without defects and with a narrow thickness distribution. The spinning parameters, voltage, distance between electrodes, and rotation speed of the spinning electrode had insignificant influences on the fiber diameter during needleless electrospinning. Full article

The semantic understanding of a scene is a key problem in the computer vision field. In this work, we address the multi-level semantic segmentation task where a deep neural network is first trained to recognize an initial, coarse, set of a few classes. Then, in an incremental-like approach, it is adapted to segment and label new objects’ categories hierarchically derived from subdividing the classes of the initial set. We propose a set of strategies where the output of coarse classifiers is fed to the architectures performing the finer classification. Furthermore, we investigate the possibility to predict the different levels of semantic understanding together, which also helps achieve higher accuracy. Experimental results on the New York University Depth v2 (NYUDv2) dataset show promising insights on the multi-level scene understanding. Full article