Study on Characteristics of Enhancement-Mode Gallium-Nitride High-Electron-Mobility Transistor for the Design of Gate Drivers

Abstract

An enhancement-mode gallium-nitride high-electron-mobility transistor (E-mode GaN HEMT) operated at high frequency is highly prone to current spikes (di/dt) and voltage spikes (dv/dt) in the parasitic inductor of its circuit, resulting in damage to the power switch. To highlight the phenomena of di/dt and dv/dt, this study connected the drain, source, and gate terminals in series with inductors (L_D, L_S, and L_G, respectively). The objective was to explore the effects of di/dt and dv/dt phenomena and operating frequency (f_S) on drain-to-source voltage (V_ds), drain-to-source current (I_ds), and gate-to-source voltage (V_gs). The experimental method comprised two projects: (1) establishment of a measurement system to assess the change of electrical characteristics of the E-mode GaN HEMT and (2) change of the f_S and the inductances (i.e., L_D, L_S, and L_G) in the circuit to measure the changes in V_ds, I_ds, and V_gs, thus summarizing the experimental results. According to the experimental results on electrical characteristics, a gate driver circuit may be designed to drive and protect the E-mode GaN HEMT while being actually applied to a 120-W synchronous buck converter with an output voltage of 12 V and an output current of 10 A.

1. Introduction

The gradual yearly increase of greenhouse gases has intensified global warming. Energy-saving and carbon reduction have become the primary development goals for each country. The demand for relevant regulations (e.g., the Energy Star Standard and California Energy Commission Appliance Efficiency Regulations) and the market in recent years have driven the continual development of high-efficiency and high-power-intensity power supply units [1,2]. Because wide-bandgap materials are characterized by high breakdown voltage and high electron mobility, which merit operation under high temperatures and high frequencies [3,4,5,6,7,8,9,10], they have enabled the development of power supply units to gradually transition from silicon power switches to wide-bandgap power switches [3,4,5].

Wide-bandgap semiconductors may be categorized by their internal structures into enhancement-mode gallium-nitride high-electron-mobility transistors (E-mode GaN HEMTs) and gallium-nitride high-electron-mobility transistors (GaN HEMTs) [11].

Table 1. The key parameters compare the enhancement-mode gallium-nitride high-electron-mobility transistors (E-mode GaN HEMTs) with the GaN HEMT [12,13].

Key Parameter		E-Mode GaN HEMT	GaN HEMT	Unit
Static	RDS(ON) (150 °C)	37	105	mΩ
Dynamic	QG	6.5	28	nC
	QGS	1.4	10	nC
	QGD	2.8	6	nC
Reverse Operation	QRR	≈0	136	nC

presents a comparison between key parameters (static, dynamic, and reverse operation) of E-mode GaN HEMT and GaN HEMT. The following findings were revealed from the comparison: (1) regarding static parameters, E-mode GaN HEMT with a R_DS(ON) value smaller than that of GaN HEMT yielded lower conduction loss. (2) Regarding dynamic parameters, both transistors are voltage-driven components that require charging and discharging of a parasitic inductor between gate-to-source and gate-to-drain terminals for conduction and cut-off. That is, because the total gate charge (Q_G), gate–source charge (Q_GS), and gate–drain charge (Q_GD) of E-mode GaN HEMT were lower than those of GaN HEMT, E-mode GaN HEMT required less time for conduction and cut-off as well as experienced weaker di/dt and dv/dt. (3) Reverse-recovery charge (Q_RR) of the E-mode GaN HEMT was approximately zero under reverse operation, constituting an extremely short reverse recovery time as well as minimal component loss and electromagnetic interference. Given the three aforementioned advantages of E-mode GaN HEMT, this study employed it for the experiment.

High-frequency operation subjects the parasitic inductor of the circuit to di/dt and dv/dt phenomena, which could entail oscillation in voltage and current waveforms and create electromagnetic interference. Serious electromagnetic interference can result in damage to the power switch [14].

A measurement system was first established to assess the electrical characteristics of the E-mode GaN HEMT. Subsequently, to accentuate the di/dt and dv/dt phenomena, this study connected the drain, source, and gate terminals in series with inductors (L_D, L_S, and L_G, respectively) and adjusted inductor values before measuring the waveform changes of V_ds, I_ds, and V_gs. In addition, this study adjusted the operating frequency from 100 kHz to 2 MHz to measure the waveform changes of V_ds and V_gs. Based on the results from the electrical characteristic experiment, this study’s aim was to design a gate driver circuit to drive the E-mode GaN HEMT while further protecting said transistor by monitoring the changes in V_gs and I_ds values.

In Section 2 and Section 3, the measurement system and electrical characteristics of E-mode GaN HEMT are introduced, respectively. Section 4 details the circuit framework and application of the gate driver circuit, whereas Section 5 presents the conclusion.

2. Measuring System

When E-mode GaN HEMT is switched on or off, di/dt and dv/dt phenomena occur. Therefore, at various operating frequencies, load currents, and inductances, a measurement system was used to assess and record the changes in V_ds, I_ds, and V_gs. Figure 1 presents the measurement system, composed of a function generator (fabricant: SIGLENT, model: SDG2042X), a passive circuit, a digital oscilloscope (fabricant: LECROY, model: HDO4034A), a DC power supply (fabricant: GWINSTEK, model: SPD-3606), and an E-mode GaN HEMT (the testing component; fabricant: GaN system, model:GS61004B). The experimental parameters in Figure 1 are detailed in

Table 2. Experimental parameters of Figure 1.

Symbol	Value	Unit
Vdc	12	V
Idc	0.1–2.0	A
fs	100–2000	kHz
LD	0.01–3.00	μH
LS	0.01–3.00	μH
LG	0.01–3.00	μH
RG_ON	2	Ω
RG_OFF	0	Ω
D1 and D2	1N4148	-
1N4148 specification [15]
Fabricant	Diodes	-
Non-Repetitive Peak Reverse Voltage (VRM)	100	V
Forward Continuous Current (IFM)	300	mA
Reverse Recovery Time (tRR)	4	ns
Vds,max of GS61004B	100	V
Ids,max of GS61004B	30	A
Vgs,max of GS61004B	7	V

.

3. Electrical Characteristics of E-mode GaN HEMT when di/dt and dv/dt Occur

Regarding Figure 2, the GS61004B component provided by GaN Systems was loaded into TINA-TI; after a circuit diagram (Figure 2) was plotted, the V_ds, I_ds, and V_gs waveforms can be simulated. The simulation was performed in the condition of I_ds = 2 A and f_s = 150 kHz with the inductance parameters of L_G = 100 nH, L_D = 50 nH, and L_S = 50 nH. The obtained waveforms of I_D(I_ds), V_ds, and V_gs from the simulation are presented in Figure 3. To elucidate the exact time when di/dt and dv/dt occurred in the waveform, the maximum and minimum values of I_ds were marked as I_ds,max and I_ds,min, respectively; the maximum and minimum values of V_ds were denoted by V_ds,max and V_ds,min, respectively; and the maximum and minimum values of V_gs were marked as V_gs,max and V_gs,min, respectively. Subsequent experiments were implemented and recorded according to the aforementioned rules.

The parameters presented in Figure 2, namely output current, operating frequency (f_s), and inductors in series (i.e., L_D, L_S, and L_G), were changed. In four testing conditions, the maximum and minimum values of V_ds, I_ds, and V_gs were measured and recorded to determine spike changes.

3.1. Applying Various L_D Values to Measure the Changes in I_ds and V_ds when di/dt and dv/dt Occur

The parameter setting of L_G = L_S = 1 nH, f_s = 100 kHz, V_gs = 5 V, and L_D = 0.01–0.50 μH was applied. Figure 4a shows that under different I_ds (ranging from 0.1 A to 2.0 A) and before L_D achieved 0.1 μH, the V_ds,max changes of the five curves exhibited a linear relationship. After L_D exceeded 0.1 μH, V_ds,max underwent a rapid change, where the V_ds,max value of the blue and yellow curves approximated the specification of GS61004B (V_ds,max = 100 V); at that point, the experiment was terminated to avoid damaging the power switch. As presented in Figure 2, because the drain- and source-end of the GS61004B exhibited parasitic capacitance (C_ds), an RLC series network was formed with the loops of V_dc, R_dc, L_D, C_ds, and L_S. Therefore, with the circuit parameters R_dc = 6 Ω, L_S = 1 nH, L_D = 0.05–0.30 µH, and C_ds = 105 pF [16], the damping ratio (ζ) [17] was calculated to be 0.137, 0.125, 0.116, 0.109, 0.102, 0.097, 0.069, and 0.056. The curve of I_ds = 2 A in Figure 4a illustrates the relationship between L_D and V_ds,max. When ζ = 0.137 (L_D = 0.05 µH), the V_ds,max amplitude was low, whereas it was high when ζ = 0.056 (L_D = 0.30 µH).

Subsequently, the V_ds,max values of corresponding Points a (12.01 V), b (26.26 V), and c (60.49 V) on the gray, orange, and light blue curves, respectively, were found to not reach 100 V. Therefore, the researcher could continue to increase the L_D for the three curves. In Figure 4b, L_D ranges from 0.5 μH to 3.0 μH and Points a′, b′, and c′ correspond to points a, b, and c in Figure 4a. The researcher continued to increase L_D until the gray curve first yielded V_ds,max = 98 V; the experiment for the gray curve was terminated. Subsequently, when the L_D was increased to 3.0 μH, the orange and the light blue curves yielded V_ds,max values of 77.19 V and 13.46 V, respectively, both of which are lower than V_ds,max = 100 V.

3.2. Applying Different L_G Values to Measure the Changes of V_ds and V_gs When di/dt and dv/dt Occur

The parameter setting of I_ds = 2 A, L_S = 1 nH, f_s = 100 kHz, V_gs = 5 V, and L_G = 0.001–0.500 μH was applied. In Figure 5a, orange (V_ds,min,a) and gray curves (V_ds,max,a) are used for when L_D = 0.2 μH and blue (V_ds,min,b) and yellow curves (V_ds,max,b) for L_D = 1.0 nH to observe V_ds changes. A comparison of V_ds,min,a and V_ds,min,b values when L_G was changed from 0.001 μH to 0.5 μH revealed that V_ds,min,b was still approximately zero, whereas V_ds,min,a ranged from −1.33 V to −1.40 V. Because the drain terminal of the GS61004B was connected to L_D = 1 nH, the inductance was relatively low, with V_ds,max,b remaining at approximately 12 V; almost no change was observed. By contrast, when L_D = 0.2 μH, the inductance increased, with V_ds,max,a ranging between 72 V and 76 V. This shows that connecting the drain terminal of GS61004B to an inductor with excessively large inductance causes an increase in V_ds,max and V_ds,min.

The blue (V_gs,min,a) and red curves (V_gs,max,a) are used for when L_D = 0.2 μH, and the gray (V_ds,min,b) and yellow curves (V_ds,max,b) are used when L_D = 1.0 nH to observe changes of V_gs, as shown in Figure 5b. Before L_G reached 0.01 μH, V_gs,min,a ranged from −0.34 V to −0.49 V, but rose to −0.64–−0.81 V after L_G reached 0.01 μH. V_gs,min,b remained almost 0 before L_G reached 0.02 μH, but the range of V_gs,min,b rose to −0.73–−0.80 V after L_G reached 0.02 μH. When L_D was set to 0.2 μH, V_gs,max,a ranged from 5.00 V to 6.85 V; when L_D was set to 1.0 nH, V_ds,max,b ranged from 5.10 V to 6.97 V. Neither voltage value exceeded the specifications for GS61004B (V_gs,max = 7 V). Because the drain terminal of GS61004B was connected to L_D, no direct effect was exerted on V_gs,max and V_gs,min. The gate terminal of GS61004B was connected to L_G, which caused V_gs,max and V_gs,min to increase with the value of L_G.

3.3. Applying Different L_S Values to Measure the Changes of I_ds, V_ds, and V_gs When di/dt and dv/dt Occur

The parameter setting of I_ds = 2 A, L_G = 1 nH, f_s = 100 kHz, V_gs = 5 V, and L_S = 0.001–2.000 μH was applied. The blue curve (I_ds,min,a) is used when L_D = 0.2 μH and the orange curve (I_ds,min,b) is used when L_D = 1.0 nH to observe changes of I_ds. In Figure 6a, I_ds,min,a ranges from −1.40 A to −1.84 A, whereas the changes of I_ds,min,b are divided into three sections detailed as follows. In the first section, where L_S ranged from 0.001 to 0.010 μH, I_ds,min,b was approximately 0 A; in the second section, where L_S ranged from 0.01 μH to 0.1 μH, I_ds,min,b was between −0.11 A and −1.13 A; and in the third section, where L_S ranged from 0.1 μH to 2.0 μH, I_ds,min,b was between −1.13 A and −1.83 A. As shown in Figure 6a, when L_s = 0.01 μH and 1.00 μH, I_ds,min decreased sharply. Theses phenomena are elucidated as follows: As indicated by the blue curve, in the I_ds loop, the inductance value for the series connection of L_D = 0.20 μH and L_S = 0.01 μH was L_DS(blue) = 0.21 μH, and I_ds,min = −1.4 A; when L_D = 0.20 μH and L_S = 1.00 μH, L_DS(blue) = 1.20 μH and I_ds,min = −1.69 A. The inductance increased by 5.7 times from 0.21 μH to 1.20 μH, indicating a significant change in I_ds,min. As depicted by the orange curve, the inductance value for the series connection of L_D = 1 nH (0.001 μH) and L_S = 0.01 μH was L_DS(orange) = 0.011 μH, and I_ds,min = −0.1 A; when L_D = 1 nH (0.001 μH) and L_S = 1.00 μH, L_DS(orange) = 1.001 μH, and I_ds,min = −1.7 A. The inductance increased 91 times from 0.011 μH to 1.001 μH, indicating that the change in the I_ds,min was larger for the orange curve than for the blue curve.

In Figure 6b, the blue (V_ds,min,a) and orange curves (V_ds,max,a) are used when L_D = 0.2 μH and the gray and yellow curves are used when L_D = 1.0 nH to observe changes in V_ds. In the section where L_S was between 0.001 μH and 0.01 μH, V_ds,min,a ranged between −2.16 V and −2.49 V, whereas V_ds,max,a ranged between 76.47 V and 78.38 V. After L_S reached 0.01 μH, V_ds,min,a did not exhibit much variation, but V_ds,max,a rose considerably to 80.57–95.88 V. The value of V_ds,min,b approximated 0 until L_S reached 0.1 μH, which was when V_ds,min,b decreased from 0 to −2.50 V. Changes in V_ds,max,b may be divided into three sections: When L_S = 0.001–0.010 μH, 0.01–0.10 μH, and 0.1–0.3 μH, the corresponding ranges of V_ds,max,b were 12.01–13.15 V, 13.51–50.42 V, and 50.42–96.19 V, respectively. Because in the third section, V_ds,max,b was approximating 100 V, the subsequent experiment was terminated. According to the aforementioned experimental results, reducing L_D to 1 nH, maintaining L_S in the loop of I_ds, gradually increasing L_S caused I_ds,max, I_ds,min, V_ds,max, and V_ds,min to rise.

In Figure 6c, the blue curve (V_gs,min,a) is used when L_D = 0.2 μH, and the orange curve (V_gs,min,b) is used when L_D = 1.0 nH to observe changes of V_gs. V_gs,min,a began at −0.4 V and continued to drop until L_S reached 0.2 μH, after which it gradually stabilized and eventually remained at approximately −0.7 V. The variation in V_gs,min,b may be divided into two sections. When L_S = 0.001–0.1 μH, V_gs,min,b was −0.12–0 V, showing negligible variation. When L_S = 0.2–2.0 μH, V_gs,min,b was −0.73–−0.4 V. This experiment revealed that because L_S was not in the loop of V_gs, its effect on V_gs,min was limited.

3.4. Applying Different L_S Values to Measure the Changes of I_ds, V_ds, and V_gs When di/dt and dv/dt Occur

The parameter setting of I_ds = 1 A, L_G = 10 nH, L_D = L_S = 1 nH, V_gs = 5 V, and f_s = 100 kHz–2 MHz was applied. In Figure 7, the blue (V_ds,max), orange (V_gs,min), and gray (V_gs,max) curves are used to observe changes in both V_ds and V_gs,. V_ds,max was found to remain at approximately 15 V, V_gs,min remained at approximately −0.64 V, and V_gs,max varied from 5.61 V to 6.12 V. According to the experimental results, the parasitic capacitance of E-mode GaN HEMT was extremely low. Take GS61004B as an example, C_iss = 328 pF, C_oss = 133 pF, and C_Rss = 5 pF. This shows that the operating frequency of 100 kHz–2 MHz was suitable for GS61004B.

4. Framework and Application of Gate Driver Circuit

According to the aforementioned experimental results, connecting inductors with excessively large inductance in series to the circuit loop of V_gs and I_ds tends to aggravate the dv/dt and di/dt phenomena. To avoid drastic spikes in the voltage and current waveforms that may damage E-mode GaN HEMT, this study designed a gate driver circuit in the hope of protecting E-mode GaN HEMT by monitoring V_gs and I_ds values. In Figure 8, the gate driver circuit comprises a controller, an isolated driver (UCC21520), a gate driver (LM5113), a high-speed amplifier (AD8028), and a shunt resistor (R_S). When the pulse width modulation (PWM) signal of V_gs is switched from on to off, the controller detects the positive and negative trigger sources to ensure that V_gs does not exceed the range between +7 V and −4 V. When E-mode GaN HEMT is switched on or off, the controller detects I_ds changes through the shunt resistor to ensure that I_ds remains within the designated value range. When V_gs or I_ds exceeds the set range, the controller turns off the gate driver to avoid damage to the E-mode GaN HEMT. In addition, the gate driving circuit is composed of three terminals: A, B, and C. Terminal A is connected to the gate terminal of the E-mode GaN HEMT, Terminal B is connected to the source terminal of the E-mode GaN HEMT, and Terminal C is connected to other components (Figure 9).

In Figure 9, two gate driver circuits are installed to the synchronous buck converter, which is applied to a 48-V electric scooter system. Parameters applied to the synchronous buck converter are presented in

Table 3. Experimental parameters of Figure 9.

Symbol	Value	Unit
Vin(min)	36.8	V
Vin(max)	57.6	V
Po	120	W
Vo	12	V
Io	10	A
ΔVo/Vo	1	%
ΔIo/Io	10	%
fs	800	kHz
Duty ratio	0.18	-
L1	2.7	μH
Co	380	μF

. Figure 10a shows the PWM waveforms of Q_H and Q_L subject to no-load current; the green waveform shows that at a 0.18 duty cycle, the dv/dt at the negative terminal was −1.6 V. The red waveform indicates that, at a 0.77 duty cycle, the spike dv/dt at the negative terminal was −1.9 V. Figure 10b shows the PWM waveforms of Q_H and Q_L subject to a full-load current. The green waveform shows that at a 0.28 duty cycle, the dv/dt at the negative terminal was −1.6 V. The red waveform indicates that, at a 0.70 duty cycle, the dv/dt at the negative terminal was −3.6 V. Waveforms of the output voltage (V_o) and output current (I_o) of the synchronous buck converter are presented in Figure 11, where V_o = 12.2 V and I_o = 10.0 A, both of which meet the specifications in Table 3.

5. Conclusions

This study explored factors influencing the spike magnitude when di/dt and dv/dt occur to GS61004B. A gate drive circuit was designed and applied to the synchronous buck converter. The following conclusions were drawn from the experimental results.

• When the dv/dt of V_ds and the di/dt of I_ds are excessively large, the L_D of the I_ds circuit loop may first be reduced before L_S is reduced.
• When the dv/dt of V_gs is excessively large, the L_G of the V_gs circuit loop may first be reduced.
• When L_D, L_G, and L_S are maintained at a minimum value, the optimal operating frequency for GS61004B is 100 kHz–2 MHz.
• The gate driver circuit is suitable for 120-W synchronous buck converter.