Study on Characteristics of Enhancement-Mode Gallium-Nitride High-Electron-Mobility Transistor for the Design of Gate Drivers

An enhancement-mode gallium-nitride high-electron-mobility transistor (E-mode GaN HEMT) operated at high frequency is highly prone to current spikes (di/dt) and voltage spikes (dv/dt) in the parasitic inductor of its circuit, resulting in damage to the power switch. To highlight the phenomena of di/dt and dv/dt, this study connected the drain, source, and gate terminals in series with inductors (LD, LS, and LG, respectively). The objective was to explore the effects of di/dt and dv/dt phenomena and operating frequency (fS) on drain-to-source voltage (Vds), drain-to-source current (Ids), and gate-to-source voltage (Vgs). The experimental method comprised two projects: (1) establishment of a measurement system to assess the change of electrical characteristics of the E-mode GaN HEMT and (2) change of the fS and the inductances (i.e., LD, LS, and LG) in the circuit to measure the changes in Vds, Ids, and Vgs, thus summarizing the experimental results. According to the experimental results on electrical characteristics, a gate driver circuit may be designed to drive and protect the E-mode GaN HEMT while being actually applied to a 120-W synchronous buck converter with an output voltage of 12 V and an output current of 10 A.


Introduction
The gradual yearly increase of greenhouse gases has intensified global warming. Energy-saving and carbon reduction have become the primary development goals for each country. The demand for relevant regulations (e.g., the Energy Star Standard and California Energy Commission Appliance Efficiency Regulations) and the market in recent years have driven the continual development of high-efficiency and high-power-intensity power supply units [1,2]. Because wide-bandgap materials are characterized by high breakdown voltage and high electron mobility, which merit operation under high temperatures and high frequencies [3][4][5][6][7][8][9][10], they have enabled the development of power supply units to gradually transition from silicon power switches to wide-bandgap power switches [3][4][5].
Wide-bandgap semiconductors may be categorized by their internal structures into enhancement-mode gallium-nitride high-electron-mobility transistors (E-mode GaN HEMTs) and gallium-nitride high-electron-mobility transistors (GaN HEMTs) [11]. Table 1 presents a comparison between key parameters (static, dynamic, and reverse operation) of E-mode GaN HEMT and GaN HEMT. The following findings were revealed from the comparison: (1) regarding static parameters, E-mode GaN HEMT with a R DS(ON) value smaller than that of GaN HEMT yielded lower conduction loss. (2) Regarding dynamic parameters, both transistors are voltage-driven components that require charging and discharging of a parasitic inductor between gate-to-source and gate-to-drain terminals for conduction and cut-off. That is, because the total gate charge (Q G ), gate-source charge (Q GS ), Table 1. The key parameters compare the enhancement-mode gallium-nitride high-electron-mobility transistors (E-mode GaN HEMTs) with the GaN HEMT [12,13]. High-frequency operation subjects the parasitic inductor of the circuit to di/dt and dv/dt phenomena, which could entail oscillation in voltage and current waveforms and create electromagnetic interference. Serious electromagnetic interference can result in damage to the power switch [14].

Key Parameter E-Mode GaN HEMT GaN HEMT Unit
A measurement system was first established to assess the electrical characteristics of the E-mode GaN HEMT. Subsequently, to accentuate the di/dt and dv/dt phenomena, this study connected the drain, source, and gate terminals in series with inductors (L D , L S , and L G , respectively) and adjusted inductor values before measuring the waveform changes of V ds , I ds , and V gs . In addition, this study adjusted the operating frequency from 100 kHz to 2 MHz to measure the waveform changes of V ds and V gs . Based on the results from the electrical characteristic experiment, this study's aim was to design a gate driver circuit to drive the E-mode GaN HEMT while further protecting said transistor by monitoring the changes in V gs and I ds values.
In Sections 2 and 3, the measurement system and electrical characteristics of E-mode GaN HEMT are introduced, respectively. Section 4 details the circuit framework and application of the gate driver circuit, whereas Section 5 presents the conclusion.

Measuring System
When E-mode GaN HEMT is switched on or off, di/dt and dv/dt phenomena occur. Therefore, at various operating frequencies, load currents, and inductances, a measurement system was used to assess and record the changes in V ds , I ds , and V gs . Figure 1 Table 2.  Figure 1. The proposed measurement system to assess electrical characteristics of enhancement-mode gallium-nitride high-electron-mobility transistors (E-mode GaN HEMT).

Electrical Characteristics of E-mode GaN HEMT when di/dt and dv/dt Occur
Regarding Figure 2, the GS61004B component provided by GaN Systems was loaded into TINA-TI; after a circuit diagram ( Figure 2) was plotted, the Vds, Ids, and Vgs waveforms can be simulated. The

Electrical Characteristics of E-mode GaN HEMT when di/dt and dv/dt Occur
Regarding Figure 2, the GS61004B component provided by GaN Systems was loaded into TINA-TI; after a circuit diagram ( Figure 2) was plotted, the V ds , I ds , and V gs waveforms can be simulated. The simulation was performed in the condition of I ds = 2 A and f s = 150 kHz with the inductance parameters of L G = 100 nH, L D = 50 nH, and L S = 50 nH. The obtained waveforms of I D (I ds ), V ds , and V gs from the simulation are presented in Figure 3. To elucidate the exact time when di/dt and dv/dt occurred in the waveform, the maximum and minimum values of I ds were marked as I ds,max and I ds,min , respectively; the maximum and minimum values of V ds were denoted by V ds,max and V ds,min , respectively; and the maximum and minimum values of V gs were marked as V gs,max and V gs,min , respectively. Subsequent experiments were implemented and recorded according to the aforementioned rules. of LG = 100 nH, LD = 50 nH, and LS = 50 nH. The obtained waveforms of ID(Ids), Vds, and Vgs from the simulation are presented in Figure 3. To elucidate the exact time when di/dt and dv/dt occurred in the waveform, the maximum and minimum values of Ids were marked as Ids,max and Ids,min, respectively; the maximum and minimum values of Vds were denoted by Vds,max and Vds,min, respectively; and the maximum and minimum values of Vgs were marked as Vgs,max and Vgs,min, respectively. Subsequent experiments were implemented and recorded according to the aforementioned rules. The parameters presented in Figure 2, namely output current, operating frequency (fs), and inductors in series (i.e., LD, LS, and LG), were changed. In four testing conditions, the maximum and minimum values of Vds, Ids, and Vgs were measured and recorded to determine spike changes.

Applying Various LD Values to Measure the Changes in Ids and Vds when di/dt and dv/dt Occur
The parameter setting of LG = LS = 1 nH, fs = 100 kHz, Vgs = 5 V, and LD = 0.01-0.50 μH was applied. Figure 4a shows that under different Ids (ranging from 0.1 A to 2.0 A) and before LD achieved 0.1 μH, the Vds,max changes of the five curves exhibited a linear relationship. After LD exceeded 0.1 μH, Vds,max underwent a rapid change, where the Vds,max value of the blue and yellow curves approximated the specification of GS61004B (Vds,max = 100 V); at that point, the experiment was terminated to avoid  The parameters presented in Figure 2, namely output current, operating frequency (fs), and inductors in series (i.e., LD, LS, and LG), were changed. In four testing conditions, the maximum and minimum values of Vds, Ids, and Vgs were measured and recorded to determine spike changes.

Applying Various LD Values to Measure the Changes in Ids and Vds when di/dt and dv/dt Occur
The parameter setting of LG = LS = 1 nH, fs = 100 kHz, Vgs = 5 V, and LD = 0.01-0.50 μH was applied. Figure 4a shows that under different Ids (ranging from 0.1 A to 2.0 A) and before LD achieved 0.1 μH, the Vds,max changes of the five curves exhibited a linear relationship. After LD exceeded 0.1 μH, Vds,max underwent a rapid change, where the Vds,max value of the blue and yellow curves approximated the specification of GS61004B (Vds,max = 100 V); at that point, the experiment was terminated to avoid The parameters presented in Figure 2, namely output current, operating frequency (f s ), and inductors in series (i.e., L D , L S , and L G ), were changed. In four testing conditions, the maximum and minimum values of V ds , I ds , and V gs were measured and recorded to determine spike changes.

Applying Various L D Values to Measure the Changes in I ds and V ds when di/dt and dv/dt Occur
The parameter setting of L G = L S = 1 nH, f s = 100 kHz, V gs = 5 V, and L D = 0.01-0.50 µH was applied. Figure 4a shows that under different I ds (ranging from 0.1 A to 2.0 A) and before L D achieved 0.1 µH, the V ds,max changes of the five curves exhibited a linear relationship. After L D exceeded 0.1 µH, V ds,max underwent a rapid change, where the V ds,max value of the blue and yellow curves approximated the specification of GS61004B (V ds,max = 100 V); at that point, the experiment was terminated to avoid damaging the power switch. As presented in Figure 2, because the drain-and source-end of the GS61004B exhibited parasitic capacitance (C ds ), an RLC series network was formed with the loops of V dc , R dc , L D , C ds , and L S . Therefore, with the circuit parameters R dc = 6 Ω, L S = 1 nH, L D = 0.05-0.30 µH, and C ds = 105 pF [16], the damping ratio (ζ) [17] was calculated to be 0.137, 0.125, 0.116, 0.109, 0.102, 0.097, 0.069, and 0.056. The curve of I ds = 2 A in Figure 4a illustrates the relationship between L D and V ds,max . When ζ = 0.137 (L D = 0.05 µH), the V ds,max amplitude was low, whereas it was high when ζ = 0.056 (L D = 0.30 µH).
Electronics 2020, 9, 1573 5 of 11 to 3.0 μH and Points a′, b′, and c′ correspond to points a, b, and c in Figure 4a. The researcher continued to increase LD until the gray curve first yielded Vds,max = 98 V; the experiment for the gray curve was terminated. Subsequently, when the LD was increased to 3.0 μH, the orange and the light blue curves yielded Vds,max values of 77.19 V and 13.46 V, respectively, both of which are lower than Vds,max = 100 V.

Applying Different LG Values to Measure the Changes of Vds and Vgs When di/dt and dv/dt Occur
The parameter setting of Ids = 2 A, LS = 1 nH, fs = 100 kHz, Vgs = 5 V, and LG = 0.001-0.500 μH was applied. In Figure 5a, orange (Vds,min,a) and gray curves (Vds,max,a) are used for when LD = 0.2 μH and blue (Vds,min,b) and yellow curves (Vds,max,b) for LD = 1.0 nH to observe Vds changes. A comparison of Vds,min,a and Vds,min,b values when LG was changed from 0.001 μH to 0.5 μH revealed that Vds,min,b was still approximately zero, whereas Vds,min,a ranged from −1.33 V to −1.40 V. Because the drain terminal of the GS61004B was connected to LD = 1 nH, the inductance was relatively low, with Vds,max,b remaining at approximately 12 V; almost no change was observed. By contrast, when LD = 0.2 μH, the inductance increased, with Vds,max,a ranging between 72 V and 76 V. This shows that connecting the drain terminal of GS61004B to an inductor with excessively large inductance causes an increase in Vds,max and Vds,min.
The blue (Vgs,min,a) and red curves (Vgs,max,a) are used for when LD = 0.2 μH, and the gray (Vds,min,b) and yellow curves (Vds,max,b) are used when LD = 1.0 nH to observe changes of Vgs, as shown in Figure  5b. Before LG reached 0.01 μH, Vgs,min,a ranged from −0.34 V to −0.49 V, but rose to −0.64-−0.81 V after LG reached 0.01 μH. Vgs,min,b remained almost 0 before LG reached 0.02 μH, but the range of Vgs,min,b rose to −0.73-−0.80 V after LG reached 0.02 μH. When LD was set to 0.2 μH, Vgs,max,a ranged from 5.00 V to 6.85 V; when LD was set to 1.0 nH, Vds,max,b ranged from 5.10 V to 6.97 V. Neither voltage value exceeded the specifications for GS61004B (Vgs,max = 7 V). Because the drain terminal of GS61004B was connected to LD, no direct effect was exerted on Vgs,max and Vgs,min. The gate terminal of GS61004B was connected to LG, which caused Vgs,max and Vgs,min to increase with the value of LG. Subsequently, the V ds,max values of corresponding Points a (12.01 V), b (26.26 V), and c (60.49 V) on the gray, orange, and light blue curves, respectively, were found to not reach 100 V. Therefore, the researcher could continue to increase the L D for the three curves. In Figure 4b, L D ranges from 0.5 µH to 3.0 µH and Points a , b , and c correspond to points a, b, and c in Figure 4a. The researcher continued to increase L D until the gray curve first yielded V ds,max = 98 V; the experiment for the gray curve was terminated. Subsequently, when the L D was increased to 3.0 µH, the orange and the light blue curves yielded V ds,max values of 77.19 V and 13.46 V, respectively, both of which are lower than V ds,max = 100 V.

Applying Different L G Values to Measure the Changes of V ds and V gs When di/dt and dv/dt Occur
The parameter setting of I ds = 2 A, L S = 1 nH, f s = 100 kHz, V gs = 5 V, and L G = 0.001-0.500 µH was applied. In Figure 5a, orange (V ds,min,a ) and gray curves (V ds,max,a ) are used for when L D = 0.2 µH and blue (V ds,min,b ) and yellow curves (V ds,max,b ) for L D = 1.0 nH to observe V ds changes. A comparison of V ds,min,a and V ds,min,b values when L G was changed from 0.001 µH to 0.5 µH revealed that V ds,min,b was still approximately zero, whereas V ds,min,a ranged from −1.33 V to −1.40 V. Because the drain terminal of the GS61004B was connected to L D = 1 nH, the inductance was relatively low, with V ds,max,b remaining at approximately 12 V; almost no change was observed. By contrast, when L D = 0.2 µH, the inductance increased, with V ds,max,a ranging between 72 V and 76 V. This shows that connecting the drain terminal of GS61004B to an inductor with excessively large inductance causes an increase in V ds,max and V ds,min .
The blue (V gs,min,a ) and red curves (V gs,max,a ) are used for when L D = 0.2 µH, and the gray (V ds,min,b ) and yellow curves (V ds,max,b ) are used when L D = 1.0 nH to observe changes of V gs , as shown in Figure 5b. Before L G reached 0.01 µH, V gs,min,a ranged from −0.34 V to −0.49 V, but rose to −0.64-−0.81 V after L G reached 0.01 µH. V gs,min,b remained almost 0 before L G reached 0.02 µH, but the range of V gs,min,b rose to −0.73-−0.80 V after L G reached 0.02 µH. When L D was set to 0.2 µH, V gs,max,a ranged from 5.00 V to 6.85 V; when L D was set to 1.0 nH, V ds,max,b ranged from 5.10 V to 6.97 V. Neither voltage value exceeded the specifications for GS61004B (V gs,max = 7 V). Because the drain terminal of GS61004B was connected to L D , no direct effect was exerted on V gs,max and V gs,min . The gate terminal of GS61004B was connected to L G , which caused V gs,max and V gs,min to increase with the value of L G . Electronics 2020, 9, x FOR PEER REVIEW 6 of 11

Applying Different LS Values to Measure the Changes of Ids, Vds, and Vgs When di/dt and dv/dt Occur
The parameter setting of Ids = 2 A, LG = 1 nH, fs = 100 kHz, Vgs = 5 V, and LS = 0.001-2.000 μH was applied. The blue curve (Ids,min,a) is used when LD = 0.2 μH and the orange curve (Ids,min,b) is used when LD = 1.0 nH to observe changes of Ids. In Figure 6a In Figure 6b, the blue (Vds,min,a) and orange curves (Vds,max,a) are used when LD = 0.2 μH and the gray and yellow curves are used when LD = 1.0 nH to observe changes in Vds. In the section where LS was between 0.001 μH and 0.01 μH, Vds,min,a ranged between −2.16 V and −2.49 V, whereas Vds,max,a ranged between 76.47 V and 78.38 V. After LS reached 0.01 μH, Vds,min,a did not exhibit much variation, but Vds,max,a rose considerably to 80.57-95.88 V. The value of Vds,min,b approximated 0 until LS reached 0.1 μH, which was when Vds,min,b decreased from 0 to −2.50 V. Changes in Vds,max,b may be divided into three sections: When LS = 0.001-0.010 μH, 0.01-0.10 μH, and 0.1-0.3 μH, the corresponding ranges of Vds,max,b were 12.01-13.15 V, 13.51-50.42 V, and 50.42-96.19 V, respectively. Because in the third section, Vds,max,b was approximating 100 V, the subsequent experiment was terminated. According to the aforementioned experimental results, reducing LD to 1 nH, maintaining LS in the loop of Ids, gradually increasing LS caused Ids,max, Ids,min, Vds,max, and Vds,min to rise.
In Figure 6c  As depicted by the orange curve, the inductance value for the series connection of L D = 1 nH (0.001 µH) and L S = 0.01 µH was L DS(orange) = 0.011 µH, and I ds,min = −0.1 A; when L D = 1 nH (0.001 µH) and L S = 1.00 µH, L DS(orange) = 1.001 µH, and I ds,min = −1.7 A. The inductance increased 91 times from 0.011 µH to 1.001 µH, indicating that the change in the I ds,min was larger for the orange curve than for the blue curve.
In Figure 6b, the blue (V ds,min,a ) and orange curves (V ds,max,a ) are used when L D = 0.2 µH and the gray and yellow curves are used when L D = 1.0 nH to observe changes in V ds . In the section where L S was between 0.001 µH and 0.01 µH, V ds,min,a ranged between −2.16 V and −2.49 V, whereas V ds,max,a ranged between 76.47 V and 78.38 V. After L S reached 0.01 µH, V ds,min,a did not exhibit much variation, but V ds,max,a rose considerably to 80.57-95.88 V. The value of V ds,min,b approximated 0 until L S reached 0.1 µH, which was when V ds,min,b decreased from 0 to −2.50 V. Changes in V ds,max,b may be divided into three sections: When L S = 0.001-0.010 µH, 0.01-0.10 µH, and 0.1-0.3 µH, the corresponding ranges of V ds,max,b were 12.01-13.15 V, 13.51-50.42 V, and 50.42-96.19 V, respectively. Because in the third section, V ds,max,b was approximating 100 V, the subsequent experiment was terminated. According to the aforementioned experimental results, reducing L D to 1 nH, maintaining L S in the loop of I ds , gradually increasing L S caused I ds,max , I ds,min , V ds,max , and V ds,min to rise. Electronics 2020, 9, x FOR PEER REVIEW 7 of 11 L S (μH)  This experiment revealed that because L S was not in the loop of V gs , its effect on V gs,min was limited.

Applying Different L S Values to Measure the Changes of I ds , V ds , and V gs When di/dt and dv/dt Occur
The parameter setting of I ds = 1 A, L G = 10 nH, L D = L S = 1 nH, V gs = 5 V, and f s = 100 kHz-2 MHz was applied. In Figure 7, the blue (V ds,max ), orange (V gs,min ), and gray (V gs,max ) curves are used to observe changes in both V ds and V gs, . V ds,max was found to remain at approximately 15 V, V gs,min remained at approximately −0.64 V, and V gs,max varied from 5.61 V to 6.12 V. According to the experimental results, the parasitic capacitance of E-mode GaN HEMT was extremely low. Take GS61004B as an example, C iss = 328 pF, C oss = 133 pF, and C Rss = 5 pF. This shows that the operating frequency of 100 kHz-2 MHz was suitable for GS61004B.
Electronics 2020, 9, 1573 8 of 11 changes in both Vds and Vgs,. Vds,max was found to remain at approximately 15 V, Vgs,min remained at approximately −0.64 V, and Vgs,max varied from 5.61 V to 6.12 V. According to the experimental results, the parasitic capacitance of E-mode GaN HEMT was extremely low. Take GS61004B as an example, Ciss = 328 pF, Coss = 133 pF, and CRss = 5 pF. This shows that the operating frequency of 100 kHz-2 MHz was suitable for GS61004B.

Framework and Application of Gate Driver Circuit
According to the aforementioned experimental results, connecting inductors with excessively large inductance in series to the circuit loop of V gs and I ds tends to aggravate the dv/dt and di/dt phenomena. To avoid drastic spikes in the voltage and current waveforms that may damage E-mode GaN HEMT, this study designed a gate driver circuit in the hope of protecting E-mode GaN HEMT by monitoring V gs and I ds values. In Figure 8, the gate driver circuit comprises a controller, an isolated driver (UCC21520), a gate driver (LM5113), a high-speed amplifier (AD8028), and a shunt resistor (R S ). When the pulse width modulation (PWM) signal of V gs is switched from on to off, the controller detects the positive and negative trigger sources to ensure that V gs does not exceed the range between +7 V and −4 V. When E-mode GaN HEMT is switched on or off, the controller detects I ds changes through the shunt resistor to ensure that I ds remains within the designated value range. When V gs or I ds exceeds the set range, the controller turns off the gate driver to avoid damage to the E-mode GaN HEMT. In addition, the gate driving circuit is composed of three terminals: A, B, and C. Terminal A is connected to the gate terminal of the E-mode GaN HEMT, Terminal B is connected to the source terminal of the E-mode GaN HEMT, and Terminal C is connected to other components ( Figure 9).

Framework and Application of Gate Driver Circuit
According to the aforementioned experimental results, connecting inductors with excessively large inductance in series to the circuit loop of Vgs and Ids tends to aggravate the dv/dt and di/dt phenomena. To avoid drastic spikes in the voltage and current waveforms that may damage E-mode GaN HEMT, this study designed a gate driver circuit in the hope of protecting E-mode GaN HEMT by monitoring Vgs and Ids values. In Figure 8, the gate driver circuit comprises a controller, an isolated driver (UCC21520), a gate driver (LM5113), a high-speed amplifier (AD8028), and a shunt resistor (RS). When the pulse width modulation (PWM) signal of Vgs is switched from on to off, the controller detects the positive and negative trigger sources to ensure that Vgs does not exceed the range between +7 V and −4 V. When E-mode GaN HEMT is switched on or off, the controller detects Ids changes through the shunt resistor to ensure that Ids remains within the designated value range. When Vgs or Ids exceeds the set range, the controller turns off the gate driver to avoid damage to the E-mode GaN HEMT. In addition, the gate driving circuit is composed of three terminals: A, B, and C. Terminal A is connected to the gate terminal of the E-mode GaN HEMT, Terminal B is connected to the source terminal of the E-mode GaN HEMT, and Terminal C is connected to other components ( Figure 9).  In Figure 9, two gate driver circuits are installed to the synchronous buck converter, which is applied to a 48-V electric scooter system. Parameters applied to the synchronous buck converter are presented in Table 3. Figure 10a shows the PWM waveforms of QH and QL subject to no-load current; the green waveform shows that at a 0.18 duty cycle, the dv/dt at the negative terminal was −1.6 V. The red waveform indicates that, at a 0.77 duty cycle, the spike dv/dt at the negative terminal was −1.9 V. Figure 10b shows the PWM waveforms of QH and QL subject to a full-load current. The green waveform shows that at a 0.28 duty cycle, the dv/dt at the negative terminal was −1.6 V. The red waveform indicates that, at a 0.70 duty cycle, the dv/dt at the negative terminal was −3.6 V. Waveforms Figure 9. Application of gate driver circuit to the synchronous buck converter.
In Figure 9, two gate driver circuits are installed to the synchronous buck converter, which is applied to a 48-V electric scooter system. Parameters applied to the synchronous buck converter are presented in Table 3. Figure 10a shows the PWM waveforms of Q H and Q L subject to no-load current; the green waveform shows that at a 0.18 duty cycle, the dv/dt at the negative terminal was −1.6 V. The red waveform indicates that, at a 0.77 duty cycle, the spike dv/dt at the negative terminal was −1.9 V. Figure 10b shows the PWM waveforms of Q H and Q L subject to a full-load current. The green waveform shows that at a 0.28 duty cycle, the dv/dt at the negative terminal was −1.6 V. The red waveform indicates that, at a 0.70 duty cycle, the dv/dt at the negative terminal was −3.6 V. Waveforms of the output voltage (V o ) and output current (I o ) of the synchronous buck converter are presented in Figure 11, where V o = 12.2 V and I o = 10.0 A, both of which meet the specifications in Table 3. Table 3. Experimental parameters of Figure 9. of the output voltage (Vo) and output current (Io) of the synchronous buck converter are presented in Figure 11, where Vo = 12.2 V and Io = 10.0 A, both of which meet the specifications in Table 3.

Symbol
High side E-mode GaN HEMT Duty Ratio=0.18 Low side E-mode GaN HEMT Duty Ratio=0.77 High side E-mode GaN HEMT Duty Ratio=0.28 Low side E-mode GaN HEMT Duty Ratio=0.70   . Waveforms of output voltage and output current. 5 V/div, 5 A/div, time: 100 ms/div. Table 3. Experimental parameters of Figure 9.

Conclusions
This study explored factors influencing the spike magnitude when di/dt and dv/dt occur to GS61004B. A gate drive circuit was designed and applied to the synchronous buck converter. The following conclusions were drawn from the experimental results.