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Open AccessFeature PaperArticle

Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

School of Electric Engineering, Soongsil University, 369, Sangdo-ro, Dongjak-gu, Seoul 06978, Korea
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Electronics 2020, 9(1), 103; https://doi.org/10.3390/electronics9010103
Received: 15 December 2019 / Revised: 27 December 2019 / Accepted: 2 January 2020 / Published: 6 January 2020
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s. View Full-Text
Keywords: CMOS; linearity; power amplifier CMOS; linearity; power amplifier
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Kim, J.; Lee, C.; Yoo, J.; Park, C. Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity. Electronics 2020, 9, 103.

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