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Article

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

1
Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
2
Hewlett Packard Enterprise, Palo Alto, CA 94304-1112, USA
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(2), 210; https://doi.org/10.3390/electronics8020210
Received: 19 December 2018 / Revised: 4 February 2019 / Accepted: 11 February 2019 / Published: 13 February 2019
(This article belongs to the Section Microwave and Wireless Communications)
This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase. View Full-Text
Keywords: Electrostatic Discharge (ESD); Dynamic Random Access Memory (DRAM); ESD gun; 3D model; numerical model; system level ESD Electrostatic Discharge (ESD); Dynamic Random Access Memory (DRAM); ESD gun; 3D model; numerical model; system level ESD
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MDPI and ACS Style

Yousaf, J.; Faisal, M.; Youn, J.; Nah, W. Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules. Electronics 2019, 8, 210. https://doi.org/10.3390/electronics8020210

AMA Style

Yousaf J, Faisal M, Youn J, Nah W. Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules. Electronics. 2019; 8(2):210. https://doi.org/10.3390/electronics8020210

Chicago/Turabian Style

Yousaf, Jawad, Muhammad Faisal, Jinsung Youn, and Wansoo Nah. 2019. "Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules" Electronics 8, no. 2: 210. https://doi.org/10.3390/electronics8020210

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