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Keywords = ESD gun

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14 pages, 1670 KB  
Article
Rise Time and Peak Current Measurement of ESD Current from Air Discharges with Uncertainty Calculation
by Georgios Fotis, Vasiliki Vita and Theodoros I. Maris
Electronics 2022, 11(16), 2507; https://doi.org/10.3390/electronics11162507 - 11 Aug 2022
Cited by 2 | Viewed by 4287
Abstract
The greater number of electrostatic discharges (ESDs) that occur in nature is by air rather than by contact. However, due to low reproducibility in the current of air discharges, the IEC 61000-4-2 defines that the current’s calibration of an ESD gun must be [...] Read more.
The greater number of electrostatic discharges (ESDs) that occur in nature is by air rather than by contact. However, due to low reproducibility in the current of air discharges, the IEC 61000-4-2 defines that the current’s calibration of an ESD gun must be made only for contact discharges. In the work presented here, there is an attempt to improve the poor reproducibility of air discharges by a significant observation derived from ESD measurements and, more specifically, the relationship between the rise time and the peak current for every ESD gun. This fact validated in this paper from current measurements of two different ESD guns will help all who are involved in ESD measurements in EMC laboratories by reducing the existing uncertainty in measurements of air discharges. Full article
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25 pages, 6020 KB  
Article
Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules
by Jawad Yousaf, Muhammad Faisal, Jinsung Youn and Wansoo Nah
Electronics 2019, 8(2), 210; https://doi.org/10.3390/electronics8020210 - 13 Feb 2019
Cited by 3 | Viewed by 5658
Abstract
This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) [...] Read more.
This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase. Full article
(This article belongs to the Section Microwave and Wireless Communications)
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