Search Results (73)

This study focuses on the evaluation of electrical stress limit capability for 3D-packaged memory (256 M × 72-bit DDR3 SDRAM) (Shanghai Fudan Microelectronics Group Co., Ltd., Shanghai, China). Guided by Reliability Enhancement Theory, this study presents a meticulously designed comprehensive test profile that incorporates critical stress parameters, including supply voltage, input clock frequency, electrostatic discharge (ESD) sensitivity, and electrical endurance. Explicit criteria for stress selection, upper/lower bounds, step increments, and duration are established. A dedicated test platform is constructed, integrating automated test equipment (ATE) and ESD sensitivity analyzers with detailed specifications on device selection criteria and operational principles. The functional performance testing methodology is systematically investigated, covering test platform configuration, initialization protocols, parametric testing procedures, functional verification, and acceptance criteria. Extreme-condition experiments—including supply voltage margining, input clock frequency tolerance, ESD sensitivity characterization, and accelerated electrical endurance testing—are conducted to quantify operational and destructive limits. The findings provide critical theoretical insights and practical guidelines for the design optimization, quality control, and reliability enhancement of 3D-packaged memory devices. Full article

This paper introduces a 0.5–5.8 GHz low-noise amplifier (LNA) incorporating a gyrator-C-based active inductor (AI) and an enhanced deep trench isolation (DTI) electrostatic discharge (ESD) diode. Results suggest that AIs exhibit excellent consistency under various process voltage temperatures (PVTs) as well as input powers and the improved DTI diodes reduce parasitic capacitance by an average of 8.5% compared to conventional ones. In terms of circuit design, comprehensive analyses of gain flatness and noise are conducted. Fabricated using a 0.18 μm SiGe BiCMOS technology, the LNA delivers a high S21 of 18.3 ± 0.3 dB, a minimum noise figure of 2.6 dB, and an S11 and S22 of less than −10 dB over the entire frequency band. Operating from a 3.3 V supply voltage with a core area of 0.049 mm², it consumes 10 mA of current. Full article

This paper presents a wideband low-power/low-voltage 60-GHz low-noise amplifier (LNA) in a 28-nm bulk CMOS technology. The LNA has been designed for high-speed millimeter-wave (mm-wave) communications. It consists of two pseudo-differential amplifying stages and a buffer stage included for 50-Ohm on-wafer measurements. Two integrated input/output baluns guarantee both simultaneous 50-ohm input–noise/output matching at input/output radio frequency (RF) pads. A power-efficient design strategy is adopted to make the LNA suitable for low-power applications, while minimizing the noise figure (NF). Thanks to the adopted design strategy, the post-layout simulation results show an excellent trade-off between power gain and 3-dB bandwidth (BW_3dB) with 13.5 dB and 7 GHz centered at 60 GHz, respectively. The proposed LNA consumes only 11.6 mA from a 0.9-V supply voltage with an NF of 8.4 dB at 60 GHz, including the input transformer loss. The input 1 dB compression point (IP_1dB) of −15 dBm at 60 GHz confirms the first-rate linearity of the proposed amplifier. Human body model (HBM) electrostatic discharge (ESD) protection is guaranteed up to 2 kV at the RF input/output pads thanks to the input/output integrated transformers. Full article

In this study, a single-pole double-throw (SPDT) switch for Sub-6 GHz application is designed. In particular, a shunt inductor is connected to the antenna port of the switch for ESD (electrostatic discharge) protection in RF (radio frequency) front end module. The shunt inductor not only serves as an ESD protection device, but also serves as a component of a parallel resonance circuit to suppress insertion loss of the switch. In addition, in order to secure the power handling capability, transistors turned off in the transmit (Tx) mode are implemented as quadruple-gate transistors. An SPDT switch is fabricated using GaAs pHEMT provided in the 500 nm GaAs BiFET process to verify the feasibility of the proposed switch structure. The operating frequency is set from 3 GHz to 5 GHz. The insertion loss and isolation measured in the Tx mode are lower than 0.35 dB and higher than 31.6 dB, respectively. The insertion loss and isolation measured in the Rx mode are lower than 0.32 dB and higher than 33.9 dB, respectively. The chip size including test pads is 0.890 × 0.875 mm². Full article

This paper proposes a monolithic electrostatic discharge/electrical overstress (ESD/EOS) co-protection device featuring gradual triggering by silicon-controlled rectifier (SCR) and metal–oxide semiconductor (MOS) structures, demonstrating enhanced voltage clamping and current-conducting capabilities. Compared with conventional PMOS-triggered SCR (PMOS-SCR) for ESD protection, the proposed dual-PMOS-triggered SCR (DPMOS-SCR) architecture within a compact area achieves monolithic ESD/EOS protection performance due to the strategic semiconductor structures integration. ESD measurement results show that the snapback voltage of the designed DPMOS-SCR with the width of 170 μm is approximately 2.5 V, the failure current (I_t2) is up to 4.5 A, and both the simulation and measurement results demonstrate that the designed DPMOS-SCR is helpful for reducing the leakage current and accelerating the response time. By embedding an additional p-type well in the DPMOS-SCR, the optimized DPMOS-SCR (ODPMOS-SCR) presents a higher breakdown voltage, trigger voltage, and holding voltage while keeping a similar I_t2. The EOS current-conducting ability measured by a surge test system indicates the peak surge current is up to 3.7 A, demonstrating superior monolithic ESD/EOS protection performance. As a result, the designed DPMOS-SCR and ODPMOS-SCR structures achieve high-voltage ESD/EOS co-protection with high efficiency in a small chip area, providing a chip-scale solution for improving the reliability of high-voltage ICs. Full article

Standards describing the test procedures recommended to investigate the shielding effectiveness of enclosures have two major issues: they generally prescribe the assessment of the electromagnetic field of empty cavities, and they do not deal with very small enclosures. However, the dimensions of some very common shielded apparatus are smaller than those considered in the standards and the electromagnetic field distribution inside the shielded structure is strongly affected by the enclosure content. In this paper, both issues have been investigated for two components commonly used in medium voltage/low voltage (MV/LV) substations: a mini personal computer used to store, process, and transmit relevant data on the status of the electric network, with these aspects being essential in smart grids, and an electronic relay which is ubiquitous in MV/LV substations. Both components are partially contained in a metallic enclosure which provides a certain amount of electromagnetic shielding against external interferences. It is observed that an electrostatic discharge may cause a failure and/or a loss of data, requiring an improvement of shielding characteristics or a wise choice of the positions where the most sensitive devices are installed inside the enclosure. Since the dimensions of very small enclosures, fully occupied by their internal components, do not allow for the insertion of sensors inside the protected volume, numerical analysis is considered as the only way for the appraisal of the effects induced by a typical source of interference, such as an electrostatic discharge. Full article

This work develops a novel compact Silicon-Controlled Rectifier (SCR) model incorporating self-heating effects, extending the conventional Ebers–Moll (E–M) framework for Bipolar Junction Transistors (BJTs) by comprehensively integrating parasitic effects. The temperature dependence of critical device parameters, including junction capacitances, emitter resistances, and saturation currents, is systematically characterized to accurately predict the device’s electrical behavior under Electrostatic Discharge (ESD) stress. Furthermore, a self-heating modeling approach is introduced based on the SCR layout characteristics. The impact of self-heating on SCR transient response was verified by comparing simulation results with measurements from SCR devices fabricated in a 0.18 µm Bipolar-CMOS-DMOS (BCD) process. Comparative analysis demonstrates superior accuracy over existing models. The proposed SCR model includes a complete definition of parameters and electrical relationships, ensuring compatibility with various Electronic Design Automation (EDA) platforms. Full article

Space particle radiation induces charging and discharging phenomena in spacecraft dielectric materials, leading to electrostatic discharge (ESD) and electromagnetic pulses (EMP), which pose significant risks to spacecraft electronic systems by causing interference and potential damage. Accurate and timely monitoring of these phenomena, combined with a comprehensive understanding of their underlying mechanisms, is critical for developing effective protection strategies against satellite charging effects. Addressing in-orbit monitoring requirements, this study proposes the design of a compact sleeve monopole antenna. Through simulations, the relationships between the antenna’s design parameters and its voltage standing wave ratio (VSWR) are analyzed alongside its critical performance characteristics, including frequency band, gain, radiation pattern, and matching circuit. The proposed antenna demonstrates operation within a frequency range of (28.73–31.25) MHz (VSWR < 2), with a center frequency of 30 MHz and a relative bandwidth of 8.4%. Performance evaluations and simulation-based experiments reveal that the antenna can measure pulse signals with electric field strengths ranging from (−1000 to −80) V/m and (80 to 1000) V/m, centered at 25.47 MHz. It reliably monitors discharge pulses generated by electron irradiation on spacecraft-grade FR4 (Flame-Retardant 4) dielectric materials, providing technical support for the engineering application of discharge research in space environments. Full article

Ariel (Atmospheric Remote-sensing Infrared Exoplanet Large-survey) is the ESA Cosmic Vision M4 mission, selected in March 2018 and officially adopted in November 2020, whose launch is scheduled by 2029. It aims at characterizing the atmospheres of hundreds of exoplanets orbiting nearby stars by low-resolution primary and secondary transit spectroscopy. The Ariel spacecraft’s operational orbit is baselined as a large-amplitude, eclipse-free halo orbit around the second Lagrangian (L2) point, a virtual point located at about 1.5 million km from the Earth in the anti-Sun direction, as it offers the possibility of long uninterrupted observations in a fairly stable radiative and thermo-mechanical environment. A direct escape injection with a single passage through the Van Allen radiation belts is foreseen. During both the injection trajectory and the final orbit around L2, Ariel will be immersed in and interact with Sun radiation and the plasma environment. These interactions usually result in the accumulation of net electrostatic charge on the external surfaces of the spacecraft, leading to a potentially hazardous configuration for the nominal operation and survivability of the Ariel platform and its payload, as it may induce harmful electrostatic discharges (ESDs). This work presents the latest results collected from surface charging analyses conducted using the SPIS tool of the European SPINE community along the GEO insertion orbit segment and operational orbit. Full article

Exposure to space radiation substantially degrades satellite systems, provoking severe partial or, in some extreme cases, total failures. Electrostatic discharges (ESD), single event latch-up (SEL), and single event upsets (SEU) are among the most frequent causes of those reported satellite anomalies. The impact of space radiation dose on satellite equipment has been studied in-depth. This study conducts a statistical analysis to explore the relationships between low-Earth orbit (LEO) and geostationary orbit (GEO) satellite anomalies and particle concentrations, solar and geomagnetic activity in the period 2010–2022. Through a monthly and daily timescale analysis, the present work explores the temporal response of space disturbances on satellite systems and the periods when satellites are vulnerable to those disturbances. Full article

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP_1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection. Full article

Both nanoscience and nanotechnology have undoubtedly contributed significantly to the development of thermite-based nanoenergetic materials (NEMs) with tunable and tailorable combustion performance and their subsequent integration into devices. Specifically, this review article reflects the immense paybacks in designing and fabricating ordered/disordered assembly of energetic materials over multiple length scales (from nano- to milli-scales) in terms of realization of desired reaction rates and sensitivity. Besides presenting a critical review of present advancements made in the synthesis of NEMs, this article touches upon aspects related to various applications concomitantly. The article concludes with the author’s summary of the insurmountable challenges and the road ahead toward the deployment of nanoenergetic materials in practical applications. The real challenge lies in the ability to preserve the self-assembly of fuel and oxidizer nanoparticles achieved at the nanoscale while synthesizing macroscale energetic formulations using advanced fabrication techniques both in bulk and thin film forms. Most importantly, these self-assembled NEMs have to exhibit excellent combustion performance at reduced sensitivity to external stimuli such as electrostatic discharge (ESD), friction and impact. Full article

On-chip electrostatic discharge (ESD) protection poses a challenge in the chip fabrication process. In this study, a novel electric fuse (E-fuse) device featuring a simple structure of Ni metal on a SiO₂ dielectric for ESD protection was proposed, and the physical mechanism of its operation was investigated in detail. Experimental evaluations, utilizing transmission line pulse (TLP) testing and fusing performance analyses, reveal that the E-fuse, constructed with a Ni metal layer measuring 5 μm in width, 100 μm in length, and 5 nm in thickness, achieved a significant ESD protection voltage of 251 V (V_HBM) and demonstrates low-voltage fusing at a bias voltage of 7 V. Compared to traditional ESD protection devices, the E-fuse boasts a smaller size and removability. To assess fusing performance, devices of varying sizes were tested using a fusing lifetime model. This study supports both theoretical and empirical evidence, enabling the adoption of cost-effective, straightforward E-fuse devices for ESD protection. Full article

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. Full article

This article discusses the important issue of designing textiles for electrostatic discharge (ESD) protection. ESD protective textiles are used to prevent the failure of electronic circuits. They also safeguard human health and life in explosive environments. The textiles are usually made of woven, knitted, or nonwoven fabrics incorporating a grid or strips of conductive fibers within a base material made of cotton, polyester, or blends of these materials. Various testing standards have been developed to evaluate the suitability of textiles for ESD protection. One of the most widely used is the EN 1149-3 standard, which outlines procedures for recording charge decay plots. The procedure can be used to evaluate all types of textiles. This paper discusses models corresponding to the standard developed in the general-purpose COMSOL Multiphysics software. Using the advanced numerical methods of the software, it is possible to graphically present the phenomena occurring during the application of the standard procedure and to determine the influence of the grid and material parameters on the shape of the charge decay plots. Furthermore, this article compares charge decay plots and shielding effectiveness measured in an accredited laboratory with simulation results. Full article