Review Reports

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Here are my opinions.

1. The author declares that the full bridge converter operating in hard switching will reduce the control bandwidth. I think this is not rigorous. The hard switching itself is not related to the design of the controller, but rather limits the switching frequency.
2. Based on full bridge converters, such as DAB, resonant converters can also achieve soft switching. And the proposed converter has a large number of switches. So does it have significant advantages. Suggest the author to provide detailed comparisons, such as voltage/current stress and losses, etc.
3. The analysis of the half bridge part of the converter and the traditional resonant converter seems to be consistent. So what's the difference between them?
4. Suggest the author to reduce the simulation content and supplement more experimental results.
5. The references also need to be further supplemented, especially regarding flat top topology.

Author Response

Comment 1:

       The author declares that the full bridge converter operating in hard switching will reduce the control bandwidth. I think this is not rigorous. The hard switching itself is not related to the design of the controller, but rather limits the switching frequency.

 

Author’s response:

The reviewer's observation is correct and well-taken. The causal chain in the original text was insufficiently precise. Hard-switching operation does not directly constrain the controller design; rather, it imposes an upper bound on the switching frequency due to the proportional increase in switching losses with frequency. A lower switching frequency in turn limits the current ripple attenuation bandwidth and slows the dynamic response of the current regulation loop.

Original: "...which restricts the control bandwidth and   results in a flat-top current stability of approximately   1%."    

[REVISED]: "...which limits the achievable switching   frequency. Operating at a reduced switching frequency   weakens the current ripple attenuation capability and   slows the dynamic response of the regulation loop,   resulting in a flat-top current stability of   approximately 1%." Page2 , line 62.

 

Comment 2:

       Based on full bridge converters, such as DAB, resonant converters can also achieve soft switching. And the proposed converter has a large number of switches. So does it have significant advantages? Suggest the author to provide detailed comparisons, such as voltage/current stress and losses, etc.

 Author’s response:

We thank the reviewer for raising this important point. The proposed  AHB-Flyback topology differs from alternative soft-switching  solutions in three respects that are particularly relevant to the  target application:

(1) Switch count and circuit complexity: The AHB-Flyback primary  stage uses only two active switches (Q1, Q2), compared with four  switches in a full-bridge DAB or full-bridge LLC. The additional  switches on the secondary side (S_Charge, S_Drain, S_Discharge,  S1–S4) serve the energy management and bipolar output functions  that are unique to this application and would be required in any  topology deployed here.

(2) Device voltage stress: The primary-side voltage stress is  clamped to V_dc (390 V), identical to a full-bridge topology. The  secondary H-bridge devices (S1–S4), however, only need to block  the storage capacitor voltage V_chset (approximately 71 V at the  rated operating point), which is far lower than V_dc. This  asymmetry allows the use of low-voltage, low-R_DS(on) devices on  the secondary side.

(3) Applicability of DAB to this application: Although DAB can  achieve ZVS, maintaining soft switching over the wide bipolar  current range required here (±100 A) is constrained by the  phase-shift angle limits: at low output currents the required  phase shift becomes small and the ZVS boundary condition is  violated.

[REVISED] A comparative discussion has been added to  Section 3 (Parameter Calculation), including a qualitative  comparison table listing switch count, primary switch voltage  stress, and the applicability of decoupled energy management  for the proposed topology versus a conventional H-bridge and  a full-bridge LLC. Page19, line 454.

 

Comment 3:

The analysis of the half bridge part of the converter and the traditional resonant converter seems to be consistent. So what is the difference between them?

Author’s response:

The reviewer correctly identifies that the FHA-based gain derivation in Section 2.2 is formally analogous to that of a standard LLC converter. Two distinctions of the proposed circuit relative to both a conventional LLC and a traditional AHB-Flyback are worth emphasizing:

(1) Duty-cycle modulation of the input fundamental: In a symmetric half-bridge LLC, Q1 and Q2 operate at D = 0.5, and the input fundamental amplitude is fixed at (2/pi)*V_dc. In the proposed AHB-Flyback, Q1 and Q2 operate complementarily with duty cycles D and (1-D), introducing the modulation factor sin(pi*D) into the input fundamental (Equation (1)). This provides a second independent control degree of freedom that a conventional LLC does not possess, enabling gain adjustment without solely relying on frequency variation.

(2) Non-negligible resonant inductance: Traditional AHB- Flyback converters assume L_m >> L_r, so that the gain is determined by the volt-second balance on L_m and is essentially duty-cycle-dependent only. The present circuit introduces an explicit resonant inductor L_r of the same order of magnitude as L_m (k = L_m/L_r = 3), so the gain becomes a function of both f_n and D simultaneously, as expressed in Equation (5). This is why a re-derivation of the gain model was necessary.

[REVISED] A dedicated paragraph has been added at the end of Section 2.2 explicitly summarizing these two distinctions. Page 6, line 167.

 

Comment 4:

Suggest the author to reduce the simulation content and supplement more experimental results.

Author’s response:

We thank the reviewer for this constructive suggestion. In the revised manuscript, the simulation content has been reduced and the experimental validation has been further strengthened.

[REVISED]On the simulation side, the soft-switching waveform presentation has been simplified. Instead of showing a large number of repetitive simulation waveforms at different operating points, only the representative soft-switching results at Iref=20 A and 100 A are retained in the revised manuscript. This revision reduces redundancy while preserving the key evidence needed to verify the ZVS/ZCS operating characteristics of the proposed topology. Page 21, Figure. 18.

On the experimental side, two additional aspects have been included. First, a new efficiency analysis subsection has been added, including the efficiency comparison between simulation and experiment under the scaled experimental condition. Second, an additional measured waveform has been provided to show the dynamic response from the end of the rise stage to the stable flat-top region, which is the application-relevant transient process for the present ECR adjustment-coil power supply. Page 24, line 546. Page 27, line 641.

 

Comment 5:

The references also need to be further supplemented, especially regarding flat-top topology.

Author’s response:

The reference list has been expanded with additional recent publications (post-2020) directly related to ion source and flat-top pulsed field power supply topologies.Page 1, line 34.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

My review comments are as follows:
I. The derivations for semiconductor devices are based on ideal assumptions and do not adequately consider parasitic effects, which can directly affect the accuracy of the mathematical analysis.
II. The authors should provide more accurate and detailed mathematical analyses for the different operating states of the proposed circuit topology over various time intervals, clearly showing the charging and discharging behavior of the resonant elements through the corresponding equations.
III. The authors are encouraged to present gain characteristics as a function of the ratio of switching frequency to resonant frequency (fs/fo).
IV. The literature review is insufficient, and the introduction section should be expanded. Recent SCIE-indexed papers published after 2020 that are directly related to this topic should be incorporated.
V. In the experimental results section, reference voltage or current values for the presented waveforms should be specified. For instance, in Figure 22, although V/div or A/div is indicated, the actual minimum and maximum values of the signals are not clearly defined.
VI. One of the most significant drawbacks of this study is that it does not include an efficiency analysis for the proposed system. The converter topology needs to present efficiency curves versus the duty ratio of the switches and the output power level to demonstrate whether its applicability is justified or not. https://onlinelibrary.wiley.com/doi/abs/10.1002/fuce.70043
 and https://www.sciencedirect.com/science/article/abs/pii/S0142061520313958 are two comprehensive studies for efficiency calculations, and the authors are encouraged to consider them in the efficiency analysis section of the paper. Furthermore, the authors need to include both simulation and experimental efficiency results, along with proper comparisons.
VII. The following important validations are missing: dynamic response under load and transient conditions, thermal performance analysis (such as temperature rise or thermal imaging), and long-term operation or reliability testing.

Author Response

Comment 1:

       The derivations for semiconductor devices are based on ideal assumptions and do not adequately consider parasitic effects, which can directly affect the accuracy of the mathematical analysis.

 

Author’s response:

The reviewer raises a valid concern. The time-domain analytical model presented in Section 2.3 is indeed based on idealized assumptions, including lossless switches, ideal transformer coupling, and zero dead time. These assumptions are standard practice in the first-principles analysis of resonant converter operating modes and are consistent with the methodology of the reference works cited in the paper (e.g., Spiazzi and Buso, 2021; Li et al., 2020).

[REVISED] A dedicated paragraph has been added at the beginning of Section 2.3 explicitly stating the modeling assumptions:

 "The following analysis assumes: (1) all switching devices are ideal with zero on-state voltage drop and instantaneous switching transitions; (2) the transformer is modeled by its magnetizing inductance L_m and an ideal turns ratio N, with winding resistance neglected; (3) dead time is negligible relative to the switching period (at 100 kHz with a dead time of approximately 100 ns, the dead-time fraction is less than 1%); (4) the resonant capacitor voltage varies negligibly within the short duration of each sub-interval transition. The impact of these simplifications on model accuracy is assessed through comparison with PLECS simulation results, which inherently include device non-idealities, in Section 4."

 Page 6, line 193.

The close agreement between the analytical predictions and simulation results (Mode 3 duration errors within ±2% across the 20–100 A range, as shown in Table 2) confirms that the idealized model provides sufficient accuracy for design purposes under the stated conditions.

 

Comment 2:

       The authors should provide more accurate and detailed mathematical analyses for the different operating states of the proposed circuit topology over various time intervals, clearly showing the charging and discharging behavior of the resonant elements through the corresponding equations.

 Author’s response:

We appreciate this suggestion.

[REVISED]In the revised manuscript, the mode-by-mode description in Section 2.3 has been substantially expanded. For each of the five flat-top maintenance modes (and the four charging-stage modes), the primary resonant loop KVL equations, secondary-side load-loop equations, and the magnetomotive-force balance across the transformer are now presented together. The time-domain solutions for i_Lr, v_Cr, i_Lm, i_out, i_load, and i_DS are all provided, along with the mode-transition conditions. This enables the reader to trace the charging and discharging behavior of each resonant element and the commutation between the transformer output and the freewheeling diode throughout the switching cycle.

 Page 9, line 247.

 

Comment 3:

The authors are encouraged to present gain characteristics as a function of the ratio of switching frequency to resonant frequency (fs/fo).

Author’s response:

We thank the reviewer for this constructive suggestion and have substantially revised Section 3.2 in response. In the original submission, the gain was plotted against the Mode 3 duty cycle D_T3 using a simplified expression valid only near f_s = f_LC.

[REVISED]To properly present the gain characteristic as a function of the frequency ratio f_s/f_o as requested, we have derived the full normalized gain expression (Equation 58), which retains the frequency-dependent term (2π f_s)^2 L_r C_r omitted in the original simplification. However, the full expression contains arcsine and nested square-root terms that make it unwieldy as a design aid. We therefore apply a Taylor expansion of the arcsine function and demonstrate that retaining terms through order x^{3/2}, where x = K f_n, yields a compact closed-form approximation (Equation 62) that preserves the essential resonant behavior. The approximation is shown to coincide with the full expression in the operating frequency range (Figure 16). The nominal flat-top operating point (f_n slightly above unity, in the inductive ZVS region) is explicitly marked on the gain curve, and the minimum gain that defines the maximum-stable-output-current boundary is discussed in the context of the wide-range design requirement.

 Page 16, line 384.

 

Comment 4:

The literature review is insufficient, and the introduction section should be expanded. Recent SCIE-indexed papers published after 2020 that are directly related to this topic should be incorporated.

Author’s response:

The reference list has been expanded with additional recent publications (post-2020) directly related to ion source and flat-top pulsed field power supply topologies. Page 1, line 34.

 

Comment 5:

In the experimental results section, reference voltage or current values for the presented waveforms should be specified. For instance, in Figure 22, although V/div or A/div is indicated, the actual minimum and maximum values of the signals are not clearly defined.

Author’s response:

The reviewer's observation is valid. In oscilloscope screenshots, the V/div and A/div scaling alone is insufficient for the reader to determine absolute signal values without knowing the vertical offset of each channel.

 [REVISED] In the revised manuscript, the experimental waveform figures have been updated by adding direct annotations of the key maximum and minimum values of the main traces, as shown in the revised figures. This makes the absolute signal levels and fluctuation ranges easier to read, instead of requiring the reader to infer them only from the V/div or A/div settings.

Page 23, Figure. 21 to Figure. 24.

 

Comment 6:

One of the most significant drawbacks of this study is that it does not include an efficiency analysis for the proposed system. The converter topology needs to present efficiency curves versus the duty ratio of the switches and the output power level to demonstrate whether its applicability is justified or not. https://onlinelibrary.wiley.com/doi/abs/10.1002/fuce.70043

 and https://www.sciencedirect.com/science/article/abs/pii/S0142061520313958 are two comprehensive studies for efficiency calculations, and the authors are encouraged to consider them in the efficiency analysis section of the paper. Furthermore, the authors need to include both simulation and experimental efficiency results, along with proper comparisons.

Author’s response:

We thank the reviewer for this important observation and for providing the two reference works on efficiency calculation methodology. We acknowledge that the absence of efficiency analysis is a significant omission and have addressed it as follows.

[REVISED] A new subsection "Efficiency Analysis" has been added in Section 4, structured as follows:

(1) Loss decomposition model: Following the methodology of the referenced works (doi:10.1002/fuce.70043 and doi:10.1016/j.ijepes.2020.106584), the total converter loss is decomposed into: (a) primary switch turn-on loss (zero under ZVS, confirmed analytically and by simulation); (b) primary switch conduction loss (computed from I_rms^2 * R_DS(on)); (c) secondary diode D1 conduction loss; (d) secondary switch conduction losses; (e) transformer core loss and copper loss; (f) resonant inductor core loss and copper loss.

(2) Simulation-based efficiency curve: PLECS simulation results showing the converter efficiency as a function of output current level (30 A to 100 A) are presented for the flat-top maintenance stage.

(3) Experimental efficiency measurements: At the scaled prototype level (V_dc = 130 V), efficiency was measured at I_ref = 10 A, 20 A, and 30 A using precision input and output power measurements. The results are presented alongside the simulation results.

(4) Comparison: The measured and simulated efficiencies are compared with theoretical estimates for a hard-switching H-bridge operating at the same current levels, demonstrating the loss reduction attributable to ZVS/ZCS operation.

Page 25, line 580. and Page 27, line 641.

 

Comment 7:

The following important validations are missing: dynamic response under load and transient conditions, thermal performance analysis (such as temperature rise or thermal imaging), and long-term operation or reliability testing.

Author’s response:

We appreciate the reviewer's comprehensive evaluation. The three items are addressed as follows:

(1) Dynamic response: The conventional load-step test, in which the reference current is abruptly changed during steady-state operation, is not directly applicable to the target application. In the ECR central adjustment coil excitation scenario, the mirror field configuration remains stable throughout each excitation pulse, and field adjustments occur only between pulses with sufficient idle time allocated for the storage capacitor to reach the new setpoint. The physically relevant dynamic metric for this converter is therefore the transition from the end of the rise phase to the stable flat-top plateau. A new figure showing this measured transition at I_ref = 30 A has been added to Section 4.2, with a detailed discussion of the application-specific operating profile.

Page 24, line 546.

 (2)  Thermal performance analysis: Direct thermal imaging of the prototype was not performed due to measurement setup limitations. However, the device-level thermal stress is quantitatively assessed through the loss decomposition presented in Section 4.3 (Figure 26). At the rated operating point I_ref = 100 A, the per-device dissipation is: primary SiC MOSFETs Q1/Q2 less than 5 W each, secondary SR MOSFETs approximately 7.5 W per path, and output H-bridge MOSFETs approximately 38 W per switch. Given the datasheet junction-to-case thermal resistances (R_θjc = 0.43 °C/W for NTHL040N120SC1, with comparable values for the Si MOSFETs) and a conservatively estimated case-to-ambient thermal resistance of 1 °C/W under forced-air cooling, the steady-state junction temperature rise is well within the 175 °C maximum ratings of all devices. Moreover, the low-duty-cycle pulsed operation (see item (3) below) further reduces the average thermal stress relative to the instantaneous loss values used in this estimate, providing additional thermal margin. Quantitative thermal imaging and long-term thermal-cycling characterization are identified as future work.

 (3) Long-term reliability testing: The target ECR adjustment-coil application operates in a  low-duty-cycle pulsed mode, with per-pulse flat-top duration on  the order of tens of milliseconds and pulse repetition rate  limited to ≤ 1 Hz by the ion source beam-extraction cycle. Between  pulses, the devices cool to near-ambient temperature, so the  accumulated stress mechanisms that dominate continuous-operation  reliability do not apply in the same way. The application-relevant  reliability metric is pulse-cycle fatigue over a representative  number of pulses, which requires an extended test campaign on the  full-scale system and is identified as future work.  At the design level, two features of the proposed topology  support long-term reliability:

(i) the primary ZVS and secondary  ZCS eliminate the dominant repetitive switching stress of  hard-switched alternatives;

(ii) during the peak-current discharge  phase, the primary semiconductors are inactive, reducing their  cumulative stress per pulse compared with direct-drive architectures.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

I have no more questions. Thank you for the author's reply. In addition, regarding comparisons, it would be more reasonable to compare with half-bridge DAB or LLC.

Reviewer 2 Report

Comments and Suggestions for Authors

Most of my review comments have been addressed adequately. Congratulations to dear authors for their research.