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Article

4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs Due to Power Cycling Tests

by
Dahui Yoo
1,
MiJin Kim
2,
Inho Kang
3 and
Ho-Jun Lee
1,*
1
Department of Electrical Engineering, Pusan National University, Busan 46284, Republic of Korea
2
Quality Team, Test & System Package, Samsung Electronics, Asan 31489, Republic of Korea
3
Korean Electrotechnology Research Institute, Changwon 51543, Republic of Korea
*
Author to whom correspondence should be addressed.
Electronics 2024, 13(7), 1267; https://doi.org/10.3390/electronics13071267
Submission received: 4 January 2024 / Revised: 26 February 2024 / Accepted: 20 March 2024 / Published: 28 March 2024
(This article belongs to the Topic Modeling, Fabrication, and Characterization of Semiconductor Materials and Devices)
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Abstract

:
Power cycling tests (PCTs) assess the reliability of power devices by closely simulating their operating conditions. A PCT was performed on commercially available 1.2 kV 4H-SiC power metal–oxide–semiconductor field-effect transistors to observe its impact on the 4H-SiC/SiO2 interface. High-resolution transmission electron microscopy and electron energy loss spectroscopy measurements showed variations in the length of the 4H-SiC/SiO2 transition layer, depending on whether the device was power cycled. Moreover, the total resistance at Vg ≫ Vt in Rtot − (Vg-Vt)−1 graph increased to 16.5%, while it changed more radically to 47.3% at Vg ≈ Vt. The threshold voltage shifted negatively. These variations cannot be expected solely through the wearout of the package.

1. Introduction

Silicon carbide (SiC) exhibits superior material properties compared to traditional silicon, making it highly suitable for power devices. In terms of thermal conductivity, SiC boasts a high value, enabling efficient heat dissipation and operation at elevated temperatures, crucial for power electronics [1,2]. Additionally, SiC’s high critical electric field allows it to handle high voltages with minimal resistance, enhancing device performance and reliability [3,4]. When compared to silicon insulated-gate bipolar transistors (IGBTs), SiC devices offer lower drift region resistance and a higher critical electric field, translating to improved efficiency and reliability in high-power applications [5]. The robustness of 4H-SiC devices makes them well-suited for harsh environments, expanding their utility in diverse fields, from electric vehicles to renewable energy systems [6]. In EVs, the high thermal conductivity of SiC ensures efficient power management and cooling, while the high critical electric field enables the handling of high voltages required for electric propulsion systems. These characteristics make SiC devices ideal for enhancing the performance and efficiency of automotive EVs, contributing to the advancement of sustainable transportation technologies. As the industry seeks solutions for higher power demands and increased energy efficiency, the merit of 4H-SiC power devices lies in their crucial role in advancing the capabilities and reliability of power electronics.
On the other hand, the reliability of 4H-SiC power MOSFETs compared to silicon IGBTs is a topic of ongoing research and development, with several key issues that need to be addressed to ensure their widespread adoption in power electronics applications. Gate oxide reliability, a critical aspect of SiC MOSFET performance, is closely intertwined with high-temperature stress degradation. The gate oxide serves as a crucial interface between the gate electrode and the semiconductor material, playing a pivotal role in device operation. Stress conditions such as extreme high temperatures, voltage bias, and current loads can lead to performance degradation and device failure [7]. Ensuring robust gate oxide capable of withstanding elevated temperatures while switching is essential for adopting 4H-SiC power MOSFETs. Failure modes in gate oxide include threshold voltage shifts and increased leakage currents [8]. High interface trap density is mentioned as the primary cause of these phenomena [8,9,10,11]. Therefore, there was a variety of research performed to overcome the reliability issue at the 4H-SiC/SiO2 interface. Siqi Zhao et al. optimized the oxidation process of silicon carbide (SiC) to minimize defects at the interface, thereby enhancing the electrical properties of the MOSFETs. Additionally, the paper explores advanced techniques such as nitrogen implantation and wet oxidation processes to passivate near-interface traps and improve the overall electrical quality of the 4H-SiC/SiO2 interface [12]. These strategies aim to mitigate interface-related challenges and enhance the performance and reliability of 4H-SiC power MOSFETs by addressing critical issues at the SiC/SiO2 interface [10]. On the other hand, degradation owing to the 4H-SiC/SiO2 interface becomes more pronounced while the device is operating [7,9].
Reliability assessments provide insights into the longevity, robustness, and failure modes under various operating conditions. As these devices find applications in electric vehicles, solar inverters, and aircraft power systems, understanding their reliability becomes indispensable. Therefore, JEDEC, AEC-A101, and AQG324 guide several tests to evaluate the reliability of power semiconductors. Among the various reliability tests, power cycling tests (PCTs) assess the reliability of power devices by closely simulating their operating conditions [13]. Failure modes commonly mentioned in PCTs include voids and cracks in the package [13,14]. The influence of power cycling-induced stress on the 4H-SiC/SiO2 interface is often underestimated.
Figure 1 shows a series of resistances within the drain-to-source current path of high-voltage vertically double-implanted 4H-SiC n-type metal–oxide–semiconductor field-effect transistors (VD-MOSFETs). The total internal resistance (Rtot) is the sum of the resistance components.
Rtot = Rcontact + RN+ + Rchannel + RJFET + RDrift + RSubstrate
The predominant components contributing to the Rtot differ between Si and 4H-SiC. In 4H-SiC VD-MOSFETs, the resistance components related to the 4H-SiC/SiO2 interface account for 80% of the Rtot [15]. The issues related to the 4H-SiC/SiO2 interface are the accumulation of interfacial carbon [16,17], threefold-coordinated O and C interstitials [17], Si vacancies [18], and dangling Si and C bonds [17]. However, silicon power semiconductors and their interfaces with SiO2 are yet to be investigated.
PCTs involve repeated switching of the gate electrode while simultaneously subjecting it to artificially high heating currents. Wearouts in solder voids and wire bonds are closely related to the coefficient of thermal expansion (CTE). At each junction, the device under test (DUT) has different CTE rates [19]. When a heated current generates a junction temperature swing, the region where the CTE is different receives thermomechanical stress. Finally, the wire bonds are broken, increasing the solder voids.
Another perspective is that the power loss at each resistor in the current path is the origin of the ejected heat. Hence, the region exposed to electrical stress or a high heating current from the PCT is closely related to the resistance. The quality of a 4H-SiC/SiO2 interface is poor; therefore, the channel resistance (RCH) is a highly resistive element of the Rtot in 4H-SiC power MOSFETs. Therefore, the impact of the active chip is questionable. When subjected to stress like elevated temperatures or varying gate bias conditions, the influence of high interface trap density is magnified. Elevated temperatures can accelerate trap-assisted tunneling processes, leading to enhanced trap occupation and subsequent degradation in device characteristics [7]. Similarly, under different gate bias conditions, the interaction between carriers and interface traps can further exacerbate threshold voltage shifts and increase on-state resistance, affecting the overall performance of the MOSFETs [7,9]. Hence, in this paper, we conducted PCTs on 4H-SiC power devices and examined the changes in the devices before and after the tests. We investigated the failure modes and defects originating from the package, which are the primary causes of failure in power cycling tests. Additionally, we explored the internal defects and degradation within the devices. Through HR-TEM/EELS analysis, we examined differences in the 4H-SiC/SiO2 transition layer depending on the PCTs. We studied the electrical characteristics influenced by the state of the 4H-SiC/SiO2 interface. By utilizing transfer characteristic graphs measured before and after power cycling tests, we observed a negative shift in the threshold voltage and an increase in the resistance of the channel region. By conducting power cycling tests, which closely simulate the operating environment of 4H-SiC power MOSFETs, we examined the resulting changes not only in the package but also in the 4H-SiC/SiO2 interface.

2. Materials and Methods

The commercial 4H-SiC MOSFET with a standard TO-247 package featuring a breakdown voltage of 1.2 kV and on-state resistance (RDS,ON) of 80 mΩ was chosen for the DUT. A MicReD Industrial Power Tester 1500 A, Siemens imposed power and monitored the DUT’s test parameters. For precise experiments, the forward voltage drop of the body diode (Von) serves as a temperature-sensitive electrical parameter (TSEP) [20]. Figure 2a shows the equivalent circuit, and Figure 2b shows the waveforms of the PCT parameters and the output junction temperature cycles. Table 1 lists the test conditions. The test equipment automatically maintains a constant temperature swing (ΔTj) under a fixed on-time (ton) and off-time (toff) by adjusting the heating current (IH). A sample is considered failed when Von increases by 120%.
To determine the failure mode at the 4H-SiC/SiO2 interface, the DUTs were decapsulated and observed, especially for the stressed cells in the active region, using GEMINI500, an ultrahigh analytical field-emission scanning electron microscope (FE-SEM), and a focused ion beam (FIB). Titan Cubed G2 60-300KV(FEI), High-resolution transmission electron microscopy (HR-TEM), and electron energy loss spectroscopy (EELS) were used to inspect the 4H-SiC/SiO2 interface of the substantially deteriorated cells in detail. The use of HR-TEM and EELS in observing the 4H-SiC/SiO2 interface brings about several key advantages in the context of this research. HR-TEM provides the visualization of nanoscale features with precision. This capability is crucial when studying the intricate details of the 4H-SiC/SiO2 transition layer, as it allows researchers to discern subtle structural changes induced by PCT. EELS, on the other hand, offers valuable insights into the elemental composition of the interface. By mapping the percentages of Si, C, and O along the transition layer, EELS helps quantify compositional variations that might be indicative of degradation or damage. Moreover, the combination of HR-TEM and EELS enables a comprehensive examination of both structural and chemical aspects, providing a holistic understanding of the 4H-SiC/SiO2 interface’s response to PCT-induced stress. This approach enhances the reliability and accuracy of the observations, making HR-TEM and EELS indispensable tools for unraveling the complexities of the SiC/SiO2 interface and its role in the performance of power devices.
The transfer curves at a fixed, small drain voltage (Vd = 50 mV) were measured using a Keysight B1506a (Santa Rosa, CA, USA),power device curve tracer, before and after the PCT. Figure 3 shows the transfer characteristics, Id vs. Vg, of the 4H-SiC n-MOSFETs (VD-MOSFETs). The linear extrapolation method employed for extracting the threshold voltage (Vt) involves plotting the device’s transfer characteristics, specifically the drain current (Id) against gate voltage (Vg) at a fixed, small drain voltage. By identifying the linear region in which the drain current increases linearly with the gate voltage, a straight line is extrapolated to intersect with the x-axis, determining the Vt accurately. The maximum transconductance point is chosen for heightened accuracy. The technique is crucial for assessing the impact of power cycling tests on the threshold voltage of 4H-SiC power devices, ensuring a reliable measure of the device’s conduction initiation point. Figure 4a plots the total resistance of the transfer graph, Rtot, vs. the (Vg-Vt)−1 value. The calculated resistance values from the transfer graph are plotted on the y-axis, while the corresponding (Vg-Vt)−1 values are plotted on the x-axis. This results in the Rtot vs. (Vg-Vt)−1 graph, providing a visual representation of the relationship between total resistance and the inverse of the gate overdrive voltage. This graph allows for a detailed analysis of how different resistance components contribute to the overall behavior of the device under varying gate conditions. At large (Vg-Vt)−1 values, where Vg closes to Vt, the channel resistance dominates the total drain-source current [21,22,23]. The intersection with the ordinate y-axis in Figure 4b yields the residual resistance Rs [21,22,23].
All series resistances, except RCH, in Equation (1) comprise Rs. There are other resistances. The resistance of the source wire to the source metal contact, RWirebond, and the resistance of the solder, RSolder, originate from the package to an active chip connection. We assumed that RWirebond and RSolder were practical reasons for the increase in Rs after PCT because regions in the n-drift are seldom weakened by ΔTj. By comparing the changed parameters in the Rtot vs. (Vg-Vt)−1 graph, we can determine which regions, such as Rs or Rch, become more resistive.

3. Results and Discussion

When the on-state voltage drop (Von) reached the predefined test stop condition mentioned in Table 1, the sample experiments were stopped. Figure 5 shows the value of Von measured at each cycle, and the thermal resistance (Rth) was checked every 500th cycle. It was observed that Von underwent dynamic variations after the 2300th cycle.

3.1. Stress Symptoms of the Surroundings

The primary reason for the increase in Von in the TO-247-3L discrete device is usually defects in/on the wire bonds [13,24]. Although solder fatigue is another potential problem, neither a 5% increase nor a decrease in Rth was observed in this experiment. An increase in thermal resistance in the thermal path is occasionally attributed to solder fatigue [13,25]. Therefore, it is hard to expect solder-void-related critical degradation. Figure 6 shows the partially decapsulated DUT images of the intrinsic and power-cycled samples. After power cycling, cracks were observed in the wire-bond heels, which led to separation. The resistance of the wire increases when the bond between the wire and the active device is weak. Overall, Von varied aggressively with wire bond deterioration.

3.2. Pattern of Degradation at a 4H-SiC/SiO2 Interface

This research investigates the impact of power cycling tests (PCT) on the 4H-SiC/SiO2 interface in commercial 1.2 kV 4H-SiC VD-MOSFETs. Employing advanced microscopy and spectroscopy techniques, this study reveals changes in the length of the 4H-SiC/SiO2 transition layer, which is critical for device reliability. The analysis of electrical parameters, including threshold voltage shifts and resistance variations, will be addressed in this chapter to demonstrate potential damage at the SiC/SiO2 interface post-PCT. The cracks and delamination on the inter-layer dielectric (ILD) were sporadically detected in the active region of each sample. Figure 7 shows cells from the DUT where the ILD was slightly delaminated. The HRTEM image in Figure 8 was obtained from the cross-section along the red and green dotted line in Figure 7.
To monitor the degradation at the 4H-SiC/SiO2 interface, Figure 8a,b shows the comparison of the HR-TEM images of the intrinsic and power-cycled DUTs. The DUT undergoing PCT (or power-cycled DUT) exhibited a different lattice structure, especially near the 4H-SiC/SiO2 interface, as indicated by the red bidirectional arrows. To quantitatively analyze the transition layer, EELS was conducted along the green line, as shown in Figure 9a, at the 4H-SiC/SiO2 interface in the junction field-effect transistor (JFET) region. The composition percentages of Si, C, and O were collected at 48 different positions, from the gate dielectric SiO2 to the semiconductor 4H-SiC. Figure 9b illustrates the percentage composition changes in the Si L-edge, O K-edge, and C K-edge collected near the 4H-SiC/SiO2 interface for each sample. The percentage composition of each element reached saturation at both ends, that is, SiO2 and SiC, except in the transition layer. The slope of each element in the transition layer also varied during PCT. The 4H-SiC/SiO2 transition layer of the power-cycled DUT was longer than that of the intrinsic sample. It is essential for maintaining a sharp and well-defined interface between the SiC and SiO2 layers to ensure proper device operation. Electrically, the transition layer influences charge carrier mobility, interface trap density, and overall device performance. A high-quality transition layer helps in reducing defects, interface traps, and charge carrier scattering, which are essential for maintaining consistent device operation over time [11,26,27].
When the length of the 4H-SiC/SiO2 transition layer was short, the surface roughness between the 4H-SiC semiconductor and SiO2 gate dielectric was low [28,29]. As the surface roughness increased, the mobility decreased, increasing the channel resistance [30,31]. To compare the results from the HR-TEM and EELS regarding the channel resistance, an Rtot vs. (Vg-Vt)−1 graph was plotted in Figure 10. Figure 10 shows the change in the overall resistance Rtot calculated using a transfer graph (Vd = 50 mV). In this graph, as the x-axis increases, Vg approaches Vt, and channel resistance RCH dominates Rtot [21]. It can be observed that the resistance of the channel increased significantly after PCT. The resistance extrapolated from the Vg ≈  Vt increased by 47.3%, while Vg ≫  Vt, (Vg-Vt)−1  → 0, increased by 16.5% after power cycling. In the Vg ≈ Vt range, a relatively low drain current flows, and it is less affected by the gate-to-source electrode feedback (G-S feedback) owing to the wire bond. The change in resistance in the Vg ≈ Vt range was more dramatic than in the case of Vg   ≫  Vt. These results indicate that RCH has increased. This corresponds to the findings of prior research that the channel resistance is very high when the transition layer is distinguishable.
Fiorenza et al. successfully showed that an interface with a low near-interface trap and oxide trap density has a shorter length than the 4H-SiC/SiO2 transition layer [32]. Zhang et al. conducted theoretical research on the relationship between near-interface oxide traps and Si interstitials in substoichiometric SiOx in the transition layer and found the presence of dangling bonds, including SiCyOx and SiOxNy compounds [33]. Likewise, complex flaws that induce a negative Vt shift exist within the 4H-SiC/SiO2 transition layer. Figure 11 shows the Vt values extracted from the measured transfer and transconductance graphs. The threshold voltage exhibited a negative shift. If the defects in the wire bond had degraded the G-S feedback, the threshold voltage would have increased. It is reasonable to assume that as the transition area with various defects expands, the influence of traps that lead to a negative Vt shift becomes more significant.
The negative threshold voltage (Vt) shift observed in the 4H-SiC MOSFETs after PCT poses significant concerns for device performance. A negative Vt shift typically indicates a degradation in the transistor’s characteristics, impacting its switching behavior and overall functionality. This shift can lead to increased power losses, reduced efficiency, and compromised reliability [34]. Moreover, negative Vt shifts are often associated with the presence of defects or traps in the semiconductor material, indicating potential structural and electrical damage. Addressing and mitigating this adverse effect is crucial for maintaining the long-term stability and functionality of 4H-SiC power devices in practical applications.

4. Conclusions

This study shows the impact of power cycling tests (PCTs) on the 4H-SiC/SiO2 interface in commercial 1.2 kV 4H-SiC VD-MOSFETs, which is crucial for evaluating power device reliability. Traditionally, PCTs focus on package-related issues, but this research emphasizes the underestimated influence of power cycling-induced stress on the 4H-SiC/SiO2 interface. The internal resistance components in 4H-SiC VD-MOSFETs significantly differ from silicon, with the 4H-SiC/SiO2 interface accounting for a substantial portion of the total resistance (Rtot).
Power cycling tests involve repeated gate electrode switching with high heating currents, causing wearout in solder voids and wire bonds. Power loss in each resistor in the current path is considered the source of ejected heat. Regions exposed to electrical stress or high heating currents, closely related to resistance, are crucial in 4H-SiC power MOSFETs. Experimental results showed dynamic variations in the on-state voltage drop (Von) attributed to defects in wire bonds. Thorough decapsulation and observation of devices revealed a correlation between Von variations and wire bond deterioration. Inspection of the 4H-SiC/SiO2 interface using HR-TEM and EELS demonstrated changes in lattice structure and composition percentages after power cycling.
A critical aspect involved plotting Rtot vs. (Vg-Vt)−1 graphs, indicating significant resistance increases after power cycling, particularly in the Vg ≈ Vt range. Findings emphasize the intricate relationship between power cycling, interface degradation, and changes in electrical parameters. In conclusion, this research contributes valuable insights into the effects of power cycling on 4H-SiC power devices, emphasizing the need for a deeper understanding of interface dynamics for enhanced device reliability and performance.

Author Contributions

Investigation, M.K.; Writing—original draft, D.Y.; Writing—review & editing, I.K. and H.-J.L. All authors have read and agreed to the published version of the manuscript.

Funding

[1] This study was supported by the Korea Institute for Advancement of Technology (KIAT) grant funded by the Korean Government (P0012451, The Competency Development Program for Industry Specialists). [2] This work was supported by the Technology Innovation Program (or Industrial Strategic Technology Development Program-Foundry-oriented SiC MOSFET 8-inch Mass Product Process Foundation Establishment) (00144306, Foundry-oriented SiC MOSFET 8-inch Mass Product Process Foundation Establishment) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

Author MiJin Kim was employed by the company Samsung Electronics. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Correction Statement

This article has been republished with a minor correction to the Funding statement. This change does not affect the scientific content of the article.

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Figure 1. Series resistors of the total resistance (Rtot).
Figure 1. Series resistors of the total resistance (Rtot).
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Figure 2. Power cycling test conditions: (a) equivalent circuit; (b) waveforms for power cycling test parameters and output junction temperature swing.
Figure 2. Power cycling test conditions: (a) equivalent circuit; (b) waveforms for power cycling test parameters and output junction temperature swing.
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Figure 3. Transfer curve and transconductance of commercial high-voltage vertically double implanted 4H-SiC n-MOSFETs (VD-MOSFETs). The linear extrapolation method is applied to extract Vt.
Figure 3. Transfer curve and transconductance of commercial high-voltage vertically double implanted 4H-SiC n-MOSFETs (VD-MOSFETs). The linear extrapolation method is applied to extract Vt.
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Figure 4. Rtot vs. (Vg-Vt)−1 graph when (a) V G → V T H ,  RCH is the dominant component of Rtot and (b) 1 V G − V T H → 0 . The y-intercept represents the residual resistance RS.
Figure 4. Rtot vs. (Vg-Vt)−1 graph when (a) V G → V T H ,  RCH is the dominant component of Rtot and (b) 1 V G − V T H → 0 . The y-intercept represents the residual resistance RS.
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Figure 5. On-state voltage drop at every cycle and thermal resistance at every 500th power cycle.
Figure 5. On-state voltage drop at every cycle and thermal resistance at every 500th power cycle.
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Figure 6. Partially decapsulated DUT images of (a) an intrinsic device and (b) a power-cycled device, whose Von was increased to 120%.
Figure 6. Partially decapsulated DUT images of (a) an intrinsic device and (b) a power-cycled device, whose Von was increased to 120%.
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Figure 7. FE-SEM image of the deteriorated cells in DUTs HR-TEM was measured along a red and green dotted line.
Figure 7. FE-SEM image of the deteriorated cells in DUTs HR-TEM was measured along a red and green dotted line.
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Figure 8. HR-TEM images of (a) an intrinsic device and (b) a power-cycled device, whose Von was increased to 120%.
Figure 8. HR-TEM images of (a) an intrinsic device and (b) a power-cycled device, whose Von was increased to 120%.
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Figure 9. EELS results: (a) SEM image for EELS percent composition mapping line (green); (b) EELS percent composition vs. depth.
Figure 9. EELS results: (a) SEM image for EELS percent composition mapping line (green); (b) EELS percent composition vs. depth.
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Figure 10. Rtot vs. (Vg-Vt)−1 graph. The y-intercept for each graph indicates the total resistance when (a) Vg ≈ Vt and (b) Vg ≫ Vt. The yellow region in (a) is magnified into (b).
Figure 10. Rtot vs. (Vg-Vt)−1 graph. The y-intercept for each graph indicates the total resistance when (a) Vg ≈ Vt and (b) Vg ≫ Vt. The yellow region in (a) is magnified into (b).
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Figure 11. The transfer curves at a fixed, small drain voltage (Vd = 50 mV). The x-intercepts is the threshold voltage before/after power cycling test.
Figure 11. The transfer curves at a fixed, small drain voltage (Vd = 50 mV). The x-intercepts is the threshold voltage before/after power cycling test.
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Table 1. Power cycling test setup.
Table 1. Power cycling test setup.
ΔTj (℃)Tjmax (℃)ton (s)toff (s)VGS,on (V)VGS,off (V)IS (mA)IH (A)Von (%)
1101702418−5−8022.3120%
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MDPI and ACS Style

Yoo, D.; Kim, M.; Kang, I.; Lee, H.-J. 4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs Due to Power Cycling Tests. Electronics 2024, 13, 1267. https://doi.org/10.3390/electronics13071267

AMA Style

Yoo D, Kim M, Kang I, Lee H-J. 4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs Due to Power Cycling Tests. Electronics. 2024; 13(7):1267. https://doi.org/10.3390/electronics13071267

Chicago/Turabian Style

Yoo, Dahui, MiJin Kim, Inho Kang, and Ho-Jun Lee. 2024. "4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs Due to Power Cycling Tests" Electronics 13, no. 7: 1267. https://doi.org/10.3390/electronics13071267

APA Style

Yoo, D., Kim, M., Kang, I., & Lee, H.-J. (2024). 4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs Due to Power Cycling Tests. Electronics, 13(7), 1267. https://doi.org/10.3390/electronics13071267

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