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J. Low Power Electron. Appl., Volume 5, Issue 4 (December 2015) , Pages 216-290

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Open AccessFeature PaperArticle
An FSK and OOK Compatible RF Demodulator for Wake Up Receivers
J. Low Power Electron. Appl. 2015, 5(4), 274-290; https://doi.org/10.3390/jlpea5040274 - 30 Nov 2015
Cited by 4 | Viewed by 4644
Abstract
This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds an [...] Read more.
This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds an LC oscillator, an envelope detector and a base-band amplifier. To optimize the trade-off between RF performances and power consumption, the cross-coupled based oscillator is biased in moderate inversion region. The proof of concept is implemented in a 65 nm CMOS technology and is intended for the 2.4 GHz ISM band. With a supply voltage of 0.5 V, the demodulator consumes 120 μW and demonstrates the demodulation of OOK and FSK at a data rate of 500 kbps. Full article
(This article belongs to the Special Issue Low-Power Systems on Chip Enabling Internet of Things)
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Open AccessFeature PaperArticle
Reconfigurable RF Energy Harvester with Customized Differential PCB Antenna
J. Low Power Electron. Appl. 2015, 5(4), 257-273; https://doi.org/10.3390/jlpea5040257 - 27 Nov 2015
Cited by 5 | Viewed by 5077
Abstract
In this work, a Radio Frequency (RF) Energy Harvester comprised of a differential Radio Frequency-to-Direct Current (RF-DC) converter realized in ST130 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology and a customized broadband Printed Circuit Board (PCB) antenna with inductive coupling feeding is presented. Experimental results [...] Read more.
In this work, a Radio Frequency (RF) Energy Harvester comprised of a differential Radio Frequency-to-Direct Current (RF-DC) converter realized in ST130 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology and a customized broadband Printed Circuit Board (PCB) antenna with inductive coupling feeding is presented. Experimental results show that the system can work with different carrier frequencies and thanks to its reconfigurable architecture the proposed converter is able to provide a regulated output voltage of 2 V over a 14 dB of RF input power range. The conversion efficiency of the whole system peaks at 18% under normal outdoor working conditions. Full article
(This article belongs to the Special Issue Low-Power Systems on Chip Enabling Internet of Things)
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Open AccessArticle
Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things
J. Low Power Electron. Appl. 2015, 5(4), 234-256; https://doi.org/10.3390/jlpea5040234 - 09 Nov 2015
Cited by 6 | Viewed by 4830
Abstract
This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT).We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We [...] Read more.
This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT).We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-μm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits. Full article
(This article belongs to the Special Issue Low Power Smart Sensors for the Internet of Things)
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Open AccessArticle
Radiation Hardened NULL Convention Logic Asynchronous Circuit Design
J. Low Power Electron. Appl. 2015, 5(4), 216-233; https://doi.org/10.3390/jlpea5040216 - 20 Oct 2015
Cited by 4 | Viewed by 4380
Abstract
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and [...] Read more.
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead. Full article
(This article belongs to the Special Issue Low-Power Asynchronous Circuits)
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