Search Results (756)

The analysis of brain data through electroencephalography (EEG) has become essential in neuroscience, affective computing, and brain–computer interfaces. Recent work associates EEG features with artificial neurotransmitter models, simulating emotions and rational–emotional decision-making using complexity theory. However, current methods face limitations: (1) linear temporal representations lacking memory and anticipation, (2) limited contextual adaptation, (3) difficulty with paradoxical affective states, and (4) absence of ethical reasoning in decision-making. We present a framework based on Sophimatics, using complex time ($t=t_{real}+i\cdot t_{imag}\in \mathbb{C}$) where $t_{real}$ represents chronology and $t_{imag}$ encodes experiential dimensions including memory depth and anticipatory imagination. The Super Time Cognitive Neural Network (STCNN) architecture enables the parallel processing of objective time sequences and subjective cognitive experiences. Our Sophimatics-assisted EEG analysis achieves: (1) two-dimensional temporal coherence integrating past experiences and future projections, (2) context-sensitive adaptation via ontological knowledge graphs, (3) interpretable symbolic reasoning compatible with clinical psychology, (4) mechanisms for resolving affective paradoxes, and (5) ethical constraints ensuring value-based decision-making. Across three case studies (emotion recognition, meditation-induced transitions, and brain–computer interface decision support), integrated Sophimatics models outperform traditional machine learning (15–22% accuracy improvement) and complexity theory models (8–14% improvement), while offering greater cognitive richness and immunity to incomplete data. Results establish a post-generative AI framework with computational wisdom: relationally interactive, ethically informed, and temporally consistent with human cognitive and affective life. The framework outlines paths toward next-generation neuromorphic systems achieving genuine understanding beyond pattern recognition. Full article

Modern computing platforms increasingly rely on random number generators (RNGs) for modeling probabilistic processes in simulation, probabilistic computing, and system validation. They are also essential for cryptographic operations such as key generation, authenticated encryption, and digital signatures. Deterministic Random Bit Generators (DRBGs), as specified in the National Institute of Standards and Technology (NIST) Special Publication (SP) 800-90A, provides a standardized method for expanding entropy into cryptographically strong pseudorandom sequences. This work presents the design and Field Programmable Gate Array (FPGA) implementation of a hash-based DRBG using Ascon-Hash256, a lightweight, quantum-resistant hash function from the NIST-standardized Ascon cryptographic suite. It implements hash-based derivation, instantiation, generation, and reseeding of the generator via iterative hash invocations and state updates. Leveraging Ascon’s sponge-based structure, the design achieves efficient entropy absorption and diffusion while maintaining an area-efficient FPGA architecture, making it well suited for resource-constrained platforms. The diffusion properties of the proposed DRBG are evaluated through avalanche and reproducibility analyses, confirming strong sensitivity to input variations and secure, repeatable operation. Moreover, Monte Carlo and stochastic-diffusion evaluation of the generated bitstreams demonstrates correct convergence and statistically consistent behavior. These results confirm that the proposed hash-based DRBG provides reproducible, hardware-efficient, and cryptographically secure random numbers suitable for next-generation neuromorphic, probabilistic computing systems, and Internet of Things (IoT) devices. Full article

Spiking neural networks are promising for energy-efficient edge intelligence, but mapping 1-bit spikes onto high-precision vector datapaths leads to underutilization and low compute density. This paper presents DeVSA, a 16-lane vector SNN accelerator for LIF-based SNNs with 1-bit spikes and BF16 weights. DeVSA reuses the compressor tree of a standard BF16 multiplier to support an 8-way spike-weight dot-product (DOT8) by directly reducing exponent-aligned, spike-gated mantissas without introducing a dedicated SNN accumulation datapath, preserving full BF16 multiplication capability. DeVSA integrates single-cycle fire-and-reset to streamline per-timestep LIF updates. A hardware micro-loop controller amortizes instruction fetch/decode over up to 256 iterations, and a shared reconfigurable adder tree supports both element-wise operations and hierarchical reductions. Synthesized in 28-nm CMOS, DeVSA operates at 1.4 GHz and achieves a peak throughput of 340.6 GFLOPS at 163 mW, corresponding to 2.09 TFLOPS/W and 838 GFLOPS/mm² post-synthesis compute density in DOT8 mode. On N-MNIST, DVS-Gesture, and CIFAR-10, DeVSA provides end-to-end effective speedups of up to 7.76× over standard vector baselines and outperforms state-of-the-art programmable SNN processors by 5.0×–7.9× in estimated post-P&R density under 50% utilization. DeVSA shows that compressor-tree reuse can deliver high compute density and energy efficiency with vector-level programmability for SNN inference. Full article

Single memristive nanowire networks have emerged as a promising pathway for energy-efficient neuromorphic computing, owing to their intrinsic nonlinearity, high dimensionality, fading memory and volatile switching dynamics relevant to physical reservoir computing. While prior works focused on oxide- or silver-based network systems, these approaches face trade-offs between operating voltage, cost, stability, and scalability. This work presents a proof-of-concept demonstration of stochastic polyvinylpyrrolidone (PVP)-coated nickel nanowire networks as low-cost and scalable memristive platforms, exhibiting low-voltage resistive switching (1–2 V). The electrical characterization reveals predominantly volatile resistive switching combined with nonvolatile behavior, consistent with a filamentary conduction mechanism at nanowire junctions. The switching dynamics are governed by the polymer coating thickness, with an intermediate PVP concentration (Ni@PVP = 1:25) showing optimal performance, with a resistance ratio of ~200, stable retention over 1 h, and a reproducible endurance of over 45 cycles. These results establish Ni@PVP nanowire networks as promising memristive platforms for neuromorphic hardware applications and physical reservoir computing, with relevant properties such as fading memory and nonlinear dynamics. Full article

Simulated spiking neural networks have been explored for over a hundred years. Many of these networks are driven by biological considerations and an attempt to simulate brains, but others are used with little biological consideration. This paper gives some history of the development of spiking neural models, their use for modelling biological and cognitive phenomena, and for machine learning. It introduces the current state of the art in computational biological neuron and synapse modelling and plasticity. It introduces and reviews balanced spiking networks and their engineering applications. Spiking networks are also used for machine learning, with the hope that their implementation on neuromorphic hardware will bring energy and time savings. Similarly, neuromorphic hardware can enable massive parallelism, supporting larger spiking networks. The use of spiking nets for machine learning, both with biologically plausible models and without, is discussed, showing that effective models already exist. The paper concludes with some notes about implementing spiking nets and a discussion including open questions and future work. Full article

Neuromorphic computing seeks to mimic structure and function of biological neural systems to enable energy-efficient, adaptive information processing. A critical component of this paradigm is neural encoding—the translation of analog or digital input data into spike-based representations suitable for spiking neural networks (SNNs). This paper provides a comprehensive overview of major neural encoding schemes used in neuromorphic systems, including rate and temporal encoding, as well as latency, interspike interval, phase, and multiplexed encoding. The purpose of this paper is to explore the use of encoding techniques for deep learning applications. We discussed the underlying principles of spike encoding approaches, their biological inspiration, computational efficiency, power consumption, integrated circuit design and implementation, and suitability for various neuromorphic applications. We also presented our research on a hardware-and-software co-design platform for different encoding schemes and demonstrated their performance. By comparing their strengths, limitations, and implementation challenges, we aim to provide insights that will guide the development of more efficient and application-specific neuromorphic systems. We also performed an encoder performance analysis via Python 3.12 simulations to compare classification accuracies across these spike encoders on three popular image and video datasets. The performance of neural encoders working with both deep neural networks (DNNs) and SNNs is analyzed. Our performance data is largely consistent with the benchmark data on image classification from other papers, while limited performance data on the University of Central Florida’s 101 (UCF-101) video dataset were found in comparable studies on spike encoders. Based on our encoder performance data, the Interspike Interval (ISI) encoder performs well across all three datasets, preserving continuous, detailed spike timing and richer temporal information for standard classification tasks. Further, for image classification, multiplexing encoders outperform other spike encoders as they simplify timing patterns by enforcing phase locking and improve stability and robustness to noise. Within the SNN testbenches, the ISI-Phase encoder achieved the highest accuracy on the Modified National Institute of Standards and Technology (MNIST) dataset, surpassing the Time-To-First Spike (TTFS) encoder by 1.9%. On the Canadian Institute For Advanced Research (CIFAR-10) dataset, the ISI encoder achieved the highest accuracy. This ISI encoder had 22.7% higher accuracy than the TTFS encoder on the CIFAR-10 dataset. The ISI encoder performed best on the UCF-101 dataset, achieving 12.7% better performance than the TTFS encoder. Full article

The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence. Full article

This paper introduces a biomimetic framework and novel brain-inspired AI (BIAI) models based on spiking neural networks (SNNs) for emotional state recognition from audio (speech), visual (face), and integrated multimodal audio–visual data. The developed framework, named eXCube2, uses a three-dimensional SNN architecture NeuCube that is spatially structured according to a human brain template. The BIAI models developed in eXCube2 are trainable on spatio- and spectro-temporal data using brain-inspired learning rules. Such models are explainable in terms of revealing patterns in data and are adaptable to new data. The eXCube2 models are implemented as software systems and tested on speech and video data of subjects expressing emotional states. The use of a brain template for the SNN structure enables brain-inspired tonotopic and stereo mapping of audio inputs, topographic mapping of visual data, and the combined use of both modalities. This novel approach brings AI-based emotional state recognition closer to human perception, provides a better explainability and adaptability than existing AI systems. It also results in a higher or competitive accuracy, even though this was not the main goal here. This is demonstrated through experiments on benchmark datasets, achieving classification accuracy above 80% on single-modality data and 88.9% when multimodal audio–visual data are used, and a “don’t know” output is introduced. The paper further discusses possible applications of the proposed eXCube2 framework to other audio, visual, and audio–visual data for solving challenging problems, such as recognizing emotional states of people from different origins; brain state diagnosis (e.g., Parkinson’s disease, Alzheimer’s disease, ADHD, dementia); measuring response to treatment over time; evaluating satisfaction responses from online clients; cognitive robotics; human–robot interaction; chatbots; and interactive computer games. The SNN-based implementation of BIAI also enables the use of neuromorphic chips and platforms, leading to reduced power consumption, smaller device size, higher performance accuracy, and improved adaptability and explainability. This research shows a step toward building brain-inspired AI systems. Full article

In event-based neuromorphic processing, computer vision finds an efficient alternative capable of optimizing computational and energy resources, inspired by the dynamics of biological neural systems. In the development of real-time processing systems, it is crucial to visually represent the information captured by sensors and to explore its content with precision. Thus, machine learning models are implemented with the capability of being deployed on hardware devices with limited capabilities, depending on the intended purpose, ensuring savings in computational resources. The aim of this work was to evaluate the limits of the implemented neuron model, leaky-integrate and fire (LIF), for fitting convolutional layers of a neural network. To this end, the characteristics of the LIF neuron model used are summarized, as well as the details of its implementation in a hardware design, using configurable parameters. The experimental phase considered two convolution approaches to compare performance, Matlab R2022a software and a spiking convolutional processor for an FPGA, using sample recordings from the MNIST-DVS dataset and Sobel kernels for edge detection. The results reflect that the number of spikes generated by both approaches is very similar and their distribution by frame addresses is directly proportional. Full article

The integration of Artificial Intelligence (AI) into Internet of Things (IoT) medical devices has revolutionized arrhythmia monitoring. However, the high computational and power demands of traditional Deep Learning (DL) models pose significant challenges for long-term, battery-operated smart electronics. Spiking Neural Networks (SNNs), inspired by the biological efficiency of the human brain, offer a promising solution. This paper reviews the intersection of SNNs, low-power IoT hardware, and biomedical signal processing. I examine the transition from frame-based to event-driven processing, and discuss the hardware–software co-design necessary for next-generation cardiac wearables. Full article

The current work proposes a novel idea of exploration of the standard 180 nm-based bulk CMOS technology operating under cryogenic temperatures to achieve energy-efficient and high-speed computation. A PMOS chip of 180 nm technology is fabricated and is explored for synaptic memory applications by operating at 4 K temperatures. This proposed approach offers numerous advantages in terms of enhanced charge carrier mobilities, reduced power dissipation, and seamless integration with standard CMOS technology. The fabricated PMOS under cryogenic temperatures exhibits pinched hysteresis characteristics, confirming the memory retention capability with very low set and reset voltages. Next, synaptic functional measurements were performed by applying constant pulse trains at the drain terminal to understand the human brain’s learning and memory retention capabilities. Full article

In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. Among the candidates for artificial synapses, memristors based on two-dimensional MXenes (specifically Ti₃C₂T_x) have attracted significant attention due to their unique layered structure, high metallic conductivity, and tunable physicochemical properties. This review provides a comprehensive analysis of MXene-based memristors, from material synthesis to system-level applications. We examine how different synthesis strategies, including etching methods, directly influence device performance and elucidate the underlying resistive switching mechanisms driven by ion migration, valence change, and interfacial processes. Furthermore, the review demonstrates the efficacy of MXenes in emulating biological synaptic functions—such as spike-timing-dependent plasticity (STDP) and long-term potentiation/depression (LTP/LTD)—and their application in tasks like handwritten digit recognition. Finally, we highlight emerging frontiers in flexible electronics and in-sensor computing, offering insights into the future trajectory of integrated sensing, memory, and computation. Full article

Spiking Neural Networks (SNNs) have attracted increasing attention due to their energy efficiency and suitability for neuromorphic data processing. Despite these advantages, the security of SNNs—particularly their robustness against backdoor attacks—remains underexplored. This study revisits fine-pruning, a widely adopted backdoor defense technique in deep neural networks, and adapts it to the unique spatio-temporal characteristics of SNNs. We propose two SNN-specific fine-pruning methods: Hook–Surrogate Gradient-based fine-pruning (HS-FP) and Spike–STDP-based fine-pruning (SS-FP). HS-FP leverages hook-based activation analysis with surrogate gradient learning, while SS-FP integrates total spike activity with hybrid STDP and surrogate gradient fine-tuning. We evaluate both methods against static, moving, and smart backdoor attacks on two neuromorphic benchmarks, N-MNIST and DVS128-Gesture. Experimental results show that both approaches reduce the attack success rate down to approximately 10% while preserving model accuracy above 99% on N-MNIST and achieving substantial recovery on DVS128-Gesture. Moreover, our analysis reveals that several phenomena observed in fine-pruning-based defenses for deep neural networks—such as mixed-function neurons and backdoor reactivation during fine-tuning—also manifest in SNNs. These findings highlight both the effectiveness and limitations of fine-pruning in the SNN domain and suggest promising directions for extending existing DNN security methodologies to neuromorphic systems. Full article

This paper presents a compact floating memtranstor (MT) emulator, a memory element characterized by a direct φ–q relationship, realized without analog multipliers or complex circuitry. The proposed design employs only two active blocks—a voltage differential transconductance amplifier (VDTA) and a voltage differential current conveyor (VDCC)—along with three grounded capacitors and a single grounded electronically tunable resistor. The emulator accurately reproduces the fundamental φ–q dynamics, exhibiting origin-crossing pinched hysteresis loops under sinusoidal excitation, and operates at a low supply voltage of ±0.9 V. Electronic tunability is achieved via bias-controlled transconductance modulation, enabling flexible adaptation across excitation frequencies and operating conditions. Validation is performed through analytical modeling, Monte Carlo simulations, temperature sensitivity analysis, and full LTspice post-layout simulations using a 180 nm CMOS process. The full-custom layout occupies 2529.49 μm², with robust performance confirmed under parasitic and process variations. Adaptive learning simulations demonstrate the emulator’s artificial synaptic plasticity, highlighting its suitability for neuromorphic computing, chaos-based circuits, and nonlinear dynamical systems. The compact, low-power, and multiplier-free architecture establishes the proposed MT emulator as a practical platform for emerging analog memory-centric applications. To validate the feasibility of the proposed solution, experimental tests are performed using commercially available components. Full article