Search Results (25)

A 10 × 10 µm² radiation-tolerant voltage-domain global shutter pixel with radiation-hardened by design (RHBD) device modification is developed to operate under high ionizing-dose rates and high total ionizing-dose (TID) levels. Therefore, a modified NMOS transistor layout is used in the pixel to achieve radiation hardness. The pixel design is demonstrated to operate up to 1 MGy or 100 Mrad (SiO₂) TID with minimal degradation. The global shutter pixel also includes correlated double sampling (CDS) to reduce noise and the impact of the collected carriers generated by the flux of gamma or X-ray radiation. Combined with an external flash, global shutter operation allows short exposures, which limits the impact of radiation on dark current and dynamic range. The pixel is designed using 180 nm CMOS Image Sensor (CIS) technology. Full article

Bias Temperature Instability (BTI)-induced aging of transistors is a serious concern in modern electronic circuits, yet its effects on the operation of mixed-signal circuits have not been extensively studied. In this work, initially we analyze how BTI-induced aging degradation influences the analog front end of Flash analog-to-digital converters (ADCs). BTI-induced aging leads to substantial increments in the offset voltage of the ADC comparators, which in turn affect their trip point voltage, leading to the alteration of the ADC’s performance characteristics, such as gain, full-scale error and integral nonlinearity. Thus, erroneous responses are generated. Next, we propose a low-cost BTI-induced aging mitigation technique based on a circuit reconfiguration method which periodically alters the average voltage stress on the ADC comparators’ transistors. The proposed method limits the comparators’ offset voltage development, restricting the shift in their trip point voltage. Consequently, the impact of aging on the performance characteristics of the ADC is drastically reduced, and its reliability is improved. According to our simulations, after two years of operation, the gain error is reduced by 95.43%, the full-scale error is reduced by 63.31% and the integral nonlinearity is reduced by 63.00%, with respect to operation without applying the proposed aging mitigation technique. Full article

As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing. Full article

This study presents a photoresist-free patterning method for solution-processed indium zinc oxide (IZO) thin films using two photochemical exposure techniques, namely pulsed ultraviolet (UV) light and UV-ozone, and a plasma-based method using oxygen (O₂) plasma. Pulsed UV light delivers short, high-intensity flashes of light that induce localised photochemical reactions with minimal thermal damage, whereas UV-ozone enables smooth and uniform surface oxidation through continuous low-pressure UV irradiation combined with in situ ozone generation. By contrast, O₂ plasma generates ionised oxygen species via radio frequency (RF) discharge, allowing rapid surface activation, although surface damage may occur because of energetic ion bombardment. All three approaches enabled pattern formation without the use of conventional photolithography or chemical developers, and the UV-ozone method produced the most uniform and clearly defined patterns. The patterned IZO films were applied as active layers in bottom-gate top-contact thin-film transistors, all of which exhibited functional operation, with the UV-ozone-patterned devices exhibiting the most favourable electrical performance. This comparative study demonstrates the potential of photochemical and plasma-assisted approaches as eco-friendly and scalable strategies for next-generation IZO patterning in electronic device applications. Full article

Nanoparticle floating gate (NPFG) transistors have gained attention as synaptic devices due to their discrete charge storage capability, which minimizes leakage currents and enhances the memory window. In this study, we propose and evaluate a mesh-type floating gate transistor (Mesh-FGT) designed to emulate the characteristics of NPFG transistors. Individual floating gates with dimensions of 3 µm × 3 µm are arranged in an array configuration to form the floating gate structure. The Mesh-FGT is composed of an Al/Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/SOI (silicon-on-insulator) stack. Threshold voltages (Vth) extracted from the transfer and output curves followed Gaussian distributions with means of 0.063 V (σ = 0.100 V) and 1.810 V (σ = 0.190 V) for the erase (ERS) and program (PGM) states, respectively. Synaptic potentiation and depression were successfully demonstrated in a multi-level implementation by varying the drain current (I_ds) and Vth. The Mesh-FGT exhibited high immunity to leakage current, excellent repeatability and retention, and a stable memory window that initially measured 2.4 V. These findings underscore the potential of the Mesh-FGT as a high-performance neuromorphic device, with promising applications in array device architectures and neuromorphic neural network implementations. Full article

This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving higher linearity and enabling energy-efficient operation with fewer dynamic current paths. The proposed IMC structure uses a 9T1C bitcell considering the trade-off between the bitcell area and the threshold voltage drop by an NMOS access transistor. We propose an energy-efficient summation mechanism for 4-bit weight rows to perform energy-efficient MAC operations. The generated MAC value is finally returned as a digital value through an analog-to-digital converter (ADC), whose performance is one of the critical components in the overall system. The proposed flash-successive approximation register (SAR) ADC is designed by combining the advantages of flash ADC and SAR ADC and outputs digital values at approximately half the cycle of SAR ADC. The proposed charge-domain IMC is designed and simulated in a 65 nm CMOS process. It achieves 102.4 GOPS throughput and 33.6 TOPS/W energy efficiency at array size of 1 Kb. Full article

This study presents a novel pH sensor platform utilizing charge-trap-flash-type metal oxide semiconductor field-effect transistors (CTF-type MOSFETs) for enhanced sensitivity and self-amplification. Traditional ion-sensitive field-effect transistors (ISFETs) face challenges in commercialization due to low sensitivity at room temperature, known as the Nernst limit. To overcome this limitation, we explore resistive coupling effects and CTF-type MOSFETs, allowing for flexible adjustment of the amplification ratio. The platform adopts a unique approach, employing CTF-type MOSFETs as both transducers and resistors, ensuring efficient sensitivity control. An extended-gate (EG) structure is implemented to enhance cost-effectiveness and increase the overall lifespan of the sensor platform by preventing direct contact between analytes and the transducer. The proposed pH sensor platform demonstrates effective sensitivity control at various amplification ratios. Stability and reliability are validated by investigating non-ideal effects, including hysteresis and drift. The CTF-type MOSFETs’ electrical characteristics, energy band diagrams, and programmable resistance modulation are thoroughly characterized. The results showcase remarkable stability, even under prolonged and repetitive operations, indicating the platform’s potential for accurate pH detection in diverse environments. This study contributes a robust and stable alternative for detecting micro-potential analytes, with promising applications in health management and point-of-care settings. Full article

Flash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overcome this trade-off; the best comparators were selected upfront (either at start-up or in the factory), and the unused comparators could be switched off. This work studies the possibility of performing comparator selection in the background concurrently with normal conversion to increase the converter lifetime. Thus, the system can automatically recover its performance from drifts or failures due to aging, temperature, etc. This paper proposes an embedded solution that includes a calibration stimulus generator (which only requires some external passive elements) and develops system design requirements. In addition, mathematical equations and error sensitivities of the system elements were derived. A 6b flash converter is implemented in UMC180nm technology, and transistor-level simulations of the system are provided to demonstrate the feasibility of the proposed system. Full article

Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process. Full article

Artificial intelligence has made people’s demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method for neural morphology computation has problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read and write to build a convolutional neural network structure to improve the performance of neural morphological computing. In the experiment, floating-gate transistors were used to simulate neural network synapses to design core cross-array circuits. A voltage subtractor, voltage follower and ReLU activation function are designed based on a differential amplifier. An Iris dataset was introduced in this experiment to conduct simulation experiments on the research circuit. The IMC circuit designed for this experiment has high performance, with an accuracy rate of 96.2% and a recall rate of 60.2%. The overall current power consumption of the hardware circuit is small, and the current power consumption of the subtractor circuit and ReLU circuit does not exceed 100 µA, while the power consumption of the negative feedback circuit is about 440 mA. The accuracy of analog circuits under the IMC architecture is above 93%, the energy consumption is only about 360 nJ, and the recognition rate is about 12 μs. Compared with the classic von Neumann architecture, it reduces the circuit recognition rate and power consumption while meeting accuracy requirements. Full article

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (V_db) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of V_db (V_{db_max}), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of V_{db_max} and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash. Full article

It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, “there’s plenty of room at the top”. The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF₆/O₂ is one of the most frequently applied. Therefore, having a predictive model for this process is indispensable in the design cycle of semiconductor devices. In this work, we implement a physical SF₆/O₂ plasma etching model which is based on Langmuir adsorption and is calibrated and validated to published equipment parameters. The model is implemented in a broadly applicable in-house process simulator ViennaPS, which includes Monte Carlo ray tracing and a level set-based surface description. We then use the model to study the impact of the mask geometry on the feature profile, when etching through circular and rectangular mask openings. The resulting dimensions of a cylindrical hole or trench can vary greatly due to variations in mask properties, such as its etch rate, taper angle, faceting, and thickness. The peak depth for both the etched cylindrical hole and trench occurs when the mask is tapered at about 0.5°, and this peak shifts towards higher angles in the case of high passivation effects during the etch. The minimum bowing occurs at the peak depth, and it increases with an increasing taper angle. For thin-mask faceting, it is observed that the maximum depth increases with an increasing taper angle, without a significant variation between thin masks. Bowing is observed to be at a maximum when the mask taper angle is between 15° and 20°. Finally, the mask etch rate variation, describing the etching of different mask materials, shows that, when a significant portion of the mask is etched away, there is a notable increase in vertical etching and a decrease in bowing. Ultimately, the implemented model and framework are useful for providing a guideline for mask design rules. Full article

Two-dimensional (2D) materials are considered attractive semiconducting layers for emerging field-effect transistors owing to their unique electronic and optoelectronic properties. Polymers have been utilized in combination with 2D semiconductors as gate dielectric layers in field-effect transistors (FETs). Despite their distinctive advantages, the applicability of polymer gate dielectric materials for 2D semiconductor FETs has rarely been discussed in a comprehensive manner. Therefore, this paper reviews recent progress relating to 2D semiconductor FETs based on a wide range of polymeric gate dielectric materials, including (1) solution-based polymer dielectrics, (2) vacuum-deposited polymer dielectrics, (3) ferroelectric polymers, and (4) ion gels. Exploiting appropriate materials and corresponding processes, polymer gate dielectrics have enhanced the performance of 2D semiconductor FETs and enabled the development of versatile device structures in energy-efficient ways. Furthermore, FET-based functional electronic devices, such as flash memory devices, photodetectors, ferroelectric memory devices, and flexible electronics, are highlighted in this review. This paper also outlines challenges and opportunities in order to help develop high-performance FETs based on 2D semiconductors and polymer gate dielectrics and realize their practical applications. Full article

This paper presents a synaptic driving circuit design for processing in-memory (PIM) hardware with a thin-film transistor (TFT) embedded flash (eFlash) for a binary/ternary-weight neural network (NN). An eFlash-based synaptic cell capable of programming negative weight values to store binary/ternary weight values (i.e., ±1, 0) and synaptic driving circuits for erase, program, and read operations of synaptic arrays have been proposed. The proposed synaptic driving circuits improve the calculation accuracy of PIM operation by precisely programming the sensing current of the eFlash synaptic cell to the target current (50 nA ± 0.5 nA) using a pulse train. In addition, during PIM operation, the pulse-width modulation (PWM) conversion circuit converts 8-bit input data into one continuous PWM pulse to minimize non-linearity in the synaptic sensing current integration step of the neuron circuit. The prototype chip, including the proposed synaptic driving circuit, PWM conversion circuit, neuron circuit, and digital blocks, is designed and laid out as the accelerator for binary/ternary weighted NN with a size of 324 × 80 × 10 using a 0.35 μm CMOS process. Hybrid bonding technology using bump bonding and wire bonding is used to package the designed CMOS accelerator die and TFT eFlash-based synapse array dies into a single chip package. Full article

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry. Full article