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Open AccessArticle

Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

by Yinhua Cui 1,†, Jeong Yeul Jeong 2,†, Yuan Gao 1 and Sung Gyu Pyo 1,*
1
School of Integrative Engineering, Chung-Ang University, Seoul 06974, Korea
2
Process Development Center, Magnachip Semiconductor, Seoul 15213, Korea
*
Author to whom correspondence should be addressed.
These two authors contributed equally to this work.
Micromachines 2020, 11(1), 32; https://doi.org/10.3390/mi11010032
Received: 29 November 2019 / Revised: 17 December 2019 / Accepted: 24 December 2019 / Published: 25 December 2019
(This article belongs to the Special Issue Selected Papers from the ICAE 2019)
This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etching 200 Å IMP Ti (ion metal plasma titanium) 200 Å CVD TiN (titanium nitride deposited by chemical vapor deposition) 2 × 50 Å. The resistivities of the glue layer and barrier, i.e., IMP Ti and CVD TiN, were 73 and 280 μΩ·cm, respectively, and the bottom coverages were 57% and 80%, respectively, at a 3.2:1 aspect ratio (A/R). The specific resistance of the tungsten film was approximately 11.5 μΩ·cm, and it was confirmed that the via filling could be performed smoothly. RF etching and IMP Ti should be at least 200 Å each, and CVD TiN can be performed satisfactorily with the existing 2 × 50 Å process. Tungsten deposition showed no difference in the via resistance with deposition temperature and SiH4 reduction time. When the barrier scheme of RF etching 200 Å IMP Ti 200 ÅCVD TiN 2 × 50 Å was applied, the via resistance was less than 20 Ω, even with a side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm. View Full-Text
Keywords: multilevel metallization; logic device; RF etching multilevel metallization; logic device; RF etching
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MDPI and ACS Style

Cui, Y.; Jeong, J.Y.; Gao, Y.; Pyo, S.G. Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices. Micromachines 2020, 11, 32.

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