A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme
by
Ching-Lin Fan 1,2,*, Ming-Chi Shang 1, Bo-Jyun Li 1, Yu-Zuo Lin 2, Shea-Jue Wang 3 and Win-Der Lee 4
Ching-Lin Fan 1,2,*, Ming-Chi Shang 1, Bo-Jyun Li 1, Yu-Zuo Lin 2, Shea-Jue Wang 3 and Win-Der Lee 4
1
Graduate Institute of Electro-Optical Engineering, National Taiwan University of Science and Technology, Taipei City 106, Taiwan
2
Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei City 106, Taiwan
3
Institute of Materials Science and Engineering, National Taipei University of Technology, Taipei City 106, Taiwan
4
Department of Electrical Engineering, Lee-Ming Institute of Technology, New Taipei City 243, Taiwan
*
Author to whom correspondence should be addressed.
Materials 2014, 7(8), 5761-5768; https://doi.org/10.3390/ma7085761
Received: 26 June 2014 / Revised: 24 July 2014 / Accepted: 30 July 2014 / Published: 11 August 2014
(This article belongs to the Special Issue Compound Semiconductor Materials 2014)
Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm2/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.
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Keywords:
amorphous indium–gallium–zinc–oxide (a-IGZO); back-side exposure; self-aligned process; thin-film transistor (TFT); two-photo-mask process; backside-lift-off (BLO)
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MDPI and ACS Style
Fan, C.-L.; Shang, M.-C.; Li, B.-J.; Lin, Y.-Z.; Wang, S.-J.; Lee, W.-D. A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme. Materials 2014, 7, 5761-5768.
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