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Open AccessArticle

High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications

1
Department of Information Engineering, University of Padova, 35151 Padova, Italy
2
Fraunhofer Institute for Integrated Systems and Device Technology IISB, 91058 Erlangen, Germany
3
IEMN-CNRS, 59652 Villeneuve d’Ascq, France
4
EpiGaN, 3500 Hasselt, Belgium
*
Authors to whom correspondence should be addressed.
Materials 2020, 13(19), 4271; https://doi.org/10.3390/ma13194271
Received: 3 August 2020 / Revised: 12 September 2020 / Accepted: 16 September 2020 / Published: 25 September 2020
(This article belongs to the Section Electronic Materials)
The aim of this work is to demonstrate high breakdown voltage and low buffer trapping in superlattice GaN-on-Silicon heterostructures for high voltage applications. To this aim, we compared two structures, one based on a step-graded (SG) buffer (reference structure), and another based on a superlattice (SL). In particular, we show that: (i) the use of an SL allows us to push the vertical breakdown voltage above 1500 V on a 5 µm stack, with a simultaneous decrease in vertical leakage current, as compared to the reference GaN-based epi-structure using a thicker buffer thickness. This is ascribed to the better strain relaxation, as confirmed by X-Ray Diffraction data, and to a lower clustering of dislocations, as confirmed by Defect Selective Etching and Cathodoluminescence mappings. (ii) SL-based samples have significantly lower buffer trapping, as confirmed by substrate ramp measurements. (iii) Backgating transient analysis indicated that traps are located below the two-dimensional electron gas, and are related to CN defects. (iv) The signature of these traps is significantly reduced on devices with SL. This can be explained by the lower vertical leakage (filling of acceptors via electron injection) or by the slightly lower incorporation of C in the SL buffer, due to the slower growth process. SL-based buffers therefore represent a viable solution for the fabrication of high voltage GaN transistors on silicon substrate, and for the simultaneous reduction of trapping processes. View Full-Text
Keywords: GaN; high-electron-mobility transistor (HEMT); trapping effect back-gating analysis GaN; high-electron-mobility transistor (HEMT); trapping effect back-gating analysis
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MDPI and ACS Style

Tajalli, A.; Meneghini, M.; Besendörfer, S.; Kabouche, R.; Abid, I.; Püsche, R.; Derluyn, J.; Degroote, S.; Germain, M.; Meissner, E.; Zanoni, E.; Medjdoub, F.; Meneghesso, G. High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications. Materials 2020, 13, 4271. https://doi.org/10.3390/ma13194271

AMA Style

Tajalli A, Meneghini M, Besendörfer S, Kabouche R, Abid I, Püsche R, Derluyn J, Degroote S, Germain M, Meissner E, Zanoni E, Medjdoub F, Meneghesso G. High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications. Materials. 2020; 13(19):4271. https://doi.org/10.3390/ma13194271

Chicago/Turabian Style

Tajalli, Alaleh; Meneghini, Matteo; Besendörfer, Sven; Kabouche, Riad; Abid, Idriss; Püsche, Roland; Derluyn, Joff; Degroote, Stefan; Germain, Marianne; Meissner, Elke; Zanoni, Enrico; Medjdoub, Farid; Meneghesso, Gaudenzio. 2020. "High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications" Materials 13, no. 19: 4271. https://doi.org/10.3390/ma13194271

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