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Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

Jozef Stefan Institute, Jamova 39, Ljubljana 1000, Slovenia
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Sensors 2013, 13(5), 6405-6422; https://doi.org/10.3390/s130506405
Received: 30 March 2013 / Revised: 24 April 2013 / Accepted: 3 May 2013 / Published: 14 May 2013
(This article belongs to the Section Physical Sensors)
Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load. View Full-Text
Keywords: data compression; LIDAR; FPGA; hardware acceleration data compression; LIDAR; FPGA; hardware acceleration
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MDPI and ACS Style

Biasizzo, A.; Novak, F. Hardware Accelerated Compression of LIDAR Data Using FPGA Devices. Sensors 2013, 13, 6405-6422. https://doi.org/10.3390/s130506405

AMA Style

Biasizzo A, Novak F. Hardware Accelerated Compression of LIDAR Data Using FPGA Devices. Sensors. 2013; 13(5):6405-6422. https://doi.org/10.3390/s130506405

Chicago/Turabian Style

Biasizzo, Anton, and Franc Novak. 2013. "Hardware Accelerated Compression of LIDAR Data Using FPGA Devices" Sensors 13, no. 5: 6405-6422. https://doi.org/10.3390/s130506405

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