Search Results (42)

This paper presents a broadband omnidirectional rectenna combined with a solar cell for hybrid energy harvesting, addressing the daytime-only limitation of solar cells via complementary RF energy harvesting. To avoid mutual interaction in integration, the solar cell is placed above the antenna to receive light/EM waves from different directions. A broadband discone antenna ensures omnidirectional RF reception from 1.56 to 6.63 GHz, while a single-stub matching circuit and voltage doubler enable rectifier operation from 1.4 to 3.6 GHz, with over 50% power conversion efficiency at 5 dBm. The measurement demonstrates that the hybrid system can yield 20.25 mW from combined RF/solar power. This broadband hybrid energy harvesting system shows potential for powering sensors throughout the day by integrating two complementary energy sources with minimal interaction. Full article

A battery charger for solid-state lithium battery packs was developed and implemented. The power stage used a phase-shifted full-bridge converter integrated with a current-doubler rectifier and synchronous rectification. Dual voltage and current control loops were employed to enable constant-voltage and constant-current charging modes. To improve the lifespan of the output filter capacitor, the current-doubler rectifier was adopted to effectively reduce output current ripple. During the initial start-up phase, as the charger transitions from constant-voltage to constant-current output mode, the use of proportional–integral control in the voltage and current loop error amplifiers may cause current overshoot during the step-rising phase, primarily due to the integral action. Therefore, this study incorporated fuzzy control, proportional control, and proportional–integral control strategies into the current-loop error amplifier. This approach effectively reduced the current overshoot during the step-rising phase, preventing the charger from mistakenly triggering the overcurrent protection mode. The analysis and design considerations of the proposed circuit topology and control loop are presented. Experimental results agree with theoretical predictions, thereby confirming the validity of the proposed approach. Full article

The advancement of Internet of Things (IoT) technology has enabled battery-powered devices to be deployed across a wide range of applications; however, it also introduces challenges such as high energy consumption and security vulnerabilities. To address these issues, adiabatic logic circuits offer a promising solution for achieving energy efficiency and enhancing the security of IoT devices. Adiabatic logic circuits are well suited for energy harvesting systems, especially in applications such as sensor nodes, RFID tags, and other IoT implementations. In these systems, the harvested bipolar sinusoidal RF power is directly used as the power supply for the adiabatic logic circuit. However, adiabatic circuits require a peak detector to provide bulk biasing for pMOS transistors. To meet this requirement, a diode-connected MOS transistor-based voltage doubler circuit is used to convert the sinusoidal input into a usable DC signal. In this paper, we propose a novel adiabatic logic design that maintains low power consumption while optimizing energy and current fluctuations across various input transitions. By ensuring uniform and complementary current flow in each transition within the logic circuit’s functional blocks, the design reduces energy variation and enhances resistance against power analysis attacks. Evaluation under different clock frequencies and load capacitances demonstrates that the proposed adiabatic logic circuit exhibits lower fluctuation and improved security, particularly at load capacitances of 50 fF and 100 fF. The results show that the proposed circuit achieves lower power dissipation compared to conventional designs. As an application example, we implemented an ultrasonic transmitter circuit within a LoRaWAN network at the end-node sensor level, which serves as both a communication protocol and system architecture for long-range communication systems. Full article

This paper presents a CMOS-based optoelectronic receiver integrated circuit (CORIC) realized in a standard 180 nm CMOS technology for the applications of short-distance optical interconnects. The CORIC comprises a spatially modulated P⁺/N-well on-chip avalanche photodiode (P⁺/NW APD) for optical-to-electrical conversion, a dummy APD at the differential input for enhanced common-mode noise rejection, a cross-coupled differential transimpedance amplifier (CCD-TIA) for current-to-voltage conversion, a 3-bit continuous-time linear equalizer (CTLE) for adaptive equalization by using NMOS registers, and a $f_T$-doubler output buffer (OB). The CTLE and $f_T$-doubler OB combination not only compensates the frequency-dependent signal loss, but also provides symmetric differential output signals. Post-layout simulations of the proposed CORIC reveal a transimpedance gain of 53.2 dBΩ, a bandwidth of 4.83 GHz even with a 490 fF parasitic capacitance from the on-chip P⁺/NW APD, a dynamic range of 60 dB that handles the input photocurrents from 1 μA_pp to 1 mA_pp, and a DC power consumption of 33.7 mW from a 1.8 V supply. The CORIC chip core occupies an area of 260 × 101 μm². Full article

The LLC resonant converter is widely recognized as an effective solution for achieving high efficiency in high-frequency operations. This is primarily due to its ability to perform zero-voltage switching (ZVS) on primary switches and zero-current switching (ZCS) on secondary rectifier switches. However, implementing the secondary rectifier of an LLC resonant converter often requires the use of jumpers on the PCB to construct circuit topologies such as the center-tap rectifier (CTR), full-bridge rectifier, and voltage-doubler rectifier (VDR). In conventional VDR configurations, the source voltage of the high-side FET fluctuates according to the switching operation of the primary switch. This fluctuation necessitates auxiliary windings or bootstrap circuits to provide a floating voltage source, adding significant complexity to gate drive circuits in high-power-density applications. This complexity poses a major barrier to the practical adoption of VDRs. To address these challenges, this paper proposes a novel rectification circuit based on the VDR topology, specifically designed for LLC resonant converters, offering simplified gate drive circuitry and improved suitability for high-power-density applications. Full article

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology. Full article

The ambipolar conduction property of graphene field-effect transistors (GFETs) and the inherent square-like dependence of the drain current on the gate voltage, enable the development of single-device architectures for analog nonlinear radiofrequency (RF) circuits. The use of GFETs in novel RF component topologies allows leveraging graphene’s attractive thermal and mechanical properties to improve the miniaturization and weight reduction of electronic components. These features are specifically appealing for integrated sensing, modulation, and transmission systems. However, given the innovative nature of emerging graphene-based technology, a complete performance analysis of any novel electronic component is essential for customizing the operating conditions accordingly. This paper presents a comprehensive circuital analysis of a GFET-based frequency doubler, exploiting a compact model for GFET circuit simulation to assess the device’s performance parameters, including power conversion gain bandwidth and saturation. The performed analysis proposes to support the design of GFET-based harmonic transponders, offering integrated sensing and signal manipulation capabilities. Full article

In this study, a frequency doubler that consists of a tunnel field-effect transistor (TFET) with dual pocket doping is proposed, and its operation is verified using technology computer-aided design (TCAD) simulations. The frequency-doubling operation is important to having symmetrical current characteristics, which eliminate odd harmonics and the need for extra filter circuitry. The proposed TFET has intrinsically bidirectional and controllable currents that can be implemented by pocket doping, which is located at the junction between the source/drain (S/D) and the channel region, to modify tunneling probabilities. The source-to-channel (I_SC) and channel-to-drain currents (I_CD) can be independently changed by managing each pocket doping concentration on the source and drain sides (N_S,POC and N_D,POC). After that, the current matching process was investigated through N_S,POC and N_D,POC splits, respectively. However, it was found that the optimized doping condition achieved at the device level (namely, a transistor evaluation) is not suitable for a frequency doubler operation because the voltage drop generated by a load resistor in the frequency doubler circuit configuration causes the currents to be unbalanced between I_SC and I_CD. Therefore, after symmetrical current matching was performed by optimizing N_S,POC and N_D,POC at the circuit level, it was clearly seen that the output frequency was doubled in comparison to the input sinusoidal signal. In addition, the effects of the S/D and pocket doping variations that can occur during process integration were investigated to determine how much frequency multiplications are affected, and these variations have the immunity of S/D doping and pocket doping length changes. Furthermore, the impact of device scaling with gate length (L_G) variations was evaluated. Based on these findings, the proposed frequency doubler is anticipated to offer benefits for circuit design and low-power applications compared to the conventional one. Full article

In the realm of electric vehicles (EVs), achieving diverse direct current (DC) voltage levels is essential to meet varying electrical load demands. This requires meticulous control of the battery voltage, which must be adjusted in line with specific load characteristics. Therefore, the integration of a well-designed power converter circuit is crucial, as it plays a pivotal role in generating different DC voltage outputs. In this study, we also consider the incorporation of two additional doubler/divider circuits at the end of the proposed converter, further enhancing its capacity to produce distinct DC voltage levels, thus increasing its versatility. The standout feature of the proposed converter lies in its remarkable ability to amplify DC voltages significantly. For instance, when the input battery voltage is set at 48 VDC with a duty cycle (D) of 0.8, the resulting output demonstrates a remarkable augmentation, producing voltages 18, 36, and 72 times higher than the input voltage. Conversely, with a reduced D of 0.2 while maintaining the input voltage at 48 VDC, the converter yields diminished voltages of 0.1875, 0.375, and 0.75 times the initial voltage. This adaptability, based on the parameterization of D, underscores the converter’s ability to cater to a wide range of voltage requirements. To oversee the intricate operations of this versatile converter, a high-speed DSP-based controller system is employed. It utilizes the renowned PID approach, known for its proficiency in navigating complex, nonlinear systems. Experimental results validate the theoretical and simulation findings, reaffirming the converter’s practical utility in EV applications. The study introduces a simple control mechanism with a single power switch, high efficiency for high-power applications, wide voltage range, especially with VDC and VMC cells, and continuous current operation for the load in CCM mode. This study underscores the significance of advanced power conversion systems in shaping the future of electric transportation. Full article

This paper presents the deployment of a hybrid energy harvesting system that combines a wireless energy harvesting (EH) system and a 6 V, 170 mA monocrystalline solar energy derived from the Sun’s rays. The hybrid energy harvesting (HEH) system comprises the rectifier, the solar cell panel, the charging circuit, and the EM4325 embedded RFID tag. This study aims to design an efficient EH system capable of increasing the read range of an active RFID tag. The proposed approach integrates a meandered line radio frequency identification (RFID) tag with an EM4325 IC chip as the receiver antenna. A halfwave doubler RF rectifier circuit is connected to the antenna using a 50 Ω SMA connector to convert the captured RF waves into usable electrical power. A solar energy charging module equipped with a Maximum Power Point Tracking (MPPT) system, a rechargeable lithium-ion battery, and a DC-DC converter is configured to manage and store the harvested energy efficiently. The UHF tag antenna operates at 919 MHz, achieving a peak gain of 3.54 dB. The proposed rectenna achieves a maximum measured harvested power conversion efficiency (PCE) of 55.14% for an input power (Pin) of 15 dBm at a distance of 5.10 cm, while the solar cell panel realizes 3.92 W of power. Experimental results demonstrate the hybrid harvester system’s effectiveness, achieving a PCE of 86.49% at an output voltage (VDC) of 5.35 V. The main advantage of this approach is the creation of a compact hybrid RF and solar EH system by combining the solar cell panel with the antenna, thus enabling multi-functionality. Full article

A comprehensive model for micro-powered piezoelectric generator (PG), analysis of operation, and control of voltage doubler joule thief (VDJT) circuit to find the piezoelectric devices (PD’s) optimum functioning points are discussed in the present article. The proposed model demonstrates the power dependence of the PG on mechanical excitation, frequency, and acceleration, as well as outlines the load behaviour for optimal operation. The proposed VDJT circuit integrates the combination of voltage doubler (VD) and joule thief circuit, whereas the VD circuit works in Stage 1 for AC (alternating current)–DC (direct current) conversion, while a joule thief circuit works in Stage 2 for DC–DC conversion. The proposed circuit functions as an efficient power converter, which converts power from AC–DC and boosts the voltage from low to high without employing any additional electronic components and generating duty cycles. The electrical nature of the input (i.e., PD) of a VDJT circuit is in perfect arrangement with the investigated optimisation needs when using the proposed control circuit. The effectiveness of the proposed VDJT circuit is examined in terms of both simulation and experiment, and the results are presented. The proposed circuit’s performance was validated with available results of power electronics interfaces in the literature. The proposed circuit’s flexibility and controllability can be used for various applications, including mobile battery charging and power harvesting. Full article

With low-power gadgets proliferating, the development of a small, effective rectenna is crucial for wirelessly energizing devices. A simple circular patch with a partial ground plane for RF-energy harvesting at ISM (2.45 GHz) band is proposed in this work. The simulated antenna resonates at 2.45 GHz with an input impedance of 50 Ω and a gain of 2.38 dBi. An L-section matching a circuit with a voltage doubler is proposed to provide excellent RF-to-DC transformation efficiency at low power input. The proposed rectenna is fabricated and the results show that the return loss and realized gain have good characteristics at the ISM band with 52% of RF-to-DC transformation efficiency, with an input of 0 dBm power. The projected rectenna is apt for power-up low sensor nodes in wireless sensor applications. Full article

This paper describes the detailed modelling of a vibration-based miniature piezoelectric device (PD) and the analysis modes of operation and control of a voltage doubler boost converter (VDBC) circuit to find the PD’s optimal operating conditions. The proposed VDBC circuit integrates a conventional voltage doubler (VD) circuit with a step-up DC-DC converter circuit in modes 1–4, while a non-linear synchronisation procedure of a conventional boost converter circuit is employed in modes 5–6. This integration acted as the voltage boost circuit without utilising duty cycles and complex auxiliary switching components. In addition, the circuit does not require external trigger signals to turn on the bidirectional switches. This facilitates the operation of VDBC circuit at very low AC voltage (V_ac ≥ 0.5 V). Besides this, the electrical characteristics of VDBC circuit’s input (i.e., PD) perfectly concurs with the studied testing scenarios using impedance power sources (mechanical shaker). Firstly, the proposed circuit which can rectify the PD’s output was tested at both constant input voltage with varying excitation frequency and constant excitation frequency with varying input voltage. Next, a small-scale solar battery was charged to validate the feasibility of the performance of the proposed VDBC circuit. The proposed circuit achieved a maximum output voltage of 11.7 V_dc with an output power of 1.37 mW. In addition, the rectified voltage waveform is stable due to the sminimisation of the ripples. In addition, the performance of VDBC circuit was verified by comparing the achieved results with previously published circuits in the literature. The results show that the proposed VDBC circuit outperformed existing units as described in the literature regarding output voltage and power. The developed rectifier circuit is suitable for various real-life applications such as energy harvesting and battery charging. Full article

The step-up DC–DC converter is widely used for applications such as IoT sensor nodes, energy harvesting, and photovoltaic (PV) systems. In this article, a new topological quasi-Z-source (QZ) high step-up DC–DC converter for the PV system is proposed. The topology of this converter is based on the voltage-doubler circuits. Compared with a conventional quasi-Z-source DC–DC converter, the proposed converter features low voltage ripple at the output, the use of a common ground switch, and low stress on circuit components. The new topology, named a low-side-drive quasi-Z-source boost converter (LQZC), consists of a flying capacitor (C_F), the QZ network, two diodes, and a N-channel MOS switch. A 60 W laboratory prototype DC–DC converter achieved 94.9% power efficiency. Full article

This paper discusses a design methodology to efficiently determine the best combination of rectenna (rectifier and antenna) to minimize the input power under a given output condition for microwave wireless power transfer (MWPT) without any other external components, such as a matching network, for cost reduction. A linearized equivalent circuit model is expanded upon to include the microstrip line connecting the antenna and rectifier. Based on the model, the design flow is presented that has mainly three steps: (1) Determination of the equivalent rectifier input impedance and the amplitude of input voltage by running SPICE simulation, (2) Drawing contour plots of input power by rectifier candidate on the antenna impedance plane by conducting model calculation and impedance loci of antenna candidates on the contour plots, and (3) Selecting the combination of antenna and rectifier which gives the minimum input power for all the combinations. To validate the equivalent circuit model and design flow, a single-diode (SD) rectifier and a voltage-doubler (VD) rectifier were fabricated in 65 nm CMOS. The input power to generate 100 μA at 1 Vdc was measured and compared. The model, SPICE and measurement are in good agreement with each other that VD has 30–50% lower input power than SD does. In addition, the sensitivity of the parasitic elements, such as the microstrip line and the bonding wires and pads on the input power, are investigated to explore the design space for rectenna. Full article