Search Results (438)

The increasing demand for noninvasive inspection (NII) of complex civil infrastructures requires overcoming the limitations of traditional ground-penetrating radar (GPR) systems in addressing diverse and large-scale applications. The solution proposed in this study focuses on an initial design that integrates a low-SWaP (Size, Weight, and Power) ultra-wideband (UWB) impulse radar with realistic electromagnetic modeling for deployment on unmanned aerial vehicles (UAVs). The system incorporates ultra-realistic antenna and propagation models, utilizing Finite Difference Time Domain (FDTD) solvers and multilayered media, to replicate realistic airborne sensing geometries. Verification and calibration are performed by comparing simulation outputs with laboratory measurements using varied material samples and target models. Custom signal processing algorithms are developed to extract meaningful features from complex electromagnetic environments and support anomaly detection. Additionally, machine learning (ML) techniques are trained on synthetic data to automate the identification of structural characteristics. The results demonstrate accurate agreement between simulations and measurements, as well as the potential for deploying this design in flight tests within realistic environments featuring complex electromagnetic interference. Full article

This paper deals with a standard cell-based analog-in-concept pW-power building block as a comparator and a wake-up oscillator. Both topologies, traditionally conceived as an analog building block made by a custom process and supply voltage-dependent design flow, are designed only by using digital gates, enabling them to be automated and fully synthesizable. This further results in supply voltage scalability and regulator-less operation, allowing direct powering by an energy harvester without additional ancillary circuit blocks (such as current and voltage sources). In particular, the circuit similarities in implementing a rail-to-rail dynamic voltage comparator and a relaxation oscillator using only digital gates are discussed. The building blocks previously reported in the literature by the author will be described, and the common root of their design will be highlighted. Full article

This study presents transistor-level simulation results for a novel memristor emulator circuit. The design incorporates an inverter and a current-mode-controlled operational transconductance amplifier to stabilize the output voltage. Transient performance is evaluated across a 20 MHz to 100 MHz frequency range. Simulations using 0.18 μm TSMC technology confirm the circuit’s functionality, demonstrating a power consumption of 0.1 mW at a 1.2 V supply. The memristor model’s reliability is verified through corner simulations, along with Monte Carlo and temperature variation tests. Furthermore, the emulator is applied in a Memristive Integrate-and-Fire neuron circuit, a CMOS-based system that replicates biological neuron behavior for spike generation, enabling ultra-low-power computing and advanced processing in retinal prosthesis applications. Full article

In air-conditioning compressors operating under ultra-low temperature conditions, both the rotational speed and load torque are at high levels, demanding pump motors that offer high efficiency and high power at high speeds. Electrically excited synchronous motors (EESMs) satisfy these operational requirements by leveraging their inherent wide-speed field-weakening capability and superior high-speed performance characteristics. Current research on EESM primarily targets electric vehicle applications, with a high-efficiency design focused on medium and low speeds. Excitation design under constant-power–speed extension remains insufficiently explored. To address it, this paper proposes an EESM design methodology optimized for high-speed efficiency and constant-power excitation control. Key EESM parameters are determined through a dynamic phasor diagram, and design methods for turn number, split ratio, and other parameters are proposed to extend the high-efficiency region into the high-speed range. Additionally, a power output modulation strategy in the field-weakening region is introduced, enabling dynamic high-power regulation at high speed through excitation adjustment. Compared to similarly sized PMSMs, the proposed EESM exhibits consistently superior efficiency beyond 10,000 rpm, delivering 19% and 49% higher power output at 12,000 rpm and 14,000 rpm, respectively, relative to conventional pump-drive PMSMs. Experimental validation via a prototype confirms excellent high-speed efficiency and sustained constant-power performance, in alignment with the design targets. Full article

To address the challenges of prolonged current isolation times and high dependency on varistors in traditional flexible short-circuit fault isolation schemes for DC systems, this paper proposes a rapid fault isolation circuit design based on an adaptive solid-state circuit breaker (SSCB). By introducing an adaptive current-limiting branch topology, the proposed solution reduces the risk of system oscillations induced by current-limiting inductors during normal operation and minimizes steady-state losses in the breaker. Upon fault occurrence, the current-limiting inductor is automatically activated to effectively suppress the transient current rise rate. An energy dissipation circuit (EDC) featuring a resistor as the primary energy absorber and an auxiliary varistor (MOV) for voltage clamping, alongside a snubber circuit, provides an independent path for inductor energy release after faults. This design significantly alleviates the impact of MOV capacity constraints on the fault isolation process compared to traditional schemes where the MOV is the primary energy sink. The proposed topology employs a symmetrical bridge structure compatible with both pole-to-pole and pole-to-ground fault scenarios. Parameter optimization ensures the IGBT voltage withstand capability and energy dissipation efficiency. Simulation and experimental results demonstrate that this scheme achieves fault isolation within 0.1 ms, reduces the maximum fault current-to-rated current ratio to 5.8, and exhibits significantly shorter isolation times compared to conventional approaches. This provides an effective solution for segment switches and tie switches in millisecond-level self-healing systems for both low-voltage (LVDC, e.g., 750 V/1500 V DC) and medium-voltage (MVDC, e.g., 10–35 kV DC) smart DC distribution grids, particularly in applications demanding ultra-fast fault isolation such as data centers, electric vehicle (EV) fast-charging parks, and shipboard power systems. Full article

The shortage of tellurium and toxicity of lead are major obstacles to scaling mid-temperature thermoelectric generators. We engineer quaternary lead chalcogenides with composition (Pb_0.8Ge_0.2Te)_0.95-x(PbSe)_0.05(PbS)_x (0 ≤ x ≤ 0.25), where Pb is lead, Ge is germanium, Te is tellurium, Se is selenium, S is sulfur, and x denotes the molar fraction of lead sulfide (PbS). The primary novelty lies in achieving ultra-low thermal conductivity through controlled phase segregation induced by systematic PbS incorporation. X-ray diffraction analysis reveals single-phase solid solutions up to x ≈ 0.10, with secondary PbS precipitates forming beyond this threshold. These PbS-rich phases create hierarchical microstructures that scatter phonons across multiple length scales, suppressing total thermal conductivity to 0.6 Wm⁻¹K⁻¹ at x = 0.15—approximately 84% lower than pristine lead telluride (PbTe) and approaching glass-like thermal conductivity values. Electrical transport measurements demonstrate sulfur’s role as an electron donor, enabling carrier-type control from p-type to n-type conduction. Despite moderate electrical power factors, the optimized composition (x = 0.20) achieves a peak dimensionless figure of merit ZT ≈ 0.34 at 650 K. This work demonstrates an effective strategy for tellurium-lean, lead-reduced thermoelectric materials through sulfur-induced phase segregation, providing practical design guidelines for sustainable waste heat recovery applications. Full article

Partial discharge (PD) in insulators will not only lead to the gradual degradation of insulation performance but even cause power system failure in serious cases. Because there is strong noise interference in the field, it is difficult to accurately locate the position of the PD source. Therefore, this paper proposes a three-dimensional spatial localization method of the PD source with a four-element ultra-high-frequency (UHF) array based on improved wavelet packet dynamic threshold denoising and the $G_{xx}-\beta$ generalized cross-correlation algorithm. Firstly, considering the field noise interference, the PD signal is decomposed into sub-signals with different frequency bands by the wavelet packet, and the corresponding wavelet packet coefficients are extracted. By using the improved threshold function to process the wavelet packet coefficients, the PD signal with low distortion rate and high signal-to-noise ratio (SNR) is reconstructed. Secondly, in order to solve the problem that the amplitude of the first wave of the PD signal is small and the SNR is low, an improved weighting function, $G_{xx}-\beta$, is proposed, which is based on the self-power spectral density of the signal and is adjusted by introducing an exponential factor to improve the accuracy of the first wave arrival time and time difference calculation. Finally, the influence of different sensor array shapes and PD source positions on the localization results is analyzed, and a reasonable arrangement scheme is found. In order to verify the performance of the proposed method, simulation and experimental analysis are carried out. The results show that the improved wavelet packet denoising algorithm can effectively realize the separation of PD signal and noise and improve the SNR of the localization signal with low distortion rate. The improved $G_{xx}-\beta$ weighting function significantly improves the estimation accuracy of the time difference between UHF sensors. With the sensor array designed in this paper, the relative localization error is 3.46%, and the absolute error is within 6 cm, which meets the requirements of engineering applications. Full article

This study presents the optimization of a laser ablation process designed to achieve the precise removal of polyamide coatings from ultra-thin platinum wires. Removing polymer coatings is a critical challenge in high-reliability manufacturing processes such as aerospace thermocouple fabrication. The ablation process must not only ensure the complete removal of the polyamide insulation but also maintain the tensile strength of the wire to withstand mechanical handling in subsequent manufacturing stages. Additionally, the exposed platinum surface must exhibit low surface roughness to enable effective soldering and be free of thermal damage or residual debris to pass strict visual inspections. The wires have a total diameter of 65 µm, consisting of a 50 µm platinum core encased in a 15 µm polyamide coating. By utilizing a UV laser with a wavelength of 355 nm, average power of 3 W, a repetition rate range of 20 to 200 kHz, and a high-speed marking system, the process parameters were systematically refined. Initial attempts to perform the ablation in an air medium were unsuccessful due to inadequate thermal control and incomplete removal of the polyamide coating. Hence, a water-assisted ablation technique was explored to address these limitations. Experimental results demonstrated that a scanning speed of 1200 mm/s, coupled with a line spacing of 1 µm and a single ablation pass, resulted in complete coating removal while ensuring the integrity of the platinum substrate. The incorporation of a water layer above the ablation region was considered crucial for effective heat dissipation, preventing substrate overheating and ensuring uniform ablation. The laser’s spot diameter of 20 µm in air and a focal length of 130 mm introduced challenges related to overlap control between successive passes, requiring precise calibration to maintain consistency in coating removal. This research demonstrates the feasibility and reliability of water-assisted laser ablation as a method for a high-precision, non-contact coating material. Full article

This paper introduces a high-efficiency buck converter designed for a wide load range, targeting low-power applications in medical devices, smart homes, wearables, IoT, and technology utilizing WiFi and Bluetooth. To achieve high efficiency across varying loads, the proposed converter employs a low-power adaptive on-time (AOT) controller that ensures output voltage stability and seamless mode transitions. An adaptive comparator (ACP) with variable output impedance is introduced, offering a variable DC gain and bandwidth to be suitable for different load conditions. A negative-level shifter (NLS) circuit, with its swing ranging from −0.5 V to the battery voltage (V_BAT), is proposed to control the smaller power p-MOS transistors. By using an NLS, the chip area, which is mostly occupied by power CMOS transistors, is reduced while the power efficiency is improved, particularly under a heavy load. A status time detector (STD) block which provides control signals to the ACP and NLS for optimized power consumption is added to identify load conditions (heavy, light, ultra-light). By employing a 180 nm CMOS technology, the active chip area occupies about 0.31 mm². With an input voltage range of 2.8–3.3 V, the controller’s current consumption ranges from 1.2 μA to 16 μA, corresponding to the output load current varying from 12 μA to 120 mA. Although the output load can vary, the output voltage is regulated at 1.2 V with a ripple between 3 and 12 mV. The proposed design achieves a peak efficiency of 96.2% under a heavy load with a switching frequency of 1.3 MHz. Full article

This work demonstrates an ultra-compact optical gas-sensing system, consisting of a pigtailed laser diode emitting at 1392.5 nm for water vapor (H₂O) detection, a silicon nitride (Si₃N₄) optical waveguide to guide the laser light, and a custom-designed, low-frequency, and T-shaped Quartz Tuning Fork (QTF) as the sensitive element. The system employs both Quartz-Enhanced Photoacoustic Spectroscopy (QEPAS) and Light-Induced Thermoelastic Spectroscopy (LITES) techniques for trace gas sensing. A 3.8 mm-wide, S-shaped waveguide path was designed to prevent scattered laser light from directly illuminating the QTF. Both QEPAS and LITES demonstrated comparably low signal-to-noise ratios (SNRs), ranging from 1.6 to 3.2 for a 1.6% indoor H₂O concentration, primarily owing to the reduced optical power (~300 μW) delivered to the QTF excitation point. These results demonstrate the feasibility of integrating photonic devices and piezoelectric components into portable gas-sensing systems for challenging environments. Full article

This study addresses the challenges of high-power consumption and complexity in conventional infrared (IR) gas sensors by integrating metamaterials and gold coatings into IR radiation sources to reduce radiation loss. In addition, emitter design optimization and material selection were employed to minimize conduction loss. Our metasurface exhibited superior performance, achieving a narrower full width at half maximum at 4197 and 3950 nm, resulting in more confined emission spectral ranges. This focused emission reduced energy waste at unnecessary wavelengths, improving efficiency compared to traditional blackbody emitters. At 300 °C, the device consumed only 6.8 mW, while maintaining temperature uniformity and a fast response time. This enhancement is promising for the operation of such sensors in IoT networks with ultra-low power consumption and at suitably low costs for widespread demands in high-technology farming. Full article

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies. Full article

The global allocation of over 5 GHz of spectral bandwidth around the 60 GHz frequency band offers significant potential for ultra-high data rate wireless communication over short distances and enables the implementation of high-resolution frequency-modulated continuous-wave (FMCW) radar applications. In this study, a Front-End Receiver covering frequencies from 57 to 64 GHz was designed and characterized in a 40 nm CMOS process. The proposed architecture includes a Low-Noise Amplifier (LNA), a novel double-balanced mixer offering variable conversion gain, and a low-power class-C Voltage-Controlled Oscillator (VCO). From post-layout simulation results, the LNA presents a noise figure (NF) less than 4.8 dB and a gain more than 19 dB, while the input compression point (P1dB) reaches −15.6 dBm. The double-balanced mixer delivers a noise figure of less than 11 dB, a conversion gain of 14 dB, and an input-referred compression point of −13 dBm. The VCO achieves a phase noise of approximately −93 dBc/Hz at 1 MHz offset from 60 GHz and a tuning range of about 8 GHz, dissipating only 6.6 mW. Overall, the receiver demonstrates a maximum conversion gain of more than 39 dB, a noise figure of less than 9.2 dB, an input- referred compression point of −37 dBm, and a power dissipation of 56 mW. Full article

Energy-efficient integrated circuits require scaled-down supply voltages, posing challenges for analog design, particularly for operational transconductance amplifiers (OTAs) essential in high-accuracy CMOS feedback systems. Below 1 V, gate-driven OTAs are limited in common-mode input range and minimum supply voltage. This work investigates CMOS Bulk-Driven (BD) sub-threshold techniques as an efficient alternative for ultra-low voltage (ULV) and ultra-low power (ULP) designs. Although BD overcomes MOS threshold voltage limitations, historical challenges like lower transconductance, latch-up, and layout complexity hindered its use. Recent advancements in CMOS processes and the need for ULP solutions have revived industrial interest in BD. Through theoretical analysis and computer simulations, we explore BD topologies for ULP OTA input stages, classifying them as tailed/tail-less and class A/AB, evaluating their effectiveness for robust analog design, while offering valuable insights for circuit designers. Full article

This article introduces a high-efficiency, high-voltage-ratio bidirectional DC–DC converter based on the Dual-Active-Bridge (DAB) topology, specifically designed for applications involving low-voltage, high-capacity cells. Addressing the critical challenge of enhancing bidirectional power transfer efficiency under ultra-high step-up ratios, which is essential for integrating renewable energy sources and battery storage systems into modern power grids, an optimized control strategy is proposed. This strategy focuses on refining switching patterns and minimizing conduction losses to improve overall system efficiency. Theoretical analysis revealed significant enhancements in efficiency across various operating conditions. Simulation results further confirmed that the converter achieved exceptional performance in terms of efficiency at extremely high voltage conversion ratios, showcasing full-range Zero-Voltage Switching (ZVS) capabilities and reduced circulating reactive power. Specifically, the proposed method reduced circulating reactive power by up to 22.4% compared to conventional fixed-frequency control strategies, while achieving over 35% overload capability. These advancements reinforce the role of DAB as a key topology for next-generation high-performance power conversion systems, facilitating more efficient integration of renewable energy and energy storage solutions, and thereby contributing to the stability and sustainability of contemporary energy systems. Full article