Search Results (257)

This paper presents a multi-stage waveform generator based on second-generation Voltage Conveyors (VCIIs). The proposed architecture enables the generation of multiple waveform types, including a sinusoid, a square wave, a triangular wave, and a reconstructed quasi-sinusoidal waveform. The system is designed using cascaded VCII-based blocks, where each stage performs a specific signal-processing function. A theoretical analysis including non-ideal effects is carried out by considering the parasitic impedances at the conveyor terminals and highlighting their impact on the frequency response and signal amplitude. The proposed architecture is validated through measurements performed with a discrete AD844-based VCII realization and through transistor-level simulations of a 0.15 μm CMOS integrated implementation. The CMOS solution includes the layout design of the VCII building block, which occupies an active area of 40 μm × 40 μm. Simulation results confirm correct operation of the CMOS implementation at distinct frequency-scaled design points between 80 kHz and 30 MHz, while the discrete AD844-based realization is validated up to 1 MHz. The obtained results also indicate an intrinsic waveform shaping mechanism, where the comparator and cascaded integration stages contribute to improving the spectral purity of the reconstructed quasi-sinusoidal output. Robustness is further verified through Total Harmonic Distortion (THD), Process-Voltage-Temperature (PVT), and Monte Carlo analyses, which show limited variability and stable performance, with a maximum THD reduction of 21.7%. At 80 kHz, the square-wave duty cycle exhibits a mean value of 50.08% and a standard deviation of 0.42% over 200 Monte Carlo runs. Full article

Back-end-of-line-compatible oxide-semiconductor field-effect transistors (OSFETs) enable vertically stackable two-transistor zero-capacitor (2T0C) dynamic random-access memory (DRAM) cells, offering high densities while maintaining low write energy. The capacitorless 2T0C cell intrinsically benefits from decoupled read/write paths and a sub-fF storage-node (SN) capacitance $C_{\mathrm{SN}}$, reducing the stored charge to the sub-fC level. However, the control-line energy overhead introduced by the independent write word-line (WWL) activation can erode this advantage. The minimum write energy is ultimately bounded not by $C_{\mathrm{SN}}$ alone but also by the drive capability and leakage of the write transistor ${\mathrm{T}}_{\mathrm{W}}$ and the WWL and write bit-line (WBL) voltage configuration. A systematic co-optimization methodology addressing these coupled constraints has yet to be established. This work is built on the insight that the write-optimization target should be the stored-charge margin $\Delta Q_{\mathrm{SN}}$ rather than the storage-node voltage $V_{\mathrm{SN}}$ because $\Delta Q_{\mathrm{SN}}$ remains nearly constant across all phases and directly governs readout distinguishability. The methodology combines a coupled analysis of threshold voltage ($V_{\mathrm{th}}$), SS, and ${\mu }_{\mathrm{FE}}$ of ${\mathrm{T}}_{\mathrm{W}}$ with the adoption of $\Delta Q_{\mathrm{SN}}$ as the read-margin metric. On this basis, the write-overdrive margin, the WBL voltage, and $V_{\mathrm{th}}$ of ${\mathrm{T}}_{\mathrm{W}}$ are sequentially optimized. The three-step procedure reduces $\Delta V_{\mathrm{WWL}}$ from 3.0 V to 2.10 V while satisfying the 2 ns design-level write-time constraint, the 0.54 fC read-margin criterion, and the 1 ks retention benchmark. Under the assumptions of the present case study, the optimized 2T0C array yields a 2.5× reduction in array-level write-related energy relative to the unoptimized baseline and a 3.0× reduction relative to the LPDDR6 1T1C array reference. Full article

To address the challenge that microelectromechanical system (MEMS) gyroscope electrostatic force-modulated closed-loop self-excited driving circuits experience significant dynamic variations in capacitive load and driving demand under different operating conditions, such as start-up, steady-state resonance maintenance, and environmental perturbations, making it difficult to simultaneously achieve strong driving capability, stable oscillation, and low power consumption, this paper proposes a high-energy-efficiency adaptive output operational amplifier architecture. Based on a dynamic load-sensing mechanism, the design introduces a three-threshold decision scheme combining a high threshold, a low threshold, and a mid-supply reference voltage. By coordinating a continuous-time voltage detection circuit with a bidirectional shift register, the proposed approach enables accurate identification of the output state and the load level. A time-division-multiplexed two-stage control strategy is adopted to rapidly compensate for the drive capability under abrupt load changes, while proactively disabling redundant output units under steady-state conditions, thereby achieving power delivery on demand. The output stage employs a Class-AB push–pull structure integrating an improved low-leakage single-pole double-throw (SPDT) switch, which hard shuts off the power transistors in the non-operating state to effectively eliminate the subthreshold leakage current. Circuit simulations in a 0.18 μm CMOS process demonstrate that the proposed operational amplifier can adaptively regulate its output current in real time according to variations in the gyroscope driving demand, ensuring sufficient an electrostatic driving force and oscillation stability during transient conditions while significantly reducing static power consumption during the resonance steady state. The proposed design provides an effective solution for high-performance and high-energy-efficiency interface circuit design in MEMS gyroscope electrostatic force-modulated closed-loop self-excited driving systems. Full article

In this study, we systematically decoupled reversible charge transitions via recombination and irreversible bulk trapping via ionization in solution-processed indium zinc oxide thin-film transistors (TFTs) under positive- and negative-bias-stress (PBS and NBS) conditions. We defined highly decoupled degradation behavior by completely evaluating time-dependent transfer characteristics and saturation leakage currents across a range of indium molarities (0.0125 M to 0.2 M). Results indicate that PBS-induced instability is likely governed by a reversible electrostatic neutralization process reducing total effective shallow and deep acceptor-like states, which are dynamically counteracted by interfacial recombination at the dielectric/semiconductor boundary. Conversely, severe degradation under NBS originated from irreversible bulk trapping triggered by the ionization of donor-like oxygen vacancies in a ZnO amorphous random network. Total effective trapped charges were calculated from threshold voltage shifts to clarify these defect kinetics quantitatively; these calculations demonstrated direct correlation with the integrated theoretical capacities of the deep and shallow acceptor-like gap-state distributions. Finally, we propose a comprehensive density of state–energy band alignment model incorporating thermal activation energies and flat-band voltages. This analytical framework proves that the composition-dependent Fermi level positioning rigorously limits and dictates complex bias-stress instabilities, offering profound insights for designing highly stable amorphous oxide semiconductor TFTs. Full article

The continued scaling of semiconductor devices at advanced technology nodes introduces significant challenges in maintaining performance, reliability, and design efficiency. This work presents a data-driven framework for the modeling and optimization of nanosheet (NS) and forksheet (FS) transistors using deep learning and Bayesian optimization. An extensive dataset is generated through LTSpice-based circuit simulations, enabling efficient exploration of the design space while incorporating key device parameters, including channel length, channel width, supply voltage, temperature, and threshold voltage, together with variability and noise effects. A deep neural network (DNN) is developed as a surrogate model to learn the nonlinear relationship between input parameters and transistor switching behavior, achieving strong predictive performance with a coefficient of determination ($R^2\approx 0.91$), mean absolute error (MAE $\approx 0.024$), and root mean square error (RMSE $\approx 0.031$) on unseen test data. To improve physical consistency, a bounded-output formulation is introduced to guarantee physically admissible voltage predictions, while device-level benchmarking is performed to assess agreement with expected transistor characteristics. The results demonstrate accurate modeling of transient behavior across the sampled operating conditions. Comparative analysis shows that NS devices achieve faster switching and lower propagation delay, whereas FS devices exhibit improved stability under certain conditions. Bayesian optimization is employed to efficiently explore the design space and identify high-performing transistor configurations without exhaustive simulation-based searches. The proposed framework provides a scalable and computationally efficient methodology for surrogate modeling, design-space exploration, and early-stage assessment of advanced transistor architectures. Full article

This study systematically investigates the intrinsic vertical breakdown characteristics of 8-inch GaN-on-Si high-electron-mobility transistor (HEMT) buffer layers (extending up to the GaN channel layer) using a vertical electrode configuration. By comparing samples with different carbon doping doses, AlN insertion layers, and superlattice cycle numbers (buffer layer thickness), combined with Technology Computer-Aided Design (TCAD) simulations, the relevant mechanisms are revealed. The results show that buffer layer thickness is a critical factor determining the vertical breakdown voltage. Its increase effectively reduces the longitudinal average electric field, widens the depletion region, and increases the breakdown voltage by approximately 50%. Carbon doping compensates for carriers and suppresses leakage through deep-level acceptor traps. Inserting thin AlN layers into the superlattice has a limited effect on improving breakdown voltage. This research provides clear experimental guidance for the optimal design of high-voltage GaN HEMT buffer layers from both material and physical perspectives. Full article

Power amplifiers are one of the most important microwave components and key equipment in satellite transponder subsystems. It plays a significant role in enhancing the overall capabilities of satellite systems, optimizing thermal design, and ensuring reliability. The rapid development of High Throughput Satellites (HTS) and global mobile communication satellites imposes challenges to power amplifier design. This paper presents a dual-band Doherty power amplifier (DPA) with a hybrid GaN HEMT device and a commercial transistor that can operate simultaneously at 0.9 GHz and 2.14 GHz. At 6 dB output power back-off (OBO), the proposed amplifier achieves drain efficiencies of 42% and 37% at the two frequency bands respectively. When excited by a 20 MHz 16 QAM signal, it exhibits adjacent channel power ratios (ACPR) of −45.4 dBc and −48.6 dBc at output power levels of 34.8 dBm and 34.9 dBm respectively. A novel dual-band offset line structure was employed to achieve the required dual-band load modulation. The proposed DPA is well-suited for application in dual-band wireless communication systems. Full article

This paper presents a behavioral-level, pre-silicon analytical co-design framework for memristor read–write interfaces, intended to establish closed-form design rules that subsequently guide SPICE-level and silicon-level realizations. Memristor-based neural hardware requires interfaces that can program resistance states efficiently while suppressing read disturbance, yet existing designs typically rely on empirical tuning without closed-form analytical rules. We close this gap by deriving a single closed-form operating-window inequality $(v_{\mathrm{on}}<V_{\mathrm{rd}}<v_{\mathrm{off}},V_{\mathrm{wr}}\ge V_{\mathrm{wr}}^{min}\left(T_{\mathrm{wr}}\right))$ from the VTEAM state equation, embedding it in an Energy–Delay–Accuracy (EDA) cost function, and validating the resulting parameter set hierarchically up to MNIST-scale inference. The main finding is that this analytically derived parameter set simultaneously achieves a 96.08% set-cycle energy saving and 90.6% MNIST top-1 accuracy (1.2% below software baseline) under realistic D2D/C2C variability, with every measured number agreeing with its analytical prediction within 2%. The framework is instantiated with a two-phase over-threshold-write and sub-threshold-read timing strategy together with a mutually exclusive PMOS-NMOS path-isolation topology, evaluated through behavioral-level MATLAB simulation under linear-drift and VTEAM models. Behavioral simulation confirms each analytical bound within 2%: a 13.78× resistance window with $\le 0.008\%$ cycle-to-cycle drift, 5.01% read-current CV, and 30.94%/96.08% Reset/Set energy savings versus a no-separation baseline. Transistor-level non-idealities (slew rate, charge injection, RTN, retention aging, peripheral overhead) are bounded analytically; full SPICE/silicon validation is identified as immediate follow-up work. These results establish a reusable, analytically grounded reference design that bridges memristive device modeling, circuit-level interface implementation, and neural network-level usability. Full article

The increase in small satellites demands the integration of commercial components to reduce costs and development time. However, the lack of standardized system-level methodologies to mitigate radiation-induced degradation limits their adoption. Although majority-carrier technologies such as MOSFET transistors dominate space power electronics, modern commercial off-the-shelf BJT transistors present a robust and cost-effective alternative. This paper evaluates the viability of the new-generation commercial off-the-shelf BJT transistors in space radiation environments by analyzing their response to total ionizing dose (measured at the circuit level) and single-event effects (inferred from component-level data). A fault-tolerant design methodology is proposed based on the strict definition of the safe operating area: the collector-emitter voltage is limited to safe values to mitigate single-event burnout, and an overdrive margin, specifically a 5× worst-case factor, is applied to compensate for the parametric degradation of the current gain. These strategies are empirically validated through two circuits: a voltage clamp and a proportional base driver operating in the 5 W to 40 W range. Experimental tests on the voltage clamp demonstrate stable operation up to one hundred kilorads, exceeding the 50 krad mission requirement by 100%. This indirectly supports the proportional base driver through shared mitigation principles, which rely on base current over-dimensioning to compensate for TID degradation. In conclusion, by applying appropriate derating rules, commercial off-the-shelf BJT transistors constitute a viable and robust alternative for small satellite power systems, mitigating the need for expensive radiation-hardened components. Full article

Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore’s Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels. In this work, we overcome this long-standing bottleneck by introducing a co-design strategy that integrates a small-diameter HiPco CNT channel with a novel asymmetric gate architecture. This approach strategically reshapes the channel electrostatics to simultaneously suppress the gate-induced drain leakage (GIDL) effect and preserve excellent carrier transport. The efficacy of this strategy is rigorously validated through calibrated technology computer-aided design (TCAD) simulations for both NMOS and PMOS operation, demonstrating an ultralow off-current of 10 fA/µm, an on-current of 1.08 mA/µm, and a record on–off ratio of 1.1 × 10¹¹ for back-gated CNTFETs at the 90 nm node. The design exhibits outstanding scalability: at the scaled 28 nm node with a supply voltage of 0.7 V, the PMOS device achieves 3 mA/µm on-current and 6 pA/µm off-current, maintaining an on–off ratio of 5 × 10⁸. This work establishes a scalable pathway toward femtoampere-level CNT CMOS, addressing the static power challenge in future nano-electronics. Full article

With the rapid advancement of digital integrated circuits, transistor sizes and integration levels have grown at an unprecedented rate, leading to increasingly complex design processes. A key challenge in digital layout design is the placement and routing of standard cell circuit layouts, which directly impact chip quality and performance. Power is a critical factor in evaluating standard cells. To enable low-power standard cell layouts, the depth-first search (DFS) algorithm is proposed to model and place the standard cell. Additionally, the study aims to satisfy Design Rule Checking (DRC), a grid routing strategy based on the deep reinforcement learning (DRL) algorithm, which quickly identifies cell boundaries and barriers such as existing nets as well as contacts, while optimizing metal routing to achieve minimal power. Results show that the standard cell layouts generated by the DRL-based model achieve over a 90% reduction in design time and approximately 5% improvements in power compared with manual layouts. The proposed method facilitates the rapid development of standard cell library and has important engineering value. Full article

The accelerating adoption of electric vehicles (EVs) is driving the demand for next-generation wide-bandgap (WBG) power devices that can deliver high efficiency, high power density, and robust operation under stringent electrical and thermal stress. Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have emerged as a leading WBG technology due to their high breakdown voltage, ultrafast switching capability, and low conduction and switching losses relative to silicon devices, enabling high-performance EV power converters such as on-board chargers, DC-DC converters, and traction inverters. This review provides a comprehensive device-level assessment of GaN HEMTs, emphasizing advanced device architectures, state-of-the-art discrete transistors, and their implications for high-frequency, high-efficiency power conversion. Critical performance and reliability challenges, including current collapse, self-heating, and gate degradation, are analyzed in the context of their physical mechanisms and operational behavior under realistic conditions such as elevated junction temperatures, high switching frequencies, and dynamic load profiles. Furthermore, emerging opportunities in ultra-wide-bandgap semiconductor technologies beyond GaN are discussed, providing insights to guide the design, optimization, and robust integration of WBG devices into next-generation EV power electronic systems. Full article

As deep learning-based Anomaly Detection (AD) transitions from theoretical research to industrial application, the focus is shifting towards operational efficiency and economic viability on edge devices. While recent studies have achieved remarkable detection accuracy on standard benchmarks, they often rely on heavy memory banks or complex backbones, which pose challenges for deployment in resource-constrained manufacturing environments. Furthermore, real-world inspection lines often present distinct challenges—such as environmental noise and strict latency requirements—that are not fully addressed by accuracy-centric metrics. To bridge the gap between high-performance research models and practical edge deployment, we introduce WEDGE-Net. Our approach is designed to balance structural precision with extreme memory efficiency. We decouple anomaly detection into two specialized streams: (1) a Frequency Stream (DWT) that physically filters out environmental noise to isolate structural defects, and (2) a Context Stream where a Semantic Module explicitly guides feature extraction to enforce object consistency. By synthesizing these two modalities, WEDGE-Net effectively suppresses high-frequency noise while enhancing structural-feature compactness. To validate operational stability, we conducted a robustness analysis of the ‘Tile’ category, which poses a challenging task for distinguishing defects from high-frequency textures. In this stress test, WEDGE-Net demonstrated superior resistance to environmental noise compared to conventional methods. Experimental results on the MVTec AD dataset demonstrate that WEDGE-Net achieves a mean image-level AUROC of 97.82% and an inference speed of 686.5 FPS (measured on an RTX 4090 GPU) under an extreme 1% memory-compression setting. Notably, our method demonstrates superior efficiency, achieving a 2.1× inference speedup over the widely adopted comparative model (PatchCore-10%) while maintaining competitive detection accuracy (e.g., 100% AUROC on Transistor). We hope this work serves as a practical reference for implementing real-time industrial inspection on resource-constrained edge devices. Full article

As emerging nonvolatile memory devices, ferroelectric field-effect transistors (FeFETs) have attracted significant attention for memory applications. However, due to the stochastic nature of fabrication processes and material properties, FeFETs exhibit pronounced device-to-device (DTD) variations, leading to threshold voltage dispersion and inconsistency in memory window (MW), which severely constrain array-level performance and reliability. In this study, a compact model-based variability analysis methodology for FeFETs has been proposed. Specifically, the Preisach ferroelectric (FE) hysteresis model was combined with the MIT Virtual Source (MVS) physical compact model to establish a macro-model for FeFETs, and statistical simulations were performed to evaluate device-level variations. Using the proposed framework, how fluctuations in two key FE parameters, film thickness (t_FE) and coercive field (E_C), affect FeFET transfer characteristics, threshold voltage (V_TH), and MW was systematically investigated. Monte Carlo (MC) simulations were further conducted to quantify the distribution width and statistical features of V_TH under different variability scenarios. The results indicate that random fluctuations in process-related parameters broaden the FeFET I_d-V_g characteristics, induce shifts in high/low threshold voltages, and cause MW variations. Moreover, when t_FE and E_C fluctuate simultaneously, the dispersions of V_TH and MW become significantly larger than those induced by a single-parameter fluctuation. The proposed compact-modeling framework and variability analysis approach enables the efficient evaluation of parameter tolerance and performance margin in FeFET arrays, providing guidance for storage-array design. Full article

While sustainability is set as a goal by a broad range of international organizations, its definition varies, and there is still a lack of practical criteria for product designers to evaluate the degree of (un)sustainability in the design phase. Life cycle assessment (LCA) can allow quantification of the environmental impacts of a product but is often carried out post-design, when the manufacturing process is already settled. Finally, while significant advances have been made towards standardizing LCA calculations by providing product category rules, large uncertainties remain in the calculation results due to a lack of transparency regarding the choices of databases, system boundaries, allocation, cut-off rules, and level of data granularity. A practical way to improve in those areas is to share with the semiconductor community a parametrizable life cycle inventory (LCI) model based on a target device to (1) identify knowledge gaps in LCA methods for such products, (2) identify the main process variables, and (3) provide a starting point for LCA calculations by the designers themselves. With this aim, a parametrizable cradle-to-gate manufacturing LCI model was developed based on the peer-reviewed process flow of a trench field-stop silicon insulated gate bipolar transistor (IGBT) semiconductor power device. The model allows computation of the environmental impacts of the IGBT manufacturing process based on different tunable parameters such as die size, wafer diameter, manufacturing yield, abatement efficiency, wafer fab throughput, wafer fab location, and associated electricity mix. Embedding a high level of data granularity, it helps identify, at elementary process levels, key environmental hotspots and associated technical levers for their reduction. Analysis of the IGBT manufacturing process tends to demonstrate the importance of an impact assessment approach considering multiple environmental categories, going beyond the sole focus on greenhouse gas emissions and accounting for potential transfers of impact. With an open-source mindset and in a continuous improvement prospective, the manufacturing inventory model and its associated tools are freely available from a public GitHub repository and open for comments and consolidation from users. Full article