Search Results (54)

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits. Full article

In this paper, a high-voltage chopper and ping-pong auto-zeroing operational amplifier was designed for industrial and automotive applications. Based on chopper stabilization, the proposed circuit introduces a novel chopper switch control signal that varies with the input common-mode voltage. This scheme effectively suppresses the reference offset caused by the chopper switches and prevents transistor breakdown under high-voltage conditions. Additionally, the ping-pong auto-zero structure was optimized by employing a six-channel parallel first-stage amplifier, which further reduced the charge injection and ripple introduced by the chopper switches. The amplifier was implemented using an SMIC (Semiconductor Manufacturing International Corporation) 180 nm 1P5M BCD (Bipolar-CMOS-DMOS) process with a chip area of 4.211 mm². The post-layout simulation results show that, under a 55 V supply, the amplifier achieves an input-referred noise Power Spectral Density (PSD) of 6.2 $\mathrm{nV}/\sqrt{\mathrm{Hz}}$ and an input offset voltage of 32 $\mu \mathrm{V}$, while the output voltage swings from 0.2 V to 53.4 V with a unity gain bandwidth of 3.2 MHz, which meets the requirements for high-voltage, high-resolution signal processing. Full article

To expand the operating frequency bands of the Doherty power amplifier (DPA), this paper proposes a dual-mode multi-band DPA design method employing impedance-and-phase constrained optimization based on reciprocal gate bias. By introducing the concept of reciprocal gate bias, the operating mode is switched by swapping the gate biases of the carrier and peaking amplifiers of the DPA, which effectively extend the operating frequency band without modifying the load modulation network. Furthermore, multiple impedance constraint circles are used to cover the optimum load impedance region obtained from the load-pull simulation. And, the phases required for impedance transformation network (ITN) across the multi-band are determined based on the impedance transformation requirements when the DPA operates in power back-off (PBO) state and saturation state. Then, the ITNs that satisfy the impedance and phase constraints can be optimized and designed. For verification, a dual-mode multi-band DPA, operating in Mode I at 1.96–2.10 GHz and 2.75–2.86 GHz, and in Mode II at 2.49–2.61 GHz and 3.20–3.36 GHz, is designed and fabricated. Measured results show that the output power of the DPA exceeds 43 dBm with corresponding saturated drain efficiencies (DEs) higher than 50% in both modes. For 6 dB PBO, the DEs are 49.4–55.7% and 49.8–51.7% in Mode I, whereas in Mode II, they range from 51.2% to 52.4% and from 50.4% to 53.5%. Moreover, good linearity can be achieved after linearization for 20 MHz modulated signals. Full article

This paper presents a high-power heterojunction bipolar transistor (HBT) power amplifier (PA) module designed for GSM/EDGE applications. The proposed HBT PA employs a differential output stage that delivers high output power at a low supply voltage. A transformer-based output matching network is employed to combine the differential output signals. Through the selection of an appropriate capacitor value at the transformer’s center tap, linearity is enhanced across a wide bandwidth without requiring additional second harmonic termination. When assembled with a low-pass filter and an antenna switch, the PA module achieves an output power of 36 dBm and a power-added efficiency (PAE) exceeding 40% in GSM mode. In EDGE mode, it delivers an output power of 28.5 dBm with a PAE exceeding 20%. Additionally, the designed PA module achieves an adjacent channel power ratio of −60 dBc at a 400 kHz offset with an output power of 28.5 dBm. Full article

This paper proposes a three-stage op amp based on the SOI (silicon-on-insulator) process, which achieves a low offset voltage and temperature coefficient across a wide temperature range from −40 °C to 250 °C. It can be used in aerospace, oil and gas exploration, automotive electronics, nuclear industry, and in other fields where the ability of electronic devices to withstand high-temperature environments is strongly required. By utilizing a SC (Switched Capacitor) notch filter, the op amp achieves low input offset in a power-efficient manner. The circuit features a multi-path nested Miller compensation structure, consisting of a low-speed channel and a high-speed channel, which switch according to the input signal frequency. The input-stage operational amplifier is a fully differential, rail-to-rail design, utilizing tail current control to reduce the impact of common-mode voltage on the transconductance of the input stage. The two-stage operational amplifier uses both cascode and Miller compensation, minimizing the influence of the feedforward signal path and improving the amplifier’s response speed. The prototype op amp is fabricated in a 0.15 µm SOI process and draws 0.3 mA from a 5 V supply. The circuit occupies a chip area of 0.76 mm². The measured open-loop gain exceeds 140 dB, with a 3 dB bandwidth greater than 100 kHz. The amplifier demonstrates stable performance across a wide temperature range from −40 °C to 250 °C, and exhibits an excellent input offset of approximately 20 µV at room temperature and an offset voltage temperature coefficient of 0.7 μV/°C in the full temperature range. Full article

This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm² on the chip, with a power consumption of 8.96 μW. Full article

This paper presents a single-input multiple-output (SIMO) cascode low-noise amplifier with inductive degeneration for inter- and intra-band carrier aggregation. The proposed low-noise amplifier has two output ports for flexible operation in carrier aggregation combinations for band 30 and band 7. However, during inter- and intra-band operation, gain variation occurs depending on the output mode. To compensate for this, a switching circuit is proposed to adjust the degeneration inductor, optimizing gain performance for both modes. The switching operation can minimize the control for the dynamic range in the receiver system to support carrier aggregation. The designed low-noise amplifier was fabricated using a 65 nm CMOS process, occupying an area of 2.1 mm². In inter-band operation, the small-signal gain was measured by 18.9 dB for band 30 and 18.6 dB for band 7, with the noise figures of 1.03 dB and 1.07 dB, respectively. For intra-band operation, the small-signal gain was 17.3 dB and 17.2 dB, with the noise figures of 1.3 dB and 1.41 dB. The IIP₃ values were measured by −7.6 dBm and −6.7 dBm for inter-band, and −6.3 dBm and −6.2 dBm for intra-band. Power consumption was 8.04 mW and 7.68 mW in inter-band, and 17.04 mW and 17.64 mW in intra-band depending on the output configuration. Full article

This paper presents an inverter-based active feedback transimpedance amplifier (IAF-TIA), in which an active feedback is applied to a voltage-mode inverter-based TIA, and therefore, the controlled positive regeneration process enables the proposed IAF-TIA to achieve the limiting operations for input currents greater than 100 μA_pp. However, the active inverter feedback mechanism might be prone to instability, hence mandating a very careful optimization of the loop gain. For this purpose, a diode-connected NMOS transistor is employed as a switch in the feedback path with its gate connected to the input, which helps not only to mitigate the corresponding issue but also to accommodate large input currents up to 1.5 mA_pp. The proposed IAF-TIA implemented in a standard 180 nm CMOS process demonstrates a 70.5 dBΩ transimpedance gain, 1.21 GHz bandwidth, 4.3$\mathrm{pA}/\sqrt{\mathrm{Hz}}$ noise current spectral density, 63.5 dB input dynamic range, and 23.6 mW power dissipation from a single 1.8 V supply. The chip core occupies an area of 180 × 50 μm², including an on-chip P⁺/N-well/Deep N-well avalanche photodiode as an optical detector. Full article

This paper presents a highly efficient 5G New-Radio (NR) RF power amplifier module (PAM). The n77 PAM consists of a high-voltage differential-topology 2 μm GaAs HBT power amplifier, a CMOS controller, a silicon-on-insulator (SOI) switch, an integrated passive device (IPD) bandpass filter, a low-noise amplifier (LNA), and a bi-directional coupler. This PAM generates a saturation output power of 32.7 dBm including the loss of the SOI switch and output filter. The designed n77 PAM is tested with a commercial envelope tracker IC (ET-IC). The designed PAM with an ET-IC achieves an ACLR of −37 dBc at a 27 dBm output power with a DFT-s-OFDM QPSK 100 MHz NR signal and saves a dc power consumption of 950 mW compared to the APT mode. For the CP-OFDM 256QAM with the most stringent EVM requirements, it achieves an EVM of 1.22% at 23 dBm and saves 640 mW compared to the APT mode. Full article

This paper presents a highly integrated C-band RF transceiver front-end design consisting of two Single Pole Double Throw (SPDT) transmit/receive (T/R) switches, a Low Noise Amplifier (LNA), and a Power Amplifier (PA) for Ultra-Wideband (UWB) positioning system applications. When fabricated using a 0.25 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process, the switch is optimized for system isolation and stability using inductive resonance techniques. The transceiver front-end achieves overall bandwidth expansion as well as the flat noise in receive mode using the bandwidth expansion technique. The results show that the front-end modules (FEM) have a typical gain of 22 dB in transmit mode, 18 dB in receive mode, and 2 dB noise in the 4.5–8 GHz band, with a chip area of 1.56 × 1.46 mm². Based on the available literature, it is known that the proposed circuit is the most highly integrated C-band RF transceiver front-end design for UWB applications in the same process. Full article

The main characteristics of high-efficiency switching-mode solid-state power amplifiers with envelope elimination and restoration (EER) methods depend on all their elements. In this article, we study the influence of the types and parameters of the envelope path low-pass filters (LPFs) on the EER transmitter out-of-band emissions. This article presents for the first time an analysis of EER transmitter operation where the output impedance of the PWM modulator is not equal to zero, as usual (with a one-sided loaded LPF), but is matched with the low-pass filter and the load (with a double-sided loaded LPF). Theoretical comparisons of EER transmitters’ out-of-band emissions were carried out with four envelope path LPF configurations (one-sided and double-sided loaded LPFs with a smooth and sharp transition, respectively), for both the nominal load (broadband antenna) and resonant antennas with a limited bandwidth. The analysis showed that for the case of transmitter operation on a resonant antenna with a limited bandwidth, the preferable option was the use of a sixth-order double-sided loaded LPF with a smooth transition. The use of the proposed modulator configuration allowed the transmitter to operate on an antenna with VSWR = 1.07 at the edges of the transmitted signal band with a minimum LPF bandwidth equal to 5.8 bands of the amplified signal. This could significantly expand its application capabilities and allow one to reduce the PWM clock frequency and increase efficiency. Full article

In the realm of electric vehicles (EVs), achieving diverse direct current (DC) voltage levels is essential to meet varying electrical load demands. This requires meticulous control of the battery voltage, which must be adjusted in line with specific load characteristics. Therefore, the integration of a well-designed power converter circuit is crucial, as it plays a pivotal role in generating different DC voltage outputs. In this study, we also consider the incorporation of two additional doubler/divider circuits at the end of the proposed converter, further enhancing its capacity to produce distinct DC voltage levels, thus increasing its versatility. The standout feature of the proposed converter lies in its remarkable ability to amplify DC voltages significantly. For instance, when the input battery voltage is set at 48 VDC with a duty cycle (D) of 0.8, the resulting output demonstrates a remarkable augmentation, producing voltages 18, 36, and 72 times higher than the input voltage. Conversely, with a reduced D of 0.2 while maintaining the input voltage at 48 VDC, the converter yields diminished voltages of 0.1875, 0.375, and 0.75 times the initial voltage. This adaptability, based on the parameterization of D, underscores the converter’s ability to cater to a wide range of voltage requirements. To oversee the intricate operations of this versatile converter, a high-speed DSP-based controller system is employed. It utilizes the renowned PID approach, known for its proficiency in navigating complex, nonlinear systems. Experimental results validate the theoretical and simulation findings, reaffirming the converter’s practical utility in EV applications. The study introduces a simple control mechanism with a single power switch, high efficiency for high-power applications, wide voltage range, especially with VDC and VMC cells, and continuous current operation for the load in CCM mode. This study underscores the significance of advanced power conversion systems in shaping the future of electric transportation. Full article

This paper presents a triple-input and four-output type voltage-mode universal active filter based on three current-feedback operational amplifiers (CFOAs). The filter employs three CFOAs, two grounded capacitors, and six resistors. The filter structure has three high-input and three low-output impedances that simultaneously provide band-reject, high-pass, low-pass, and band-pass filtering functions with single-input and four-output type and also implements an all-pass filtering function by connecting three input signals to one input without the use of voltage inverters or switches. The same circuit configuration enables two unique filtering functions: low-pass notch and high-pass notch. Three CFOAs with three high-input and low-output impedance terminals enable cascading without voltage buffers. The circuit is implemented using three commercial off-the-shelf AD844 integrated circuits, two grounded capacitors, and six resistors and further implemented as a CFOA-based chip using three CFOAs, two grounded capacitors, and six resistors. The CFOA-based chip has lower power consumption and higher integration than the AD844-based filter. The circuit was simulated using OrCAD PSpice to verify the AD844-based filter and Synopsys HSpice for post-layout simulation of the CFOA-based chip. The theoretical analysis is validated and confirmed by measurements on an AD844-based filter and a CFOA-based chip. Full article

Space-based communications at the very high frequency (VHF) band for air traffic management is a new technology application under development that requires energy-efficient architectures to mitigate the power limitations of satellite platforms. The usage of high-efficiency radiofrequency (RF) transmitters can help reduce the power consumption, but nonlinearities concerning the amplified signal in wide fractional bandwidth systems are a problem to solve. This paper proposes a high-efficiency (RF) power amplifier (PA) for satellite communications at the VHF band that aims to reduce the envelope distortion inherent to wide fractional bandwidth multicarrier polar-mode transmitters. Its design is based on a solution called hybrid-coupled switching voltage PA in combination with gallium nitride (GaN) high electron mobility transistor (HEMT) technology. The developed VHF PA prototype delivers up to 95 W from a 28 V power supply, with a drain efficiency about 80% within the 118 MHz to 138 MHz operating band. To test its linearity performance, operating in a polar-mode configuration, a GaN-based wideband envelope amplifier (EA) has been developed to modulate the RF PA supply port. This EA improves its power efficiency by combining it with a slow envelope power supply (SEPS). Some measurements have been taken for a 100 W peak envelope power (PEP) and 10 MHz (maximum carrier spacing) four-tone digitally-modulated test signal, where any distortion product is attenuated 46 dB below the average power of the amplified signal without applying any digital predistortion (DPD) technique. Full article

The active sound navigation and ranging (SONAR) transmission system emits acoustic pulses underwater using a wave generator, a SONAR power amplifier (SPA), and a projector. The acoustic pulse travel in the direction of the target and return as an echo to a hydrophone to learn the range or speed of the object. Often the same device is used as a hydrophone and a projector; in this context, it is known as a transducer. In order to obtain a maximum range of detection in the SONAR, it is desirable to generate the maximum amount of acoustic power until the point in which the echo can be detectable in an atmosphere with non-wished noise. Therefore, a high value of source level (SL) is required that depends largely on the value of electrical power applied to the transducer ($P_e$). However, when trying to obtain the maximum range of detection in the SONAR system there are the following three peculiar limitations that affect performance: The cavitation, the reverberation, and the effect of interaction in the near field. In this paper, an experimental measurement methodology is presented to detect the cavitation effects in a tonpilz-type transducer for an active SONAR transmission system using a transducer as a projector and a calibrated hydrophone in a hydroacoustic tank by measuring the parameters of total harmonic distortion of the fundamental waveform (THD-F) of the generated acoustic pulse, transmitting voltage response (TVR) to characterize the system and sound pressure level (SPL) that indicates the intensity of sound at a given distance. Whereas the reverberation and the interaction effect in the near field are objects of other study cases. A 570.21 W and THD-F < $5\%$ switched-mode power amplifier (SMPA) prototype was developed to excite the electroacoustic transducer employing a full-bridge inverter (FBI) topology and a digital controller using a field-programmable gate array (FPGA) for unipolar sine pulse width modulation (SPWM) to generate a continuous wave (CW) acoustic pulse at a frequency 11.6 kHz. The results obtained show that from the level of $P_e=196.05$ W with the transducer at 1 $\mathrm{m}$ of depth, the value of THD-F increases significantly while the behavior of the TVR and SPL parameters is affected since it is not as expected and is attributed when cavitation occurs. Full article