A 55 V, Six-Channel Chopper and Auto-Zeroing Amplifier with 6.2 nV/$\sqrt{\mathbf{Hz}}$ Noise and −128 dB Total Harmonic Distortion

Abstract

In this paper, a high-voltage chopper and ping-pong auto-zeroing operational amplifier was designed for industrial and automotive applications. Based on chopper stabilization, the proposed circuit introduces a novel chopper switch control signal that varies with the input common-mode voltage. This scheme effectively suppresses the reference offset caused by the chopper switches and prevents transistor breakdown under high-voltage conditions. Additionally, the ping-pong auto-zero structure was optimized by employing a six-channel parallel first-stage amplifier, which further reduced the charge injection and ripple introduced by the chopper switches. The amplifier was implemented using an SMIC (Semiconductor Manufacturing International Corporation) 180 nm 1P5M BCD (Bipolar-CMOS-DMOS) process with a chip area of 4.211 mm². The post-layout simulation results show that, under a 55 V supply, the amplifier achieves an input-referred noise Power Spectral Density (PSD) of 6.2 $\mathrm{nV}/\sqrt{\mathrm{Hz}}$ and an input offset voltage of 32 $\mu \mathrm{V}$, while the output voltage swings from 0.2 V to 53.4 V with a unity gain bandwidth of 3.2 MHz, which meets the requirements for high-voltage, high-resolution signal processing.

1. Introduction

With the rapid evolution of integrated circuits, process nodes have progressively scaled from micrometer dimensions to advanced 7 nm and 3 nm nodes. In 2024, the Taiwan Semiconductor Manufacturing Company (TSMC) achieved a significant milestone by commencing the mass production of a 2 nm node, as reported in communications on recent industry developments. This relentless miniaturization has substantially increased the transistor density while reducing the power consumption, driving the demand for innovative low-voltage design methodologies [1]. Consequently, substantial progress has been made in developing low-voltage operational amplifiers, enabling enhanced performance in power-constrained applications. In contrast, the advancement of high-voltage operational amplifiers has lagged despite their critical role in emerging applications. Specifically, sensor analog front ends, medical instrumentation, and automotive electronics increasingly necessitate operational amplifiers capable of delivering a high closed-loop gain, minimal noise, and a low offset under elevated voltage conditions [2,3,4]. High-precision, fast-responding operational amplifiers are paramount to ensure accurate signal acquisition, thereby facilitating superior system-level control and reliability in these high-voltage environments.

Several techniques are widely adopted to achieve high accuracy, including digital trimming (DigiTrim), chopper stabilization, and auto-zeroing. Digital trimming, as can be performed using Analog Devices’ DigiTrim technology [5], adjusts the circuit performance using digitally programmed weighted current sources. Adjustment data are input via existing analog pins using specific digital keyword sequences. These values can be temporarily programmed, evaluated, and fine-tuned for optimal precision before permanent adjustment. Chopper stabilization [6], a frequency-domain technique, employs switch-based modulation to shift the input signal to the high-frequency domain, amplify it, and finally demodulate it back to its original frequency. Auto-zeroing, a time-domain error correction method, uses a capacitor to store the instantaneous error during a phase when the inputs are short-circuited, producing a constant output (e.g., zero) [7]. In the subsequent phase, the stored error is subtracted from the signal, enabling the output to track the input with constant level shifting.

Despite their advantages in achieving low noise and a low offset in high-voltage environments, these techniques have notable limitations. Digital trimming relies on blowing polysilicon fuses for permanent adjustments, rendering the process irreversible [8]. If the trimming parameters are later found to be suboptimal, redesign or reproduction is necessary, which increases the cost. In chopper amplifiers, charge injection and clock feedthrough from chopping switches introduce the glitching and modulated ripple of the original offset, manifesting at even and odd harmonics of the chopping frequency, respectively [9]. These artifacts often result in a residual output offset. Due to its signal-sampling nature, auto-zeroing increases the noise power spectral density within the sampling frequency range. This increase stems partly from the folding of 1/f noise tails and partly from the aliasing of broadband thermal noise. It will cause the input-referred noise power spectral density (PSD) to exceed the original thermal noise PSD within twice the Nyquist frequency [10]. Combining auto-zeroing and chopper techniques can enhance the operational amplifier noise and offset performance [11].

Most precision operational amplifiers leverage chopping and auto-zeroing to achieve low noise and offsets. Dension et al. introduced a micropower chopper-stabilized amplifier. It achieved a noise floor of 0.98 V_rms over a bandwidth of 0.05 to 100 Hz [12]. Another study proposed a chopper DC Servo Loop (DSL) utilizing an active Gm-C integrator to mitigate the electrode DC offset, with a power consumption of 3.24 $\mu \mathrm{W}$ per channel at a 1.8 V supply voltage and an input equivalent noise PSD of 39 $\mathrm{n}\mathrm{V}\mathrm{/}\sqrt{\mathrm{H}\mathrm{z}}$ [13]. Bakker et al. presented a nested chopper technique that significantly reduces the offset in traditional chopper amplifiers by adding only one pair of choppers, resulting in an amplifier with no 1/f noise and a thermal noise of 27 $\mathrm{n}\mathrm{V}\mathrm{/}\sqrt{\mathrm{H}\mathrm{z}}$ [14]. Additionally, Stanescu et al. combined chopping with symmetric notch filtering, reducing the noise PSD to 7.5 without altering the primary path’s equivalent RC network [15]. Dzahini et al. introduced a continuous-time auto-zeroing stabilized architecture, achieving a typical input offset voltage of 2 $\mu \mathrm{V}$ and a temperature drift of 100 $\mathrm{n}\mathrm{V}\mathrm{/}°\mathrm{C}$ [16]. Research on high-voltage operational amplifiers with high precision remains limited. Kilesnikov et al. focused on high-voltage operational amplifiers without dynamic offset compensation, resulting in an offset voltage of 300 $\mu \mathrm{V}$ at a 36 V supply voltage [17]. In contrast, Kusuda proposed an auto-zeroing and chopper operational amplifier operating across a 4.5 to 60 V supply range. It employed post-production trimming to achieve a maximum offset voltage drift of 0.02 $\mu \mathrm{V}\mathrm{/}°\mathrm{C}$ and a noise PSD of 6.8 $\mathrm{n}\mathrm{V}\mathrm{/}\sqrt{\mathrm{H}\mathrm{z}}$ [18]. Current research on high-voltage operational amplifiers predominantly focuses on optimizing single performance metrics, such as noise or offset voltage reduction, with a limited emphasis on comprehensive multi-dimensional performance enhancement. Furthermore, most existing designs operate at a 30 V supply voltage [19], which is inadequate for applications requiring higher-voltage environments.

This paper addresses these challenges by proposing a novel operational amplifier design at a 55 V supply voltage. The design integrates chopping and ping-pong auto-zeroing structures, as supported by patents on a ping-pong auto-zeroing amplifier. The auto-zeroing structure suppresses the chopper ripple induced by modulation, while a six-channel parallel connection mitigates chopper glitches caused by charge injection and clock feedthrough. This configuration achieves low noise, a low offset, and rail-to-rail output characteristics under high-voltage conditions, offering a high-performance solution for applications in sensor analog front ends, medical devices, and automotive electronics.

2. Circuit Design

The high-voltage chopper amplifier structure adopted in this paper is shown in Figure 1.

In chopper amplifier design, the charge injection and clock feedthrough of the chopper switches have always been the primary factors affecting the offset voltage and noise of the operational amplifier. The chopper switch demodulates the mismatch caused by charge injection in the input chopper switch and appears as an offset of the differential input. Figure 2 illustrates the transient waveform at the amplifier’s input under the influence of charge injection, with the charges injected during each clock transition represented by q1–q4. Ideally, charges q3 and q1 can cancel each other when input to Gm1, similarly to charges q4 and q2.

In practice, due to mismatches, errors are inevitable. Let the charge mismatch $△q_{3,1}=q_3-q_1$ and $△q_{4,2}=q_4-q_2$. The current resulting from these mismatches is subjected to chopper modulation and flows to $V_{in+}$ and $V_{in-}$, producing the DC bias components $I_{bias+}$ and $I_{bias-}$, which can be expressed as

$$\begin{array}{c}{I}_{bias+}=f_{ch}△q_{3,1}-△q_{4,2}\end{array}$$

(1)

$$\begin{array}{c} I_{bias-}=-f_{ch}△q_{3,1}-△q_{4,2}\end{array}$$

(2)

Furthermore, since each chopper switch has an on-resistance, R_on, the input bias currents flowing through them will result in a residual input offset voltage, $V_{os,ch}$.

$$\begin{array}{c}{V}_{os,ch}=2f_{ch}△q_{3,1}-△q_{4,2}{R}_{on}\end{array}$$

(3)

In high-voltage designs, if traditional switching timing is employed, where the high and low levels of the timing correspond to the positive and negative supply voltages, the charge injection can be expressed as $\Delta q=C\Delta U$. When the common-mode level significantly deviates from the supply voltage, the offset voltage induced by charge injection becomes substantial. For instance, using a 50 V supply voltage compared to a 5 V supply voltage design, the input-referred offset voltage increases by 10. Furthermore, the charge injection quantity $Q_{inj}$ of an MOS (Metal Oxide Semiconductor) transistor can be approximated as

$$\begin{array}{c}{Q}_{inj}\approx C_{ox}\cdot W\cdot L\cdot \left(V_{GS}-V_{TH}\right)\end{array}$$

(4)

The on-resistance $R_{on}$ of the transistor can be approximated by the following expression:

$$\begin{array}{c}{R}_{on}\approx {\displaystyle \frac{1}{{\mu }_n{C}_{ox}\left(W/L\right)\left(V_{GS}-V_{TH}\right)}}\end{array}$$

(5)

From Equations (4) and (5), it is evident that reducing W and L minimizes the charge injection effect while also lowering the noise in chopper. This paper proposes a common-mode tracking regulator (CM-Reg) to address the charge injection issue in high-voltage applications. This structure allows the voltage variation across the switch, i.e., the gate–source voltage of the MOS switch, to be set to a fixed value. Additionally, the substrate potential of the MOS transistor can track changes in the input common-mode voltage, further mitigating the impact of the body effect. The circuit is illustrated in Figure 3 and Figure 4.

The $CH\_VDD$ generation circuit consists of MP1, MP2, R1, R2, and the tail current source MN3. MN4, a high-voltage transistor, effectively isolates the node, ensuring that the transistors operate within a safe voltage range. The differential input signals INN and INP generate an AC ground signal at node X. $CH\_VDD$ can be expressed as

$$\begin{array}{c}CH\_VDD=V_{GS,mp1}+IR\end{array}$$

(6)

Under a fixed current condition, $V_{gs,mp1}$ remains relatively constant. By adjusting the resistor values, a voltage that varies with the input common-mode voltage can be obtained. In this design, $CH\_VDD$ is set to approximately $(V_{\mathit{incm}}+1.6)\mathrm{V}$.

Similarly, the input transistors of the $CH\_VSS$ generator are composed of PMOS (P-type Metal Oxide Semiconductor) transistors, mirroring the structure of the $CH\_VDD$ generator. This configuration ensures the largest input range for the amplifier. In Figure 4, MP5 and MP6 can be regarded as a split form of a single transistor. The value of $CH\_VSS$ can be expressed as

$$\begin{array}{c}\begin{array}{c}CH\_VSS=V_{GS,mp3}-V_{GS,mp5,6}\end{array}\end{array}$$

(7)

MN3, MN4, MP7, and MP8 are high-voltage transistors employed to ensure that the low-voltage transistors operate within a safe voltage range. In this design, $CH\_VSS$ is set to be equal to the input common-mode level. Furthermore, due to the high-voltage environment, specific nodes may experience transient high-voltage pulses during large-signal settling or power-up processes that could potentially damage devices. To address this, the design incorporates diode-connected MOS transistors to protect nodes prone to such pulses, as shown in the boxed section of Figure 4. When the input signal exhibits significant fluctuations, these structures clamp the voltage across the nodes, ensuring that the MOS transistors remain within a safe voltage range.

The circuit generates $CH\_VDD$ and $CH\_VSS$ voltages to power a two-phase non-overlapping clock generator, producing clock signals that track the input common-mode voltage for use by the chopper input switches. This ensures that the NMOS (N-type Metal Oxide Semiconductor) switches maintain a constant 1.6 V gate–source turn-on voltage. Additionally, the back gates of the switches are driven by $CH\_VSS$ to avoid threshold voltage changes due to the body effect. As a result, the charge injections and on-resistance are maintained at a constant level with a change in $V_{incm}$.

The operational amplifier is primarily a three-stage amplifier with a nested Miller compensation structure. The overall circuit schematic is depicted in Figure 5.

This design integrates input auto-zeroing, output auto-zeroing, and chopper techniques and employs a six-channel parallel configuration. The operation is divided into three phases: offset storage (pre-charge, PC), offset cancelation, and chopper amplification. The timing relationship for the six channels ensures that at any given moment, one channel is in the PC phase, one channel is in the auto-zeroing (AZ) phase, and the remaining four channels are in the amplification phase (CH or CH_INV). The timing diagram for the six channels is shown in Figure 6a, while the single-channel timing is illustrated in Figure 6b.

During the offset storage phase, also known as the pre-charge phase, switches S1, S2, S3, S4, S5, S6, S7, S8, and S9 are closed. Currently, the common-mode buffer (CM-buf) provides a 1.6 V common-mode voltage to the input of the amplifier while biasing the amplifier’s output common-mode voltage at $V_{cm}$. In this configuration, the circuit employs an auto-zeroing structure with an “auxiliary amplifier,” where $G_{maz}$ represents the auxiliary amplifier. To analyze the offset voltage in this phase, we denote the trans-impedance of GM1 as R and account for the offset voltage $V_{os2}$ of $G_{maz}$. This leads to Equations (7) and (8).

$$\begin{array}{c}{G}_{m1}{V}_{os1}R-G_{maz}\left(V_{out}-V_{os2}\right)R=V_{out}\end{array}$$

(8)

$$\begin{array}{c}{V}_{out}={\displaystyle \frac{G_{m1}{V}_{os1}R+G_{m2}{V}_{os2}R}{1+G_{m2}R}}\end{array}$$

(9)

At this point, the equivalent offset voltage at the input can be expressed as

$$\begin{array}{c}{V}_{os,tot}={\displaystyle \frac{V_{out}}{G_{m1}R}}={\displaystyle \frac{V_{os1}}{1+G_{m2}R}}+{\displaystyle \frac{G_{m2}}{G_{m1}}}\left({\displaystyle \frac{V_{os2}}{1+G_{m2}R}}\right)\end{array}$$

(10)

The offset voltage is stored on C_az. During the offset cancelation, switches S3 and S4 are opened, while the other switches remain unchanged. At this stage, the trans-impedance R and $G_{maz}$ form a negative feedback system, thereby eliminating the offset voltage. Generally, since $G_{mR}>>1$, ensuring $G_{m1}>>G_{maz}$ can significantly reduce the offset voltage. Moreover, when switches S3 and S4 are closed, the circuit effectively replicates the amplifier’s offset voltage Vos1 at nodes X and Y. The input-referred offset of the entire circuit is $V_{os1}/A_1$, substantially better than the equivalent total offset voltage of Vos derived in Equation (9).

In the chopping phase, switches S10 and S11 are closed, and Gm1, in conjunction with the cascaded Gm2 and Gm3, amplifies the input signal. Since the circuit has undergone the auto-zeroing phase, the original offset of Gm1 is canceled by $G_{maz}$, resulting in a significantly reduced chopping ripple at the output. The chopper modulates the equivalent offset voltage and 1/f noise at the input to the chopping frequency Fc, which is filtered out by a low-pass filter. Additionally, when configured in a six-channel parallel connection, the charge injection effects of the MOS switches at the chopping frequency are also mitigated.

The core of the circuit is a three-stage amplifier with a nested Miller compensation structure [20]. Figure 7 shows a simplified schematic of the circuit.

In Figure 7, Gmi, Ri, and Ci (where i = 1, 2, 3) represent the transconductance, output impedance, and equivalent parasitic capacitor of the ith stage, respectively. Gm1 and Gm2 are the compensation capacitors, and CL includes the load capacitor and output parasitic capacitor of the third stage. Assuming that the DC gain of the amplifier is very high and that the compensation and load capacitors are much larger than the parasitic capacitors, this circuit’s closed-loop signal transfer function $A_V\left(s\right)$ can be expressed as

$$\begin{array}{c}{A}_v\left(s\right)={\displaystyle \frac{A_{dc}}{1+\beta A_{dc}}}{\displaystyle \frac{1-\frac{C_{m2}}{g_{m3}}s-\frac{C_{m1}{C}_{m2}}{g_{m2}{g}_{m3}}{s}^2}{D\left(s\right)}}\end{array}$$

(11)

$$\begin{array}{c}D\left(s\right)=1+\left({\displaystyle \frac{C_{m1}}{\beta g_{m1}}}-{\displaystyle \frac{C_{m2}}{g_{m3}}}\right)s\end{array}+\left({\displaystyle \frac{g_{m3}-g_{m2}-\beta g_{m1}}{\beta g_{m1}}}{\displaystyle \frac{C_{m1}{C}_{m2}}{g_{m2}{g}_{m3}}}\right)s^2+{\displaystyle \frac{C_{m1}{C}_{m2}{C}_L}{\beta g_{m1}{g}_{m2}{g}_{m3}}}{s}^3$$

(12)

$$\begin{array}{c}D\left(s\right)=\left(1+{\displaystyle \frac{s}{{\omega }_{p1}}}\right)\left(1+{\displaystyle \frac{s}{{\omega }_{p2}}}\right)\left(1+{\displaystyle \frac{s}{{\omega }_{p3}}}\right)\end{array}$$

(13)

The three poles can be derived by describing (11) and (12) as fp1, fp2, and fp3, respectively.

$$\begin{array}{c}\begin{array}{c}{f}_{p1}\approx {\displaystyle \frac{g_{m1}}{2\pi C_{m1}}}\end{array}\end{array}$$

(14)

$$\begin{array}{c}\begin{array}{c}{f}_{p2}\approx {\displaystyle \frac{g_{m2}}{2\pi C_{m2}}}\end{array}\end{array}$$

(15)

$$\begin{array}{c}\begin{array}{c}{f}_{p3}\approx {\displaystyle \frac{g_{m3}}{2\pi C_L}}\end{array}\end{array}$$

(16)

From Equation (10), we have two zeros, which are

$$\begin{array}{c}\begin{array}{c}{f}_{z,RHP}={\displaystyle \frac{g_{m2}}{4\pi C_{m1}}}\left(-1+\sqrt{1+{\displaystyle \frac{4g_{m3}{C}_{m1}}{g_{m2}{C}_{m2}}}}\right)\end{array}\end{array}$$

(17)

$$\begin{array}{c}{f}_{z,LHP}=-{\displaystyle \frac{g_{m2}}{4\pi C_{m1}}}\left(1+\sqrt{1+{\displaystyle \frac{4g_{m3}{C}_{m1}}{g_{m2}{C}_{m2}}}}\right)\end{array}$$

(18)

The zero in the right half-plane may reduce the closed-loop stability; therefore, the design must connect a nulling resistor in series with the compensation capacitor to eliminate the right half-plane zero.

The structure of the first-stage amplifier, as depicted in Figure 8, primarily comprises two sets of differential input cascode amplifiers. An auxiliary amplifier is incorporated into the cascode amplifier to eliminate the offset. The operational amplifier utilizes complementary NMOS and PMOS differential pairs for its input stage. This configuration provides two benefits: first, it enhances the transconductance of the amplifier; secondly, since the input transistors share the bias current, it doubles the output capability without increasing the power consumption.

The design of the second and third amplifier stages is based on a conventional folded cascode structure, with the output stage optimized for high-voltage operation. A linear transconductance loop tailored for high-voltage applications is introduced, with the overall architecture depicted in Figure 9. To ensure effective cascading in the first stage, which has an output common-mode voltage of 1.8 V, the PMOS differential input pair of the subsequent stages employs a 4.2 V supply to maintain bias compatibility.

The output stage is an enhanced high-voltage design built upon a traditional Class AB structure, operating at a 55 V supply voltage to meet the demands of high-voltage applications. Within the designed linear transconductance loop, NDMOS (N-type Double-Diffused MOSFET) devices (DMOS1 and DMOS2) are utilized as high-voltage clamping devices to limit the voltage difference between the 5 V transistors and the supply rails to no more than 4 V, which thereby effectively protects low-voltage devices from breakdown.

Similarly, DMOS3 and DMOS4 are incorporated in the output stage to provide overvoltage protection for transistors M7 and M8. This design enhances the circuit’s adaptability to high-voltage environments and improves the amplifier’s gain performance by increasing the equivalent output impedance, Rout, which is expressed in Equation (18).

$$R_{out}=(g_{m, DMOS3}\cdot r_{o, DMOS3}\cdot r_{o, M7})\parallel (g_{m, DMOS4}\cdot r_{o, DMOS4}\cdot r_{o, M8})$$

(19)

Switching regulators are commonly used for step-down conversion within system-on-chip or digital circuits in low-voltage applications. However, in high-voltage environments, this approach introduces significant electromagnetic interference and results in substantial ripple and noise in the output voltage. To address this, the proposed design employs a high-voltage LDO (Low-Dropout Regulator) as an intermediate stage for voltage conversion, directly generating a low-voltage supply from a 55 V high-voltage source to power the chip. The circuit is illustrated in Figure 10. To protect the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in the error amplifier from high-voltage breakdown, high-voltage DMOS (Double-Diffused MOSFET) transistors are incorporated in each branch to isolate high-voltage nodes, ensuring the MOSFETs operate within a safe voltage range.

A bias circuit generates the reference $Vref$ for the error amplifier. A depletion-mode MOSFET, M1, and resistor, R1, form a current-generating branch in the bias circuit. Due to the negative threshold voltage, the Vth of M1 remains conductive when the circuit is unpowered, ensuring excellent self-startup characteristics without requiring an additional startup circuit. During regular operation, the branch current can be approximated as $I_{D2}\approx -V_{th}{R}_1$, forming a stable current source. Using a current mirror structure, this current is replicated in the branch generating $V_{ref}$, providing a stable reference voltage.

A pre-regulator structure is introduced to supply a stable voltage to the error amplifier and bias circuit to enhance the high-voltage protection further. This pre-regulator effectively limits the gate–source voltage of each MOSFET to prevent high-voltage breakdown and ensure circuit reliability.

Overvoltage protection circuits are critical in larger power systems, as shown in Figure 11. This circuit primarily consists of a sampling circuit, a comparator, and an output shaping circuit. The comparator compares the two branch currents, I₁ and I₂, to determine whether an undervoltage condition exists. The current through the MOSFET is determined by the gate–source voltage V_GS and the width-to-length ratio (W/L). In this configuration, the circuit operates in two typical states: one is the V_GS-dominant mode, where the effect of V_GS on the current is greater than the effect of the width-to-length ratio. At this point, the voltage at node Y is pulled up to VDD (Voltage Drain Drain), the output V_out is high, and transistor M7 is turned off. The second is the width-to-length ratio-dominant mode, where the influence of V_GS is less than that of the width-to-length ratio. At this point, the voltage at node Y is pulled down to VSS (Voltage Source Source), the output V_out is low, and M7 is turned on. By comparing the magnitudes of I1 and I2, the circuit dynamically controls the conduction state of M7 to achieve undervoltage protection. When VDD rises from 0 V, the width-to-length ratio primarily determines the current. Since, at this point, the voltage V_Y at node Y is pulled down to VSS, V_out = 0, and M7 conducts. The output voltage V_X1 can be expressed as

$$\begin{array}{c}{V}_{X1}=\left({\displaystyle \frac{R_2+R_3}{R_1+R_2+R_3}}\right)\times V_{DD}\end{array}$$

(20)

When VDD rises to a specific value, the effect of V_GS gradually dominates, pulling the voltage at node Y up to VDD, resulting in V_out = 1 and M7 turning off. At this point, the output voltage V_X2 becomes

$$\begin{array}{c}{V}_{X2}=\left({\displaystyle \frac{R_2}{R_1+R_2}}\right)\times V_{DD}\end{array}$$

(21)

In the critical state where the effect of the width-to-length ratio on the current is balanced with the effect of V_GS on the current, I1 = I2. At this point, the threshold voltage V_in for undervoltage protection can be derived, expressed as

$$V_{in}={\displaystyle \frac{4{\left[\sqrt{\frac{1}{{\mu }_n{C}_{ox}{(W/L)}_1}}-\sqrt{\frac{1}{{\mu }_n{C}_{ox}{(W/L)}_2}}\right]}^2}{R_4^2}}\left(R_5-4\sqrt{2}{R}_2-2\sqrt{2}{R}_4\right)+\left(1-2\sqrt{2}\right)V_{TH}$$

(22)

3. Post-Simulation Results

The amplifier designed in this work was implemented using the SMIC 0.18 μm BCD process. Figure 12 presents a photograph of the layout, which had an area of 2166 μm × 1944 μm.

The operational amplifier was simulated under the following conditions: a supply voltage of 55 V, an input common-mode voltage of 27.5 V, a load resistance of 10 kΩ, and a load capacitance of 100 pF. Initially, the input noise power spectral density (PSD) was simulated at a supply voltage of 55 V and a temperature of 25 °C. The simulation results, depicted in Figure 13, indicate that the corner frequency was approximately 10 Hz, with the noise PSD only being $6.2 \mathrm{n}\mathrm{V}\mathrm{/}\sqrt{\mathrm{H}\mathrm{z}}$.

To enhance the reliability of the simulation data, the offset was simulated using the Monte Carlo method to compute its mean value. As depicted in Figure 14, the results demonstrate that with 100 sample points, the input offset voltage was 32 $\mu \mathrm{V}$.

Figure 15 shows the amplifier’s closed-loop frequency response. The unity gain bandwidth was 3.32 MHz, and the phase margin was 84°, ensuring the amplifier’s stability in closed-loop conditions.

In high-voltage application scenarios, the precise measurement of weak differential signals is often required under conditions characterized by high common-mode input voltages and elevated supply voltages. This imposes stringent demands on the common-mode rejection ratio (CMRR) and the power supply rejection ratio (PSRR) of the measurement circuitry. The proposed design incorporates input coupling capacitors to enhance the CMRR and an on-chip LDO to improve the PSRR. As demonstrated in Figure 16, the implemented approach achieved a CMRR of up to 167 dB and a PSRR of up to 188 dB, highlighting its efficacy in mitigating the adverse effects of common-mode and power supply variations.

Finally, the amplifier’s slew rate and setup time were simulated, as shown in Figure 17. The slew rate for the rising edge was 3.28 $\mathrm{V}\mathrm{/}\mu \mathrm{s}$, and for the falling edge, it was 1.31 $\mathrm{V}\mathrm{/}\mu \mathrm{s}$. With the error range of the output voltage’s stable value set at 0.1% of Vin, the setup time was determined to be 3.9 $\mu \mathrm{s}$. The results demonstrate the amplifier’s excellent response speeds to large and small signal inputs.

To ensure that the amplifier’s output could accurately reflect the input signal, measuring the Total Harmonic Distortion (THD) was essential. When the amplifier was configured in a unity negative feedback structure with an input signal frequency of 1 kHz and an amplitude of 1 V, the output signal spectrum was as shown in Figure 18, and the THD was −128 dB. Figure 19a,b shows the Total Harmonic Distortion for different frequencies and different input signal amplitudes.

4. Discussion

Table 1. Comparison with other work.

	This Work	[21]	[22]	[23]	[24]	[17]	[19]	[25]
Max. Vsy (V)	55	40	36	27.3	24	33	60	30
Power Current ($\mu \mathrm{A}$)	960	1800	415	3000	500	6650	26	800
Slew Rate $(\mathrm{V}\mathrm{/}\mu \mathrm{s})$	3.28	20	0.8	50	1.6	15.7	—	—
en ($\mathrm{n}\mathrm{V}\mathrm{/}\sqrt{\mathrm{H}\mathrm{z}}$)	6.2	5.1	8.8	6	30	—	31	136
Max. Vos $(\mu \mathrm{V})$	32	120	25	250	10	300	5	5
GBW ($\mathrm{MHz}$)	3.2	11	2	25	1.8	7.95	1	1
CMRR ($\mathrm{dB}$)	167	140	146	110	120	—	160	143
PSRR ($\mathrm{dB}$)	188	140	142	110	128	—	120	121
THD ($\mathrm{dB}$)	−128	−126	−120	—	−108	—	—	—

presents a comparison between the operational amplifier designed in this work and previous achievements. This design competes strongly with other researched state-of-the-art designs regarding its equivalent input noise, offset voltage, frequency characteristics, and power supply rejection ratio. This design achieves excellent performance in terms of its noise and offset voltage by employing multi-channel auto-zeroing and chopper techniques. The overall circuit simulation results indicate that the operational amplifier can precisely amplify small signals under high-voltage conditions.

5. Conclusions

Targeting industrial measurement and automotive electronics applications, a high-voltage chopper ping-pong auto-zeroing operational amplifier based on the SMIC 0.18 $\mu \mathrm{m}$ BCD process was proposed in this paper. The proposed design introduces a high-voltage common-mode follower, effectively suppressing random offsets caused by charge injection. A six-channel parallel first-stage amplifier structure was adopted, significantly reducing the ripple introduced by the chopper. A high-voltage LDO and an undervoltage protection circuit were proposed to enhance the power supply stability and system safety. The simulation results demonstrate that, under a 55 V supply voltage, the amplifier achieves a noise PSD of 6.2 $\mathrm{n}\mathrm{V}\mathrm{/}\sqrt{\mathrm{H}\mathrm{z}}$, an input offset voltage of 32 $\mu \mathrm{V}$, a signal bandwidth of 3.2 MHz, and a slew rate of 3.2 $\mathrm{V}\mathrm{/}\mu \mathrm{s}$. These characteristics meet the requirements for precise high-voltage small-signal measurements in industrial and automotive electronics applications.