Design of Dual-Mode Multi-Band Doherty Power Amplifier Employing Impedance-and-Phase Constrained Optimization

Abstract

To expand the operating frequency bands of the Doherty power amplifier (DPA), this paper proposes a dual-mode multi-band DPA design method employing impedance-and-phase constrained optimization based on reciprocal gate bias. By introducing the concept of reciprocal gate bias, the operating mode is switched by swapping the gate biases of the carrier and peaking amplifiers of the DPA, which effectively extend the operating frequency band without modifying the load modulation network. Furthermore, multiple impedance constraint circles are used to cover the optimum load impedance region obtained from the load-pull simulation. And, the phases required for impedance transformation network (ITN) across the multi-band are determined based on the impedance transformation requirements when the DPA operates in power back-off (PBO) state and saturation state. Then, the ITNs that satisfy the impedance and phase constraints can be optimized and designed. For verification, a dual-mode multi-band DPA, operating in Mode I at 1.96–2.10 GHz and 2.75–2.86 GHz, and in Mode II at 2.49–2.61 GHz and 3.20–3.36 GHz, is designed and fabricated. Measured results show that the output power of the DPA exceeds 43 dBm with corresponding saturated drain efficiencies (DEs) higher than 50% in both modes. For 6 dB PBO, the DEs are 49.4–55.7% and 49.8–51.7% in Mode I, whereas in Mode II, they range from 51.2% to 52.4% and from 50.4% to 53.5%. Moreover, good linearity can be achieved after linearization for 20 MHz modulated signals.

1. Introduction

In modern wireless communication systems, the diversity of business requirements is driving the rapid evolution of technologies [1,2]. On one hand, to meet the complex demands of different services, a series of advanced modulation techniques have been widely adopted, resulting in an increase in the peak-to-average power ratio (PAPR) of signals [3,4,5,6,7]. This poses high requirements for the efficiency of power amplifiers (PAs) in the power back-off (PBO) state [8,9,10]. On the other hand, multiple communication standards coexist in the field of wireless communication [11], including LTE Band (0.7–2.6 GHz) [12,13], 5G NR N77 (3.3–4.2 GHz) [14,15], and N78 (3.3–3.8 GHz) [16,17], which are becoming more distributed. This presents a huge challenge for conventional PA architectures to achieve efficient operation across such wide and scattered frequency bands.

Doherty power amplifiers (DPAs) have been one of the widely used PA architectures in wireless communication base stations due to the simplicity in structure and their ability to achieve high efficiency at saturation and in the PBO state [18,19]. Many studies focus on broadband DPA [20,21]. Nevertheless, because of restrictions in their load modulation network (LMN) designs, an impedance mismatch still exists in the low-power region, resulting in decreased efficiency [22]. A novel topology of the matching network, like single-loop LMN [23] and coupled transmission line-based LMN [24], has also been used to expand bandwidth. Due to the inherent bandwidth limitations of DPA, such as a $\lambda$/4 wavelength transmission line, the extent of bandwidth expansion remains limited, failing to meet the demands of emerging communication standards separated by more than one octave [25,26,27].

In response to the requirements of modern wireless systems where multiple communication standards coexist, multi-band DPAs have emerged as a promising solution. Conventional T- or $\pi$-network-based multi-band impedance transformers, limited by their fixed network structures, usually have narrow operating bandwidths and cannot meet the growing needs of modern communication systems [28,29,30]. Recently, new circuit architectures have been explored to realize multi-band DPAs, such as coupler-based LMNs [31], stub-loaded stepped-impedance transformers [32], and three-way architectures [25]. Tri-band DPAs have also been developed to extend the operational frequency range [33]. Nevertheless, most multi-band DPA implementations have largely concentrated on dual-band or tri-band configurations, which may constrain their applicability in broader spectrum-sharing scenarios. To enhance the flexibility of the load modulation network, the reciprocal gate bias has been proposed for DPA designs to extend the bandwidth and the operating mode without altering the circuit structure [34,35,36]. However, how to simply and effectively utilize this method to expand the operating frequency band remains to be further investigated.

Moreover, to improve the performance of PAs, optimization design methods can be applied to assist in the circuit designs. For example, Bayesian optimization, consisting of a probabilistic surrogate model and an acquisition function as its core components [37], has been employed for broadband DPA design [38] and digitally controlled dual-input DPA design [39]. However, the design process is complex due to the determination of initial parameters needed to employ real-frequency techniques [40]. When compared to these optimization design methods, particle swarm optimization (PSO) streamlines the optimization process while providing robust global search capability, fast convergence, and straightforward extensibility [41]. These characteristics have enabled PSO-based designs of broadband PA [42], and LMBA [43]. Thus, an adaptive PSO will be applied to the optimization design of dual-mode multi-band DPA in this work.

In this paper, a novel multi-band DPA design approach is proposed, which incorporates impedance and phase constrained optimization under reciprocal gate bias, reducing design complexity while effectively expanding the operating frequency bands and bandwidth of the DPA. This paper is structured as follows. Section 2 describes the dual-mode multi-band DPA design theory based on reciprocal gate bias and the impedance-and-phase constrained method. Section 3 details the DPA design and simulation. Section 4 presents fabrication and measurement results. Section 5 is the conclusion.

2. Dual-Mode Multi-Band DPA Optimization Design Theory

The architecture of a conventional DPA is illustrated in Figure 1, which comprises a Class-AB carrier amplifier and a Class-C peaking amplifier. $R_L$ is the load impedance at the combining point. To enhance the performance of a DPA, it is essential to select the optimal load impedance. Post-matching network (PMN) is employed to convert 50 $\mathsf{\Omega }$ to $R_L$ across the operating band. Transistors are divided into their package and current generator (CG). The impedance transformation network (ITN) is formed by an output matching network (OMN) and package. The output architecture of a conventional DPA exhibits limited flexibility, as it can only achieve impedance transformation in one single mode. Specifically, at saturation, both of the carrier and peaking ITN need to transform $Z_{C1,Sat}=Z_{P1,Sat}=2R_L$ to $Z_{C,Sat}=Z_{R,Sat}=R_{opt}$, where $R_L$ and $R_{opt}$ are the load impedance at the combining point and the optimal load impedance at the CG plane, respectively. In the PBO state, the carrier ITN needs to transform $Z_{C1,PBO}=R_L$ to $Z_{C,PBO}=2R_{opt}$, while the peaking branch remains inactive, requiring its output impedance $Z_{P1,Out}$ to be infinite. By satisfying the aforementioned impedance transformations, the desired Doherty characteristics can be achieved.

2.1. Dual-Mode DPA Architecture Based on Reciprocal Gate Bias

In this paper, a dual-mode DPA output architecture based on reciprocal bias [44,45] is employed, as illustrated in Figure 2, which enables the DPA to operate effectively in different modes without altering the circuit structure.

Table 1. Functions of CG1, CG2, ITN1, and ITN2 in dual-mode operation.

	CG1	CG2	ITN1	ITN2
Mode I	carrier PA	peaking PA	carrier ITN	peaking ITN
Mode II	peaking PA	carrier PA	peaking ITN	carrier ITN

illustrates functions of CG1, CG2, ITN1, and ITN2 in dual-mode operation.

By swapping the gate bias of the two transistors, $V_{G1}$ and $V_{G2}$, the roles of the carrier and peaking amplifiers interchange accordingly. In Mode I, the CG1 biased with $V_{G1}$ at Class-AB works as the carrier PA, while the CG2 biased with $V_{G2}$ at Class-C works as the peaking PA. ITN1 functions as the carrier ITN, facilitating the impedance transformation from $Z_{C1,Sat}=2R_L$ to $Z_{C,Sat}=R_{opt}$ at saturation and from $Z_{C1,PBO}=R_L$ to $Z_{C,PBO}=2R_{opt}$ in PBO. Simultaneously, ITN2 functions as the peaking ITN, achieving impedance transformation at saturation from $Z_{P1,Sat}=2R_L$ to $Z_{P,Sat}=R_{opt}$, and guaranteeing the output impedance $Z_{P1,Out}$ of the peaking branch in PBO to be infinite.

After the gate biases are swapped, the DPA switches into Mode II, where the CG1 becomes the peaking PA and the CG2 becomes the carrier PA. It should be noted that, although ITN1 and ITN2 in the DPA circuit structure remain unchanged, their functions have been swapped. Specifically, ITN1 now functions as the peaking ITN, while ITN2 functions as the carrier ITN. Due to the different frequency responses of the ITNs in different operating modes, through appropriate design, the DPA can achieve dual-band operation in the same mode, as shown in Figure 2. As a result, the combined operating band of the DPA will be expanded.

During the process of designing the ITNs for the reciprocal gate bias dual-mode DPA, it is necessary to consider the impedance and phase delay requirements in both modes, so as to achieve Doherty operation.

2.2. Load Impedance Region Determination Methods

Load-pull simulation is a commonly used method for obtaining the optimum impedance region. As shown in Figure 3, the overlapping part of the equal-power circles and equal-efficiency circles is the optimum load impedance region. Since the obtained region has an irregular shape, an appropriate method is required to describe it. Conventional impedance constraints are typically calculated using the absolute value of impedance error between the achieved impedance and the target one. To enhance the feasibility of the optimization design, Kong et al. [18] proposed a method based on an inner-tangent circle, which is selected as the optimized target load impedance area. In order to further improve the utilization of the optimum load impedance region, this paper employs multiple impedance constraint circles to describe the region, as shown in Figure 3, where the target load impedance area is expanded compared to previous methods.

To improve the utilization of the optimum load impedance region, this paper employs multiple impedance constraint circles to describe the region, as shown in Figure 3. For each impedance constraint circle, $|\Gamma |$ represents its radius, which can be calculated by (1):

$$|\Gamma |=|{\displaystyle \frac{Z_a-Z_{center}}{Z_a+Z_{center}^{*}}}|$$

(1)

where $Z_a$ represents a point on the impedance constraint circle that is tangent to the optimum impedance region, and $Z_{center}$ represents the center of the circle.

2.3. Determination of ITN Phase Delay

The bandwidth of the DPA is significantly influenced by the phase delays of the carrier and peaking ITNs. The schematic of the ideal load modulation network of the DPA is shown in Figure 4.

Table A1. Variable symbols and definitions.

Variable Symbol	Definition
${\theta }_C$	Target phase delay for the carrier ITN.
${\theta }_P$	Target phase delay for the peaking ITN.
m	Phase delay parameter for the carrier ITN.
n	Phase delay parameter for the peaking ITN.
$f_L$	Design frequency of the low target band.
$f_H$	Design frequency of the high target band.
${\theta }_{C\text{\_}L}$	Target phase delay of the carrier ITN at $f_L$.
${\theta }_{C\text{\_}H}$	Target phase delay of the carrier ITN at $f_H$.
${\theta }_{P\text{\_}L}$	Target phase delay of the peaking ITN at $f_L$.
${\theta }_{P\text{\_}H}$	Target phase delay of the peaking ITN at $f_H$.
$m_1$	Phase delay parameter of the carrier ITN at $f_L$.
$m_2$	Phase delay parameter of the carrier ITN at $f_H$.
$n_1$	Phase delay parameter of the peaking ITN at $f_L$.
$n_2$	Phase delay parameter of the peaking ITN at $f_H$.
$F_{\theta }$	Phase delay optimization objective function.
${\theta }_{IL}$	ITN phase delay at $f_{I\text{\_}L}$ in Mode I.
${\theta }_{IH}$	ITN phase delay at $f_{I\text{\_}H}$ in Mode I.
${\theta }_{IIL}$	ITN phase delay at $f_{II\text{\_}L}$ in Mode II.
${\theta }_{IIH}$	ITN phase delay at $f_{II\text{\_}H}$ in Mode II.
${\theta }_{I\text{\_}L}$	Target phase delay for the ITN at $f_{I\text{\_}L}$ in Mode I.
${\theta }_{I\text{\_}H}$	Target phase delay for the ITN at $f_{I\text{\_}H}$ in Mode I.
${\theta }_{II\text{\_}L}$	Target phase delay for the ITN at $f_{II\text{\_}L}$ in Mode II.
${\theta }_{II\text{\_}H}$	Target phase delay for the ITN at $f_{II\text{\_}H}$ in Mode II.
$Z_b$	Load impedance of the ITN at a specific design frequency.
$Z_{center\text{\_}1}$	Center impedance of the first impedance constraint circle.
$|{\Gamma }_1|$	Radius of the first impedance constraint circle.
$Z_{center\text{\_}n}$	Center impedance of the n-th impedance constraint circle.
$|{\Gamma }_n|$	Radius of the n-th impedance constraint circle.
$F_{\Gamma }$	Comprehensive impedance optimization objective function.
F	Total optimization objective function.

in Appendix A summarizes the variable symbols and their definitions in the process of phase delay determination. To achieve the desired impedance transformation, the phase delay ${\theta }_C$ of the carrier ITN and the phase delay ${\theta }_P$ of the peaking ITN can be expressed by (2) and (3), respectively:

$${\theta }_C=-{90}^{\circ }-m\times {180}^{\circ }$$

(2)

$${\theta }_P=-{180}^{\circ }-n\times {180}^{\circ }$$

(3)

where m and n represent the required phase delay parameters for the carrier ITN and peaking ITN, respectively.

$f_L$ and $f_H$ are assumed as the design frequencies for the low and high target bands, respectively. According to [33], the phase delay parameters of the ITN are derived as a function of the design frequencies, based on the principle of phase periodicity. Let ${\theta }_{C\text{\_}L}$ and ${\theta }_{C\text{\_}H}$ represent the phase delay target of the carrier ITN at $f_L$ and $f_H$, respectively. Given that the carrier ITN’s phase delay is frequency-dependent, substituting this relationship into (2) yields (4):

$$\begin{array}{cc}\hfill {\theta }_{C\text{\_}L}:{\theta }_{C\text{\_}H}& =f_L:f_H\hfill \\ \hfill & =(-{90}^{\circ }-m_1\times {180}^{\circ }):(-{90}^{\circ }-m_2\times {180}^{\circ })\hfill \end{array}$$

(4)

where $m_1$ and $m_2$ denote the phase delay parameters of the carrier ITN, and they are non-negative integers that satisfy $m_2$> $m_1$. Similarly, let ${\theta }_{P\text{\_}L}$ and ${\theta }_{P\text{\_}H}$ represent the phase delay target of the peaking ITN at $f_L$ and $f_H$, respectively. Substituting the relationship according to [33] into (3) yields (5):

$$\begin{array}{cc}\hfill {\theta }_{P\text{\_}L}:{\theta }_{P\text{\_}H}& =f_L:f_H\hfill \\ \hfill & =(-{180}^{\circ }-n_1\times {180}^{\circ }):(-{180}^{\circ }-n_2\times {180}^{\circ })\hfill \end{array}$$

(5)

where $n_1$ and $n_2$ denote the phase delay parameters of the peaking ITN, and they are non-negative integers, satisfying $n_2$> $n_1$.

A realizable ITN has different frequency responses at different design frequencies. The phase delay parameters for the carrier and peaking ITNs are expressed as (6) and (7):

$$m_2={\displaystyle \frac{f_H}{f_L}}\left(m_1+{\displaystyle \frac{1}{2}}\right)-{\displaystyle \frac{1}{2}}$$

(6)

$$n_2={\displaystyle \frac{f_H}{f_L}}(n_1+1)-1$$

(7)

Once the phase delay parameters for the low and high target bands are determined, the phase delays of the carrier and peaking ITNs can be calculated using (6) and (7). These phase delays will serve as optimization objectives in the design of carrier and peaking ITNs.

2.4. Impedance-and-Phase Constrained Optimization

A schematic for impedance and phase simulation is illustrated in Figure 5, where the phase delay at the CG plane and the impedance at the package plane can be obtained simultaneously. Through the aforementioned analysis of the required impedance and phase delay for the dual-mode multi-band DPA, this paper proposes a design approach based on impedance-and-phase constrained optimization. This approach can effectively reduce the complexity associated with the design of dual-mode multi-band DPA. Table A1 summarizes the variable symbols and their definitions for impedance-and-phase constrained optimization.

Assuming that the frequencies $f_{I\text{\_}L}$, $f_{I\text{\_}H}$, $f_{II\text{\_}L}$, and $f_{II\text{\_}H}$ are the design frequencies for lower and upper bands in two modes, respectively, the ITN in Mode I serves as the carrier ITN, with phase delay targets ${\theta }_{I\text{\_}L}$ and ${\theta }_{I\text{\_}H}$, according to (2), while it serves as the peaking ITN in Mode II, with phase delay targets ${\theta }_{II\text{\_}L}$ and ${\theta }_{II\text{\_}H}$ according to (3). Consequently, the phase delay optimization objective function for the ITN is formulated as shown in (8):

$$F_{\theta }({\theta }_{IL},{\theta }_{IH},{\theta }_{IIL},{\theta }_{IIH})=max\left(\left|\frac{{\theta }_{IL}-{\theta }_{I\text{\_}L}}{40}\right|,\left|\frac{{\theta }_{IH}-{\theta }_{I\text{\_}H}}{40}\right|,\left|\frac{{\theta }_{IIL}-{\theta }_{II\text{\_}L}}{40}\right|,\left|\frac{{\theta }_{IIH}-{\theta }_{II\text{\_}H}}{40}\right|\right)$$

(8)

where ${\theta }_{IL}$, ${\theta }_{IH}$, ${\theta }_{IIL}$ and ${\theta }_{IIH}$ represent the ITN phase delays to be optimized at the corresponding design frequencies in Mode I and Mode II, respectively. When the maximum value of $F_{\theta }$ is less than 1, the deviations between the phase delay of the designed ITN and targets meet specific requirements. To obtain the optimal load impedance for the design frequencies $f_{I\text{\_}L}$, $f_{I\text{\_}H}$, $f_{II\text{\_}L}$, and $f_{II\text{\_}H}$, appropriate impedance constraint circles are selected to characterize the target impedance regions at different frequencies as illustrated in Figure 3. The impedance optimization objective function for ITN1 at each design frequency is expressed in (9):

$$\begin{array}{cc}\hfill F_{{\Gamma }_{\text{\_}}b}\left(Z_b\right)& =min\left({\displaystyle \frac{1}{|\Gamma |}}\left|{\displaystyle \frac{Z_b-Z_{center\text{\_}1}}{Z_b+Z_{center\text{\_}1}^{*}}}\right|,\dots ,{\displaystyle \frac{1}{|\Gamma |}}\left|{\displaystyle \frac{Z_b-Z_{center\text{\_}n}}{Z_b+Z_{center\text{\_}n}^{*}}}\right|\right)\hfill \\ \hfill & (b=I\text{\_}L,I\text{\_}H,II\text{\_}L,II\text{\_}H)\hfill \end{array}$$

(9)

where $Z_{center\text{\_}1}$ to $Z_{center\text{\_}n}$ represent the centers of reflection coefficient constraint circles, and $|{\Gamma }_1|$ to $|{\Gamma }_n|$ denote the radii of these circles. $Z_b$ represents the load impedance of the ITN, where the subscript k can take values $I\text{\_}L$, $I\text{\_}H$, $II\text{\_}L$, and $II\text{\_}H$, corresponding to the four design frequencies. When the minimum value of $F_{\Gamma \text{\_}b}$ is less than 1, it indicates that $Z_b$ falls within at least one selected impedance constraint circle, achieving optimization. Notably, the impedance optimization objective has been achieved. To ensure that the ITN simultaneously satisfies the impedance constraint requirements at each design frequency, the impedance optimization objective function is designed as shown in (10):

$$F_{\Gamma }=max\left(F_{\Gamma \text{\_}I\text{\_}L}\left(Z_{I\text{\_}L}\right),F_{\Gamma \text{\_}I\text{\_}H}\left(Z_{I\text{\_}H}\right),F_{\Gamma \text{\_}II\text{\_}L}\left(Z_{II\text{\_}L}\right),F_{\Gamma \text{\_}II\text{\_}H}\left(Z_{II\text{\_}H}\right)\right)$$

(10)

where $Z_{I\text{\_}L}$, $Z_{I\text{\_}H}$, $Z_{II\text{\_}L}$, and $Z_{II\text{\_}H}$ represent the impedances of ITNs that need to be optimized in dual-mode multi-band operation. When the maximum value of $F_{\Gamma }$ is less than 1, it indicates that the impedance values of the OMN at each operating frequency have been optimized to fall within the target impedance region.

By combining (8) and (10), the impedance-and-phase constrained optimization objective function is formulated as shown in (11):

$$F=max(F_{\theta },F_{\Gamma })$$

(11)

When the impedance-and-phase constrained optimization objective function F converges to a value less than 1, it signifies that the ITN has successfully achieved the design objectives.

In order to achieve better performance, various optimization methods have been widely applied to numerous engineering problems [46,47,48,49,50,51,52,53,54]. Therefore, to further enhance both the global optimization efficiency of complex systems and the dynamic adaptability of algorithms, the adaptive particle swarm optimization (APSO) is proposed. The flow chart of the above optimization design process is illustrated in Figure 6. Initially, the ITN topology is determined, and then, the APSO parameters, such as population size, number of iterations, and initial population, are initialized, in which each particle in the population corresponds to the design variables of the ITN (i.e., the width and length of microstrip lines). Subsequently, each particle is transferred to an Advanced Design System (ADS) through an interface program to generate the ITN topology, and S-parameter simulation is performed to obtain the impedance and phase corresponding to the generated ITN. Following this, the simulated results are transferred to MATLAB 2022 through the interface program, after which they are evaluated using the proposed impedance-and-phase optimization objective function. The iteration of APSO continues until the optimization objective is satisfied.

In summary, the proposed dual-mode multi-band DPA utilizes reciprocal gate bias to switch between operating modes, thereby extending the operational frequency bands. Based on load-pull simulations, multiple impedance constraint circles are introduced to encompass optimal load impedance regions. Phase delay targets are derived from the principle of phase periodicity. Subsequently, the optimization design of ITNs is processed with impedance and phase constraints using APSO. This approach enables high-efficiency operation across all designated frequency bands in both modes.

3. Design and Simulation of Dual-Mode Multi-Band DPA

To verify the proposed design method, a dual-mode multi-band DPA is designed and simulated using Wolfspeed CGH40010F GaN transistors. The center frequencies are selected as 2.0 and 2.8 GHz in Mode I, and 2.5 and 3.3 GHz in Mode II, due to the presence of a large number of commonly used communication frequency bands in their vicinity. The relevant details are elaborated in the Introduction section. Rogers 4350, a dielectric substrate material with a relative dielectric constant of 3.66 and a thickness of 30 mils, is chosen for this design.

3.1. Determination of the Impedance Constraint Region

Considering that the dual-mode multi-band DPA operates at center frequencies of 2.0, 2.8, 2.5, and 3.3 GHz, load-pull simulations are performed for these four frequencies, as illustrated in Figure 7. For each optimum impedance region, four impedance constraint circles are introduced to maximize utilization. The centers $Z_{center\text{\_}1}$ to $Z_{center\text{\_}4}$ and radii $|{\Gamma }_1|$ to $|{\Gamma }_4|$ of these circles are detailed in

Table 2. Impedance constraint circle parameters at four design frequencies.

Frequency (GHz)	2.0 GHz	2.8 GHz	2.5 GHz	3.3 GHz
$Z_{center\text{\_}1}$	13.86 + j × 12.24	20.73 + j × 8.15	14.79 + j × 6.8	12.38 + j × 3.77
$|{\Gamma }_1|$	0.198	0.22	0.2	0.104
$Z_{center\text{\_}2}$	23.3 + j × 12.45	27.5 + j × 13.72	24.68 + j × 5.41	18.16 + j × 1.49
$|{\Gamma }_2|$	0.208	0.148	0.098	0.154
$Z_{center\text{\_}3}$	32.83 + j × 6.66	21.17 + j × 4.91	17.98 + j × 4.48	24.96 + j × 1.81
$|{\Gamma }_3|$	0.139	0.145	0.144	0.078
$Z_{center\text{\_}4}$	22.17 + j × 4.91	11.87 + j × 8.8	11.87 + j × 8.8	12.48 + j × 1.25
$|{\Gamma }_4|$	0.139	0.188	0.181	0.109

. This approach effectively describes the impedance target region in the impedance-and-phase constrained optimization. Since the transistors used in both branches of the dual-mode multi-band DPA are identical, the target impedance regions for the ITNs of both circuits at saturation can be accurately characterized using this method.

3.2. Determination of Phase Delays of Carrier and Peaking ITNs

Once the design frequencies have been determined, the phase delay parameters of the carrier and peaking ITNs can be calculated using (4) and (5). Given that m and n are integers, the values of $n_2$ and $m_2$, calculated using (6) and (7), must be rounded after selecting $n_1$ and $m_1$. The required phase delay targets for ITN1 and ITN2 are summarized in

Table 3. Phase and frequency targets for dual-mode carrier and peaking ITNs.

		Mode I @ 2.0 GHz	Mode I @ 2.8 GHz		Mode II @ 2.5 GHz	Mode II @ 3.3 GHz
ITN1	m	1	2 *	n	1	2 *
	${\theta }_C$	$-{270}^{\circ }$	$-{450}^{\circ }$	${\theta }_P$	$-{360}^{\circ }$	$-{540}^{\circ }$
ITN2	n	1	2 *	m	2	3 *
	${\theta }_P$	$-{360}^{\circ }$	$-{540}^{\circ }$	${\theta }_C$	$-{450}^{\circ }$	$-{630}^{\circ }$

* The values are approximate values.

for the dual-mode multi-band DPA operating at 2.0, 2.8, 2.5, and 3.3 GHz. By applying this method, the phase delay targets for the carrier and peaking ITNs within the target frequency bands can be accurately determined.

3.3. Design of ITNs

Considering the phase delay requirements for the carrier and peaking ITNs of the dual-mode multi-band DPA across the two operating modes, the design process initially focuses on the carrier ITN for Mode I.

Using the impedance-and-phase constrained optimization design described in Section 2.4, multiple optimization iterations are carried out to guarantee that ITN1 satisfies the desired impedance and phase delay requirements at saturation and in the PBO state. The ITN1 topology to be optimized is shown in Figure 8, together with the objective function values of the best individual at each iteration to illustrate the optimization process. As the iterations proceed, the objective function value converges and stabilizes after approximately 20 iterations, indicating that these design variables successfully meet the design target. Additionally, the ITN topology generated by the set of variables in the best individual which satisfies the requirements for impedance matching and phase delay has been obtained, and the values of these variables are presented in

Table 4. Optimized parameters of ITN1 in Figure 8.

Width/Length (mm)	Value
$W_1/L_1$	5.04/4.11
$W_2/L_2$	5.04/19.35
$W_3/L_3$	1.20/2.16
$W_4/L_4$	5.17/5.14
$W_5/L_5$	2.27/18.10
$W_6/L_6$	1.50/16.01
$W_7/L_7$	0.30/19.39

. The phase delay variation curves of the 10th, 30th, and 50th individuals at the four operating frequencies (2.0, 2.5, 2.8, and 3.3 GHz) are shown in Figure 9, indicating that the phase delays of the selected individuals at the four target frequencies fulfill the phase delay requirements for ITN1 in the dual-mode multi-band DPA, which confirms the consistency and validity of the optimization across the population.

The designed ITN1 structure is presented in Figure 10a. Since ITN2 and ITN1 in the reciprocal-bias dual-mode multi-band DPA have a similar structure, ITN2 is designed by adding a phase compensation line after ITN1. The corresponding schematic is shown in Figure 10b.

After the impedance-and-phase constrained optimization design is completed, Figure 11 depicts the resulting phase delays of ITN1 and ITN2 at their respective design operating frequencies. When the reciprocal-bias dual-mode multi-band DPA operates in Mode I, ITN1 functions as the carrier ITN. At 2.0 and 2.8 GHz, its phase delays are $-{301}^{\circ }$ and $-{449}^{\circ }$, respectively. Meanwhile, ITN2 acts as the peaking ITN, with phase delays of $-{355}^{\circ }$ and $-{525}^{\circ }$ at 2.0 and 2.8 GHz, correspondingly. Upon swapping the gate bias, the DPA switches to Mode II. In this mode, ITN2 serves as the carrier ITN, presenting phase delays of $-{464}^{\circ }$ and $-{630}^{\circ }$ at 2.5 and 3.3 GHz, respectively. ITN1 functions as the peaking ITN, with phase delays of $-{397}^{\circ }$ and $-{540}^{\circ }$ at 2.5 and 3.3 GHz, respectively. These results are consistent with the theoretical analysis.

The optimized trajectory achieved by the optimized OMN and the optimal impedance regions at four frequencies are shown in Figure 12. The impedance at 2.0 and 2.8 GHz in Mode I, as well as at 2.5 and 3.3 GHz in Mode II, is all located within the optimum load impedance region. This confirms that the design meets the expected objectives.

3.4. Simulation Results of Dual-Mode Multi-Band DPA

The performance of the dual-mode multi-band DPA is simulated under different operating modes, and the results are presented in Figure 13. In Mode I, the designed DPA functions within the frequency bands of 1.96–2.10 and 2.75–2.86 GHz. At saturation, its drain efficiencies (DEs) are 57.0–62.5% and 52.4–57.4%, respectively. The 6 dB PBO DEs span from 51.4 to 55.9% and 52.4 to 54.0%.

In Mode II, the DPA operates within the frequency bands of 2.49–2.61 and 3.20–3.36 GHz. At saturation, the DEs reach 59.2–69.6% and 64.3–67.5%, respectively. The 6 dB PBO DEs range from 51.6 to 55.7% and 51.8 to 58.6%, respectively.

Figure 14 illustrates the simulated gain and efficiency versus output power at the center operating frequencies for both Mode I and Mode II. At saturation, the output power at the four design frequencies exceeds 43 dBm, while the 6 dB PBO efficiency is over 50%, demonstrating a satisfactory performance. In addition, the simulated load modulation trajectories at the CG plane of the devices are plotted in Figure 15. The results show that the designed DPA can achieve appropriate Doherty load modulation for both carrier and peaking amplifiers.

4. Fabrication and Measurement of Dual-Mode Multi-Band DPA

To further validate the design, the dual-mode multi-band DPA was fabricated. A photograph of the DPA is shown in Figure 16a. To evaluate its performance, the fabricated DPA was measured with continuous wave and modulated signals. The measurement was carried out across the frequency bands of 1.96–2.10 GHz and 2.75–2.86 GHz for Mode I, and 2.49–2.61 GHz and 3.20–3.36 GHz for Mode II, with the setup presented in Figure 16b. The drain bias voltages of the carrier and peaking PAs are both 28 V. The gate bias voltage of the carrier PA is −3 V, and that of the peaking PA is −6 V. For the selected transistor, the DC quiescent current ($I_{dq}$) of the carrier PA is 0.1 A.

4.1. Continuous Wave Measurement

The measured efficiency and gain versus output power of the dual-mode multi-band DPA are presented in Figure 17. The DPA maintains high efficiency in both saturation and PBO state. Figure 18 illustrates measured and simulated DE and output power versus frequency in Mode I and Mode II.

In Mode I, for the bands of 1.96–2.10 and 2.75–2.86 GHz, in the 6 dB PBO state, the DPA attains DEs of 49.4–55.7% and 49.8–51.7%, respectively. At saturation, the DEs are in the range of 55.2–62.5% and 53.7–60.0%.

In Mode II, for the bands of 2.49–2.61 and 3.20–3.36 GHz, for the 6 dB PBO state, the DPA attains DEs of 51.2% to 52.4% and 50.4% to 53.5%. At saturation, the DEs are in the range of 60.0–68.6% and 60.2–63.5%, respectively.

The experimental results are appropriately consistent with the simulation results, validating the effectiveness of the proposed design methodology.

4.2. Modulated Signal Measurement

To evaluate the performance of the DPA, an LTE signal with a PAPR of 6.5 dB and a bandwidth of 20 MHz was used for measurement. To meet the linearity requirements for wireless communication systems, digital predistortion (DPD) was applied to the DPA. The piecewise second-order dynamic deviation reduction model was used in the DPD modeling [55]. The magnitude threshold was set as 0.4 0.7 for the normalized data, while the nonlinearity order was selected as {7, 7, 7} and the memory length was set to {3, 3, 3}. Figure 19 presents the measured results of the adjacent channel leakage ratio (ACLR) before and after DPD implementation at the designed operating frequencies. As shown in the figure, the ACLR values are consistently around −50 dBc after DPD. The average output power ranges from 36 to 37 dBm, with DEs exceeding 50%.

Figure 20 illustrates the output spectra of the four design operating frequencies before and after DPD. After DPD, ACLR performance reaches approximately −50 dBc, indicating a significant improvement in the nonlinear effects of the DPA.

Table 5. Comparison with published works measured under continuous wave signal.

Ref.	Freq. (GHz)	Pmax (dBm)	Gain (dB)	DEsat (%)	DE6dB (%)
R. Kalyan [56]	1.50/2.14 & 1.85/2.55	43.2	10.0–13.0	62.0–70.0	52.0–56.0
X. Li [57]	0.73/1.65 2.67/3.57	42.5	9.0–14.0	52.7–73.1	44.6–58.9
X. A. Nghiem [58]	0.95/1.50 2.14/2.65	44.2	9.0–13.0	43.0–61.0	32.0–56.0
T.W.	2.00/2.80 & 2.50/3.30	44.1	9.5–14.7	53.7–68.6	49.4–55.7

compares the proposed DPA with the published multi-band or multi-mode DPAs measured under a continuous wave signal. The results demonstrate that the proposed DPA exhibits satisfactory performance.

5. Conclusions

This paper proposes a dual-mode multi-band DPA design method employing impedance-and-phase constrained optimization based on reciprocal gate bias. By swapping the gate bias of the two transistors, the roles of the carrier and peaking amplifiers interchange accordingly. A dual-mode multi-band DPA operating in Mode I at 1.96–2.10 GHz and 2.75–2.86 GHz, and in Mode II at 2.49–2.61 GHz and 3.20–3.36 GHz, is designed and fabricated. The measured results show that this DPA can achieve high DEs at saturation and PBO states within all the operating frequency bands, making it suitable for future wireless communication systems. Experimental results confirm that the DPA achieves high drain efficiency at both saturation and PBO levels across all bands, demonstrating strong potential for deployment in next-generation wireless communication systems.