Search Results (72)

The development of an integrated circuit faces the challenge of the physical limit of Moore’s Law. One of the most important “Beyond Moore” challenges is the scaling down of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) versus their increasing static power consumption. This is because, at room temperature, the thermal emission transportation mechanism will cause a physical limitation on subthreshold swing (SS), which is fundamentally limited to a minimum value of 60 mV/decade for MOSFETs, and accompanied by an increase in off-state leakage current with the process of scaling down. Moreover, the impacts of short-channel effects on device performance also become an increasingly severe problem with channel length scaling down. Due to the band-to-band tunneling mechanism, Tunnel Field-Effect Transistors (TFETs) can reach a far lower SS than MOSFETs. Recent research works indicated that TFETs are already becoming some of the promising candidates of conventional MOSFETs for ultra-low-power applications. This paper provides a review of some advances in materials and structures along the evolutionary process of TFETs. An in-depth discussion of both experimental works and simulation works is conducted. Furthermore, the performance of TFETs with different structures and materials is explored in detail as well, covering Si, Ge, III-V compounds and 2D materials, alongside different innovative device structures. Additionally, this work provides an outlook on the prospects of TFETs in future ultra-low-power electronics and biosensor applications. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

The surface morphology of porous source electrodes plays a significant role in the performance of vertical channel indium–gallium–zinc oxide thin-film transistors (VC-IGZO-TFTs). This study systematically investigates the properties of porous MXene-based source electrodes and their impact on VC-IGZO-TFTs fabricated with varying MXene concentrations. As the MXene concentration increases, both the sheet resistance and porosity of the electrodes decrease. VC-IGZO-TFTs based on a 3.0 mg/mL MXene concentration exhibit optimal electrical performance, with a threshold voltage (V_th) of 0.16 V, a subthreshold swing (SS) of 0.20 V/decade, and an on/off current ratio (I_on/I_off) of 4.90 × 10⁵. Meanwhile, the VC-IGZO-TFTs exhibit excellent electrical reliability and mechanical stability. This work provides a way to analyze the influence of sheet resistance and porosity on the performance of VC-IGZO-TFTs, offering a viable approach for enhancing device efficiency through porous MXene electrode engineering. Full article

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness of 4 nm. The Al₂O₃ film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10⁻⁷ A/cm² at 1 MV/cm. MoS₂ FETs incorporating this Al₂O₃ gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (V_th) of −0.96 V, a high carrier mobility (μ) of 34.85 cm²·V⁻¹·s⁻¹, and an on/off current ratio exceeding 10⁶. These results highlight the potential of Al₂O₃ in enabling low-power 2D electronic devices for post-Moore applications. Full article

Using novel SiO₂ surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µ_eff) of more than 100 cm²/V·s and 31.1 cm²/V·s at hole densities (Q_h) of 1 × 10¹¹ and 5 × 10¹² cm⁻², respectively. To further improve the on-current/off-current (I_ON/I_OFF), an ultra-thin 7 nm thick SnO nanosheet pFET shows a record-breaking I_ON/I_OFF of 6.9 × 10⁶ and remarkable µ_eff values of ~70 cm²/V·s and 20.7 cm²/V·s at Q_h of 1 × 10¹¹ cm⁻² and 5 × 10¹² cm⁻², respectively. This is the first report of an oxide semiconductor transistor achieving a hole effective mobility µ_eff that reaches 20% of that in single-crystal Si pFETs at an ultra-thin body thickness of 7 nm. In sharp contrast, the control SnO nanosheet pFET without surface passivation or UV anneal exhibits a small I_ON/I_OFF of 1.8 × 10⁴ and a µ_eff of only 6.1 cm²/V·s at 5 × 10¹² cm⁻² Q_h. The enhanced SnO pFET performance is attributed to reduced defects and improved quality in the SnO channel, as confirmed by decreased charges related to sub-threshold swing (SS) and threshold voltage (Vth) shift. Such a large improvement is further supported by the increased Sn²⁺ after passivation and UV anneal, as evidenced by X-ray photoelectron spectroscopy (XPS) analysis. The I_ON/I_OFF ratio exceeding six orders of magnitude, remarkably high hole µ_eff, and excellent two-month stability demonstrate that this pFET is a strong candidate for integration with SnON nFETs in next-generation ultra-high-definition displays and monolithic three-dimensional integrated circuits (3D ICs). Full article

To address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure. In the off-state, the SGO structure effectively suppresses GIDL by reducing the electric field intensity at the channel/drain interface while simultaneously decreasing gate capacitance to reduce static power consumption. Based on an accurate device model, a systematic investigation was conducted into the effects of varying the thickness and length of the SGO structure on TFET performance, enabling the optimization of the SGO design. The simulation results demonstrate that, compared to normal MS TFETs, the SGO MS TFET reduces the off-state GIDL current ($I_{\mathrm{off}}$) from $4.6\times {10}^{-7}$ A to $2.6\times {10}^{-11}$ A, achieving a maximum improvement of 4.22 orders of magnitude in the on-state-to-off-state current ratio ($I_{\mathrm{on}}/I_{\mathrm{off}}$) and a 28% reduction in subthreshold swing (SS). Furthermore, compared to lightly doped drain (LDD) MS TFETs, the SGO MS TFET achieves a 32% reduction in total gate capacitance and a 23% enhancement in carrier mobility at the channel/drain interface. This study demonstrates that SGO provides an effective solution for GIDL suppression. Full article

In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous. Due to increasing concerns around energy efficiency, gate density, and scalability in the semiconductor industry, there has been much interest recently in the fabrication of viable low-power energy-efficient devices. The Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET represents a cutting-edge transistor architecture designed for superior sustainability and energy efficiency, improving the overall efficiency of the system by reducing leakage and enhancing gate control; therefore, as part of the transition to a sustainable future, several semiconductor industries, including Intel, Samsung, Texas Instruments, and IBM, are using this technology. In this study, Hetero-Dielectric Single-Metal Gate-All-Around MOSFET (HD-SM-GAA MOSFET) devices and circuits were designed using Schottky source/drain contacts and tunable high-k dielectric Hf_xTi_1−xO₂ in the TCAD simulator using the following specifications: N-Channel HD-SM-GAA MOSFET (‘Device-I’) with a 5 nm radius and a 21 nm channel length alongside two P-Channel HD-SM-GAA MOSFETs (‘Device-II’ and ‘Device-III’) with radii of 5 nm and 8 nm, respectively, maintaining the same channel length. Thereafter, the inverters were implemented using these devices in the COGENDA TCAD simulator. The results demonstrated significant reductions in short-channel effects: subthreshold swing (SS) (‘Device-I’ = 61.5 mV/dec, ‘Device-II’ = 61.8 mV/dec) and drain-induced barrier lowering (DIBL) (‘Device-I’ = 8.2 mV/V, ‘Device-II’ = 8.0 mV/V) in comparison to the existing literature. Furthermore, the optimized inverters demonstrated significant improvements in noise margin values such as Noise Margin High (NM_H) and Noise Margin Low (NM_L), with Inverter-1 showing 38% and 44% enhancements and Inverter-2 showing 40% and 37% enhancements, respectively, compared to the existing literature. The results achieved illustrate the potential of using this technology (e.g., for power inverters) in embedded power control applications where energy efficiency and scalability are important, such as sustainable smart cities. Full article

This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping concentration—on the row hammer effect (RHE) in DRAM cells. The influence of adjacent and passing gates on the DRAM cell body potential was identified as a key factor in D0 and D1 failures. The tolerance for D1 and D0 failures was analyzed, defined as the threshold number of pulses required to induce a 0.6 V change in the storage node voltage (from 1.2 V to 0.6 V for a D1 failure or from 0 V to 0.6 V for a D0 failure). D1 (D0) failure tolerances with the slope from the top of the top gate (θ_angle) of 3°, the height of the TiN gate covering the fin (H_{fin_overlap}) of 12.5 nm, and the height of the fin (H_fin) of 12.5 nm are 1.26 × 10⁶ (4.8 × 10⁶), 1.14 × 10⁶ (4 × 10⁷), and 7.5 × 10⁵ (4.8 × 10⁵), respectively. Higher θ_angles and smaller fin heights generally result in higher RHE tolerances. Although decreasing the fin height reduced the RHE, it also decreased the on-current and resulted in an increase in the threshold voltage (V_T) and the subthreshold swing (SS). In addition, by increasing the substrate bottom doping concentration (P_{dop_bot}), we improve RHE tolerance twice its original level without reducing the on-current. Therefore, designing a buried channel array transistor (BCAT) structure requires careful consideration of these trade-offs, and a thorough understanding of the underlying mechanism is crucial to devising strategies that reduce RHE tolerance. The findings of this study are expected to contribute significantly to the development of next-generation DRAM architectures, enhancing stability and performance. By addressing the reliability challenges posed by advanced scaling, this study paves the way for the ongoing advancement of DRAM technology for high-density and high-performance applications. Full article

Gate dielectrics are essential components in nanoscale field-effect transistors (FETs), but they often face significant instabilities when exposed to harsh environments, such as radioactive conditions, leading to unreliable device performance. In this paper, we evaluate the performance of ultrascaled transition metal dichalcogenide (TMD) FETs equipped with vacuum gate dielectric (VGD) as a means to circumvent oxide-related instabilities. The nanodevice is computationally assessed using a quantum simulation approach based on the self-consistent solutions of the Poisson equation and the quantum transport equation under the ballistic transport regime. The performance evaluation includes analysis of the transfer characteristics, subthreshold swing, on-state and off-state currents, current ratio, and scaling limits. Simulation results demonstrate that the investigated VGD TMD FET, featuring a gate-all-around (GAA) configuration, a TMD-based channel, and a thin vacuum gate dielectric, collectively compensates for the low dielectric constant of the VGD, enabling exceptional electrostatic control. This combination ensures superior switching performance in the ultrascaled regime, achieving a high current ratio and steep subthreshold characteristics. These findings position the GAA-VGD TMD FET as a promising candidate for advanced radiation-hardened nanoelectronics. Full article

The praseodymium-doped indium zinc oxide (PrIZO) thin-film transistor (TFT) is promising for applications in flat-panel displays, due to its high carrier mobility and stability. Nevertheless, there are few studies on the mechanism of annealing on PrIZO films and the fabrication of flexible devices. In this work, we first optimized the annealing-process parameters on the glass substrate. As the annealing temperature rises, the film tends to be denser and obtains a lower surface roughness, a narrower optical-band gap and less oxygen-vacancy content. However, the μ-PCD test shows the 250 °C-annealed film obtains the least defects. And the PrIZO TFT annealed at 250 °C exhibited a desired performance with a saturation mobility (μ_sat) of 14.26 cm²·V⁻¹·s⁻¹, a subthreshold swing (SS) of 0.14 V·dec⁻¹, an interface trap density (D_it) of 3.17 × 10¹¹, an I_on/I_off ratio of 1.83 × 10⁸ and a threshold voltage (Vth) of −1.15 V. The flexible devices were prepared using the optimized parameters on the Polyimide (PI) substrate and subjected to static bending tests. After bending at a radius of 5 mm, the mobility of devices decreases slightly from 12.48 to 10.87 cm²·V⁻¹·s⁻¹, demonstrating the great potential of PrIZO for flexible displays. Full article

In active-matrix organic light-emitting diode (AMOLED) displays, conventional pixel circuits that compensate for the non-uniformity of the threshold voltage (V_T) of low-temperature polycrystalline silicon thin-film transistors (TFTs) can hardly compensate for variations in other TFT parameters, such as carrier mobility (μ₀), subthreshold swing (SS) and the various effects of parasitic capacitance. In recent high-resolution AMOLED displays, as the current required for OLED pixel driving decreases, the current error rate (CER) caused by the non-uniform TFT parameters increases. In this study, we analyzed the influence of each TFT parameter on the CER using SPICE simulation. Based on our analysis, the origin of the increased CER can be classified into two categories: the charging capability of driving TFT and the capacitive coupling effect of the switching TFT. The SS of the driving TFT and the parasitic capacitance of the switching TFT are major factors that affect the CER in terms of the charging capability and capacitive coupling effect, respectively. Our analysis results can be summarized as follows: The SS value of the driving TFT should be high, and its variation should be small to minimize the CER. The variation in the parasitic capacitance of the switching TFT possibly occurs due to long-term bias conditions, as well as process non-uniformity. Therefore, the stability of TFT should also be confirmed for the prevention of anomalous CER caused by long-term bias stress. Full article

High-k metal oxides are gradually replacing the traditional SiO₂ dielectric layer in the new generation of electronic devices. In this paper, we report the production of five-element high entropy metal oxides (HEMOs) dielectric films by solution method and analyzed the role of each metal oxide in the system by characterizing the film properties. On this basis, we found optimal combination of (AlGaTiYZr)O_x with the best dielectric properties, exhibiting a low leakage current of 1.2 × 10⁻⁸ A/cm² @1 MV/cm and a high dielectric constant, while the film’s visible transmittance is more than 90%. Based on the results of factor analysis, we increased the dielectric constant up to 52.74 by increasing the proportion of TiO₂ in the HEMOs and maintained a large optical bandgap (>5 eV). We prepared thin film transistors (TFTs) based on an (AlGaTiYZr)O_x dielectric layer and an InGaZnO_x (IGZO) active layer, and the devices exhibit a mobility of 18.2 cm²/Vs, a threshold voltage (V_th) of −0.203 V, and an subthreshold swing (SS) of 0.288 V/dec, along with a minimal hysteresis, which suggests a good prospect of applying HEMOs to TFTs. It can be seen that the HEMOs dielectric films prepared based on the solution method can combine the advantages of various high-k dielectrics to obtain better film properties. Moreover, HEMOs dielectric films have the advantages of simple processing, low-temperature preparation, and low cost, which are expected to be widely used as dielectric layers in new flexible, transparent, and high-performance electronic devices in the future. Full article

Recently, two-dimensional materials have gained significant attention due to their outstanding properties such as high charge mobility, mechanical strength, and electrical characteristics. These materials are considered one of the most promising solutions to overcome the limitations of semiconductor technology and are being utilized in various semiconductor device research. In particular, molybdenum diselenide (MoSe₂) and tungsten diselenide (WSe₂) are actively being developed for device applications due to their high electron mobility, optical properties, and electrical characteristics. In this study, we fabricated MoSe₂ and WSe₂-based junction field-effect transistors (JFET) and further deposited two-dimensional materials on the same device to fabricate and compare JFETs with a gate-all-around (GAA) structure. The research results showed that the GAA-structure JFET exhibited performance improvements in drain current, subthreshold swing (SS) transconductance (gm), and mobility, achieving enhancements ranging from a minimum of 1.2 times to a maximum of 10 times compared to conventional JFET. Full article

In this study, we aimed to propose an optimal structure for an AlGaN/InGaN/GaN/AlGaN/SiC HEMT by investigating how the breakdown voltage varies with the thickness and composition of the InGaN layer. The breakdown voltage was shown to be highly dependent on the In composition. Specifically, as the In composition increased, the breakdown voltage rapidly increased, but it exhibited saturation when the In composition exceeded 0.06. Therefore, it is desirable to maintain the In composition at or above 0.06. The variation in breakdown voltage due to thickness was relatively small compared to the variation caused by In composition. While the breakdown voltage remained nearly constant with increasing thickness, it began to decrease when the thickness exceeded 10 nm. Hence, the thickness should be kept below 10 nm. Additionally, as the In composition increased, the subthreshold swing (SS) also increased, but the drain current value was shown to increase. On the other hand, it was observed that the SS value in the transfer characteristics and the current–voltage characteristics were almost unaffected by the thickness of the InGaN layer. Full article

ZnO thin films were deposited using RF sputtering by varying the argon:oxygen gas flow rates and substrate temperatures. Structural, optical and electrical characterization of ZnO thin films were systematically carried out using X-Ray diffraction (XRD), scanning electron microscopy (SEM), UV–visible spectroscopy, X-Ray photoelectron spectroscopy (XPS) and Hall measurements. Film deposited at room temperature and annealed at 300 °C exhibited low O₂ incorporation with localized defects and a high percentage of Zn interstitials. A large crystalline size and fewer grain boundaries resulted in a high Hall mobility of 46.09 cm²/V-s Deposition at higher substrate temperatures resulted in improvement in O₂ incorporation through the annihilation of localized defects and decrease in oxygen vacancies and Zn interstitials. Urbach tails within the bandgap were identified using the absorption spectrum and compared with the % defects from XPS. Bottom-gate thin-film transistors were subsequently fabricated on a SiO₂/p-Si substrate using the combination of RF sputtering, wet etching and photolithography. Variation in the substrate temperature showed performance enhancement in terms of the leakage current, threshold voltage, sub-threshold swing and I_ON/I_OFF ratio. Thin-film transistor (TFT) devices deposited at 300 °C resulted in an O₂-rich surface through chemisorption, which led to a reduction in the leakage current of up to 10⁻¹² A and a 10-fold reduction in the sub-threshold swing (SS) from 30 V to 2.8 V. Further TFT optimization was carried out by reducing the ZnO thickness to 50 nm, which resulted in a field-effect mobility of 1.1 cm²/V-s and I_ON/I_OFF ratio of 10⁵. Full article