Search Results (67)

This work introduces an innovative approach for estimating the Single-Event Upset (SEU) cross-sections in Static Random-Access Memory (SRAM) devices, addressing challenges related to limited technological information and the complexity of Technology Computer-Aided Design (TCAD) simulations. The proposed methodology is designed to be accessible even to users without in-depth TCAD expertise, enabling a streamlined yet accurate SEU cross-section estimation. Using simplified mixed-modeling (TCAD-based 2D modeling with circuit-level SPICE simulations), this approach significantly reduces computational efforts while maintaining good correlation with experimental data. Furthermore, this study identifies key parameters that influence TCAD modeling accuracy and proposes strategies for approximating unknown parameters, enhancing the reliability of SEU cross-section predictions. Full article

With continued scaling of CMOS technology, the critical charge required for state retention in SRAM cells has decreased, leading to increased vulnerability to radiation-induced soft errors such as single-event upsets (SEUs) and single-event multi-node upsets (SEMNUs) in space environments. To address these reliability challenges, this paper proposes a 16-transistor radiation-hardened SRAM cell, EWS-16T, designed to improve resilience against soft errors. The performance of the proposed EWS-16T cell was evaluated through the 90 nm CMOS process and compared with previously reported radiation-hardened cells, including QCCS, SCCS, SAW16T, HP16T, RHSCC16T, and S8P8N. The results show that EWS-16T achieves the shortest write access time (22.11 ps) and the highest word line write trip voltage (WWTV) (279 mV) among all comparison cells. In addition, it demonstrates excellent performance in terms of critical charge tolerance (>300 fC) and low hold power consumption (53 nW). Furthermore, a comprehensive performance evaluation using the electrical quality metric (EQM) confirms that the EWS-16T cell achieves an outstanding balance among write efficiency, power consumption, and soft error resilience. These results indicate that EWS-16T is a highly promising SRAM design capable of ensuring reliable operation even in radiation-intensive space environments. Full article

Advancements in CMOS technology have significantly reduced both transistor dimensions and inter-device spacing, leading to a lower critical charge at sensitive nodes. As a result, SRAM cells used in space applications have become increasingly vulnerable to single-event upset (SEU) caused by the harsh radiation environment. To ensure reliable operation under such conditions, radiation-hardened SRAM designs are essential. In this paper, we propose a low-power read-decoupled radiation-hardened 16T (LDRH16T) SRAM cell to mitigate the effects of SEU. The proposed cell is evaluated against several state-of-the-art soft-error-tolerant SRAM designs, including QUCCE12T, WE-QUATRO, RHBD10T, SIS10T, EDP12T, SEA14T, and SAW16T. Simulations are conducted using a 90 nm CMOS process at a supply voltage of 1 V and a temperature of 27 °C. Simulation results show that LDRH16T successfully recovers its original state after injection at all sensitive nodes. Furthermore, since its storage nodes are decoupled from the bit lines during read operations, the proposed cell achieves the highest read stability among the compared designs. It also exhibits superior write ability, shorter write delay, and significantly lower hold power consumption. In addition, LDRH16T demonstrates excellent overall performance across key evaluation metrics and proves its capability for reliable operation in space environments. Full article

In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources of performance degradation even in terrestrial areas. Hence, the need to test and mitigate the effects of SEUs on FPGA-based TDCs is crucial to ensure that the design achieves reliable performance under critical conditions. The TMR SEM IP provides real-time fault injection, and dynamic SEU monitoring and correction in safety critical conditions without intervening with the functionality of the system, unlike traditional fault injection methods. This paper presents a scalable and fast fault emulation framework that tests the effects of SEUs on the configuration memory of a 5.7 ps-resolution TDC implemented on ZedBoard. The experimental results demonstrate that the standard deviation in mean bin width is 2.4964 ps for the golden TDC, but a 0.8% degradation in the deviation is observed when 3 million SEUs are injected, which corresponds to a 0.02 ps increment. Moreover, as the number of SEUs increases, the degradation in the RMS integral non-linearity (INL) of the TDC also increases, which shows 0.04 LSB (6.8%) and 0.05 LSB (8.8%) increments for 1 million and 3 million SEUs injected, respectively. The RMS differential non-linearity (DNL) of the faulty TDC with 3 million SEUs injected shows a 0.035 LSB (0.8%) increase compared to the golden TDC. Full article

Electronic equipment in space is constantly exposed to high-energy particles, which can induce Single Event Upsets (SEUs) in memory components, threatening system reliability. To address this critical challenge, we propose RHLP-18T, a radiation-hardened 18-transistor (18T) Static Random-Access Memory (SRAM) cell designed to enhance robustness against radiation-induced faults. The proposed cell integrates circuit-level Radiation-Hardened-by-Design (RHBD) techniques to mitigate both SEUs and multi-node upsets. Comprehensive simulations were conducted using 90 nm CMOS technology, benchmarking RHLP-18T against nine existing RHBD cells (RHBD14T, HPHS12T, NRHC14T, QCCS12T, RHMC12T, RHWC12T, SEA14T, SIMR-18T, and SERSC16T). Simulation results demonstrate that the proposed RHLP-18T cell exhibits superior SEU tolerance, achieving a Read Static Noise Margin (RSNM) over three times higher than the next best design. Moreover, the proposed cell achieves the lowest hold power consumption among all evaluated cells. These improvements result in the highest Figure of Merit (FOM), indicating that RHLP-18T provides an optimal trade-off between robustness and overall performance for operation in radiation-exposed environments. Full article

This paper proposes a fault-tolerant flexible manufacturing system (FMS) that features a dual-level fault tolerance mechanism at both the workcell and system levels to enhance reliability. The workcell controller was implemented on a Field Programmable Gate Array (FPGA). Reconfigurable duplication was used as the first level of fault tolerance at the workcell level. It was shown how to detect and recover from FPGA faults such as Single Event Upsets (SEUs), hard faults, and Single Event Functional Interrupts (SEFIs). The prototype of the workcell controller was successfully implemented using two Zybo Z7-20 AMD boards and an Arduino DUE. Petri Nets were used to prove that controller reliability increased by 346% after 1440 operational hours. The second level of fault tolerance was at the FMS level; the Supervisor (SUP) took over the responsibilities of any malfunctioning workcell controller. Riverbed software was used to prove that the system successfully met the end-to-end delay requirements. Finally, Matlab showed that there is a further increase in performability. Full article

Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸$Ni$ and ²⁸$Si$, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs. Full article

The digital integrated circuit (IC) design industry is continuously evolving. However, the rapid advancements in technology are accompanied by major reliability concerns. Conventional clock-based synchronous designs become exceedingly susceptible to transient errors, caused by radiation rays, power jitters, electromagnetic interferences (EMIs), and/or other noise sources, primarily due to aggressive device and voltage scaling. quasi-delay-insensitive (QDI) asynchronous (clockless) circuits demonstrate inherent robustness against such transient errors, owing to their unique architecture. However, they are not completely immune. This article presents a hardened QDI Sleep Convention Logic (SCL) asynchronous architecture, which can fully recover from radiation-induced single-event effects such as single-event upset (SEU) and single-event latch-up (SEL). Multiple benchmark circuits are designed based on the proposed architecture. The simulation results indicate that the proposed designs offer substantial energy savings per operation, dissipate substantially less power during idle phases, and have lower area footprints in comparison to designs based on an existing resilient Null Convention Logic (NCL) architecture at the cost of increased latency. In addition, a formal verification framework for the proposed architecture is also presented. The performance and scalability of the proposed verification scheme are demonstrated using several multiplier benchmark circuits of varying width. Full article

Advances in deep submicron semiconductor technology have increased the significance of studying soft errors caused by atmospheric radiation in avionics systems. Atmospheric radiation particles, such as protons and neutrons, can induce Single Event Upsets (SEUs) in sensitive electronic components, leading to system malfunctions and data corruption. Traditional reliability analysis based on older IC or LSI components may fail to account for radiation-induced effects. However, modern avionics systems equipped with state-of-the-art VLSI components are increasingly susceptible to Single Event Upsets (SEUs), potentially leading to underestimated failure rates in these advanced systems. This study introduces an integrated failure rate analysis that incorporates both the physics of failure rates resulting from aging and wear-out and soft error rates induced by atmospheric radiation. The proposed failure rate analysis of the reliability of avionics operating at altitudes of up to 18 km by combining the physics of failure rates with radiation-induced failure rates was derived using a semi-empirical SEU estimation method. Case studies using the Zynq 7000 board, sourced from AMD (San Jose, CA, USA), confirmed that the integrated failure rate analysis provides more accurate reliability predictions compared to conventional analysis. This approach is expected to improve the accuracy of safety assessments during the preliminary development stages, leading to a shortened development timeline and enhanced design quality. Full article

As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. Full article

To meet the high-reliability requirements of real-time on-orbit tasks, this paper proposes a fault-tolerant reinforcement design method for spaceborne intelligent processing algorithms based on convolutional neural networks (CNNs). This method is built on a CNN accelerator using Field-Programmable Gate Array (FPGA) technology, analyzing the impact of Single-Event Upsets (SEUs) on neural network computation. The accelerator design integrates data validation, Triple Modular Redundancy (TMR), and other techniques, optimizing a partial fault-tolerant architecture based on SEU sensitivity. This fault-tolerant architecture analyzes the hardware accelerator, parameter storage, and actual computation, employing data validation to reinforce model parameters and spatial and temporal TMR to reinforce accelerator computations. Using the ResNet18 model, fault tolerance performance tests were conducted by simulating SEUs. Compared to the prototype network, this fault-tolerant design method increases tolerance to SEU error accumulation by five times while increasing resource consumption by less than 15%, making it more suitable for spaceborne on-orbit applications than traditional fault-tolerant design approaches. Full article

The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry. When a radiation particle strikes a sensitive node of a conventional 6T SRAM cell, a single event upset (SEU) can occur, flipping in the stored data in the cell. Additionally, charge sharing between transistors can cause single-event multi-node upsets (SEMNUs), where data in multiple nodes are flipped simultaneously due to a single particle strike. Therefore, this paper proposes a radiation-hardened high stability 16T (RHHS16T) cell for space applications. The characteristics of RHHS16T are evaluated and compared with previously proposed radiation-hardened SRAM cells such as QUCCE12T, WEQUATRO, RHBD10T, RHD12T, RSP14T, RHPD14T, and RHBD14T. Simulation results for RHHS16T indicated that the proposed cell demonstrates improved performance in read stability, write access time, and write stability compared to all comparison cells. These improvements in the proposed cell are achieved with higher power consumption and a minor area penalty. Notably, isolating the storage node from the bit line during read operations and the feedback loop between nodes during write operations enables the proposed RHHS16T to achieve enhanced read stability and write stability, respectively. The proposed integrated circuit was implemented using a 90 nm CMOS process and operates at a supply voltage of 1V. Furthermore, RHHS16T provides high immunity against SEUs and SEMNUs. Through its enhanced read and write stability, it ensures reliable data retention for space applications. Full article

In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space industry. To mitigate the impacts of SEUs and SEMNUs, this paper proposes the Read Stability Improved and Low Power (RSLP16T) SRAM cell. It was confirmed that in SEU-induced simulations, all nodes of the RSLP16T could be restored with a charge amount of less than 100 fC. Additionally, it was verified that a similar level of restoration was possible for SEMNUs occurring in pair of storage nodes. The proposed cell achieves a high level of read stability due to a high pull-down cell ratio (current ratio, CR) at the storage nodes and the fact that only a pair of nodes is in contact with the bit lines during read operations. Because all node paths use a stacking structure for internal transistor configuration and a relatively higher number of cells are composed of PMOS, it consumes the least hold power. While these improvements come at the cost of slightly increased delay time and area, performance evaluation revealed that the equivalent quality metric (EQM) was the highest, indicating that the benefits outweigh the drawbacks. The proposed integrated circuit is implemented in the 90 nm CMOS process and operated on 1 V supply voltage. Full article

Exposure to space radiation substantially degrades satellite systems, provoking severe partial or, in some extreme cases, total failures. Electrostatic discharges (ESD), single event latch-up (SEL), and single event upsets (SEU) are among the most frequent causes of those reported satellite anomalies. The impact of space radiation dose on satellite equipment has been studied in-depth. This study conducts a statistical analysis to explore the relationships between low-Earth orbit (LEO) and geostationary orbit (GEO) satellite anomalies and particle concentrations, solar and geomagnetic activity in the period 2010–2022. Through a monthly and daily timescale analysis, the present work explores the temporal response of space disturbances on satellite systems and the periods when satellites are vulnerable to those disturbances. Full article

The exposure of spaceborne devices to high-energy charged particles in space results in the occurrence of both a total ionizing dose (TID) and the single-event effect (SEE). These phenomena present significant challenges for the reliable operation of spacecraft and satellites. The rapid advancement of semiconductor fabrication processes and the continuous reduction in device feature size have led to an increase in the significance of the synergistic effects of TID and SEE in static random access memory (SRAM). In order to elucidate the involved physical mechanisms, the synergistic effects of TID and single-event upset (SEU) in a new kind of 130 nm 7T silicon-on-insulator (SOI) SRAM were investigated by means of cobalt-60 gamma-ray and heavy ion irradiation experiments. The findings demonstrate that 7T SOI SRAM is capable of maintaining normal reading and writing functionality when subjected to TID irradiation at a total dose of up to 750 krad(Si). In general, the TID was observed to reduce the SEU cross-section of the 7T SOI SRAM. However, the extent of this reduction was influenced by the heavy ion LET value and the specific writing data pattern employed. Based on the available evidence, it can be proposed that TID preirradiation represents a promising avenue for enhancing the resilience of 7T SOI SRAMs to SEU. Full article