A Radiation-Hardened Low-Power SRAM with Enhanced Write Capability for Space Applications

With continued scaling of CMOS technology, the critical charge required for state retention in SRAM cells has decreased, leading to increased vulnerability to radiation-induced soft errors such as single-event upsets (SEUs) and single-event multi-node upsets (SEMNUs) in space environments. To address these reliability challenges, this paper proposes a 16-transistor radiation-hardened SRAM cell, EWS-16T, designed to improve resilience against soft errors. The performance of the proposed EWS-16T cell was evaluated through the 90 nm CMOS process and compared with previously reported radiation-hardened cells, including QCCS, SCCS, SAW16T, HP16T, RHSCC16T, and S8P8N. The results show that EWS-16T achieves the shortest write access time (22.11 ps) and the highest word line write trip voltage (WWTV) (279 mV) among all comparison cells. In addition, it demonstrates excellent performance in terms of critical charge tolerance (>300 fC) and low hold power consumption (53 nW). Furthermore, a comprehensive performance evaluation using the electrical quality metric (EQM) confirms that the EWS-16T cell achieves an outstanding balance among write efficiency, power consumption, and soft error resilience. These results indicate that EWS-16T is a highly promising SRAM design capable of ensuring reliable operation even in radiation-intensive space environments.