Search Results (43)

Memristors, as novel one-port electronic elements, have very good memory and commutating properties, insignificant power consumption, and a good compatibility to present CMOS integrated chips. They are applicable in neural networks, memory arrays, and various electronic devices. This paper proposes a simple LTSPICE model of an adapted activation function and a neuron built on memristors. In the neuron, synaptic bonds are implemented by single memristors, allowing a decreased circuit complexity. The summing and scaling schemes are based on op-amps and memristors. The applied modified tangent-sigmoidal activation function is implemented with MOS transistors and memristors. Analyses and simulations are conducted using a simple and high-rate operating memristor model with parasitic parameters—resistance, inductance, capacitance, and small-signal DC components. Their influence on the normal operation of the memristors in the neuron is analyzed, paying attention to their usage and adjustment. The proposed memristor-based artificial neuron is analyzed in MATLAB–Simulink and LTSPICE simulators. A comparison between the derived results confirms the correct operation of the proposed memristor neuron. The generation and analyses of the suggested memristor-based neuron is a significant and promising step for the design and engineering of high-complexity neural networks and their realization in ultra-high-density integrated neural circuits and chips. Full article

The integration of AI-driven optimization into Electronic Design Automation (EDA) enables smarter and more adaptive circuit design, where symmetry and asymmetry play key roles in balancing performance, robustness, and manufacturability. This work presents a model-driven optimization methodology for sizing low-phase-noise LC voltage-controlled oscillators (VCOs) at 5 GHz, targeting Wi-Fi, 5G, and automotive radar applications. The approach uses the EKV transistor model for analytical CMOS device characterization and applies a diverse set of metaheuristic algorithms for both single-objective (phase noise minimization) and multi-objective (joint phase noise and power) optimization. A central focus is on how symmetry—embedded in the complementary cross-coupled LC-VCO topology—and asymmetry—introduced by parasitics, mismatch, and layout constraints—affect optimization outcomes. The methodology implicitly captures these effects during simulation-based optimization, enabling design-space exploration that is both symmetry-aware and robust to unavoidable asymmetries. Implemented in CMOS 180 nm technology, the approach delivers designs with improved phase noise and power efficiency while ensuring manufacturability. Yield analysis confirms that integrating symmetry considerations into metaheuristic-based optimization enhances performance predictability and resilience to process variations, offering a scalable, AI-aligned solution for high-performance analog circuit design within EDA workflows. Full article

Through atomic-scale characterization of a single cobalt atom anchored in a pyridinic N₃ vacancy of graphene (Co-N₃-gra), this study computationally explores three interconnected functionalities mediated by cobalt’s electronic configuration. Quantum-confined molecular prototypes extend prior bulk models, achieving a competitive catalytic activity for CO oxidation via Langmuir–Hinshelwood pathways with a 0.85 eV barrier. These molecular prototypes’ discrete energy states facilitate single-electron transistor operation, enabling sensitive detection of NO, NO₂, SO₂, and CO₂ through adsorption-induced conductance modulation. When applied to lithium–sulfur batteries using periodic Co-N₃-gra, cobalt sites enhance polysulfide conversion kinetics and suppress the shuttle effect, with the Li₂S₂→Li₂S step identified as the rate-limiting process. Density functional simulations provide atomic-scale physicochemical characterization of Co-N₃-gra, revealing how defect engineering in 2D materials modulates electronic structures for multifunctional applications. Full article

This paper addresses the complex behavior of Single-Electron Bipolar Avalanche Transistors (SEBATs) through a comprehensive modeling approach. TCAD simulations were used to analyze the behavior of the device during avalanche pulses triggered by electron injection. The simulations consider the avalanche process and charge flow and include the parasitic capacitances and resistances. A SPICE model is proposed using parameters extracted from the TCAD simulations. Both TCAD and SPICE simulations are validated against experimental results obtained on 150 nm CMOS devices and are employed to provide a clear understanding of the phenomena observed experimentally during SEBAT operation. The impact of parasitic elements on device operation is studied using simulations. This work enables the optimization of SEBAT devices and their integration in circuits for better signal-to-noise ratios, efficiency, and potential applications in sensing and digitizing low-level signals. Full article

Colloidal quantum dots (QDs) and graphene hybrids have emerged as promising platforms for optoelectronic and biosensing applications due to their unique photophysical and electronic properties. This study investigates the fundamental mechanism underlying the photoluminescence (PL) quenching and recovery in graphene–QD hybrid systems using single-layer graphene field-effect transistors (SLG-FETs) and time-resolved photoluminescence (TRPL) spectroscopy. We demonstrate that PL quenching and its recovery are primarily driven by charge transfer, as evidenced by an unchanged fluorescence lifetime upon quenching. Density functional theory calculations reveal a significant charge redistribution at the graphene–QD interface, corroborating experimental observations. We also provide a simple analytical quantum mechanical model to differentiate charge transfer-induced PL quenching from resonance energy transfer. Furthermore, we leverage the charge transfer mechanism for ultrasensitive biosensing to detect biomarkers such as immunoglobulin G (IgG) at femtomolar concentrations. The sensor’s electrical response, characterized by systematic shifts in the Dirac point of SLG-FETs, confirms the role of analyte-induced charge modulation in PL recovery. Our findings provide a fundamental framework for designing next-generation graphene-based biosensors with exceptional sensitivity and specificity. Full article

The article presents basic information about the induction heating of gears, which are widely used in various industries. This article presents the methodology and results of a coupled FEM simulation of a circuit model for a power electronics converter connected to an inductor-charged heating system. The induction heating of gears was performed using a high-frequency inverter with SiC MOSFET transistors. A prototype inverter was built using a full-bridge structure with a series-parallel resonant circuit. The operating frequency was 350 kHz, the output power of the inverter was 3.5 kW, and the drain efficiency was equal to 96%. Coupled simulation was performed for a charge in the form of a gear made of 42CrMo4 steel (material parameters are provided in the article) for two types of heating: with and without a magnetic field concentrator. In addition, the article presents the results of co-simulation studies in the following form: a distribution of magnetic induction in the gear, energy density in the gear, the characteristics of energy density in a single tooth on the 8 mm length and the temperature of the tooth tip for two types of induction heating. Full article

This paper presents a new small-signal model for double-channel (DC)–high-electron-mobility transistors, developed through an analysis of the unique coupling effects between channels in devices. Unlike conventional single-channel HEMTs, where electrons only transport laterally in the channel, DC-HEMTs exhibit additional vertical transport between the two channels along the material direction. This double-channel coupling effect significantly limits the applicability of traditional small-signal models to DC-HEMTs. Firstly, the coupling effect between the two channels is characterized by introducing the double-channel coupling sub-model, which consists of R_GaN, R_AlN, and C_AlN. At the same time, by introducing parameters gm_{_upper} and gm_{_lower}, the new model can accurately characterize the properties of double channels. Secondly, initial values for R_GaN, R_AlN, and C_AlN are calculated based on the device’s physical structure and material properties. Similarly, initial values for gm_{_upper} and gm_{_lower} are derived from the device’s DC measurement and TCAD simulation results. Furthermore, a comprehensive parameter extraction method enables the optimized extraction of intrinsic parameters, completing the model’s construction. Finally, validation of the model’s fitting reveals a significantly reduced error compared to traditional small-signal models. This enhanced accuracy not only verifies the precise representation of the device’s physical characteristics but also demonstrates the model’s effectiveness. Full article

A derivation of a tight-binding model from Schrödinger formalism for various topologies of position-based semiconductor qubits is presented in the case of static and time-dependent electric fields. The simplistic tight-binding model enables the description of single-electron devices at a large integration scale. The case of two electrostatically Wannier qubits (also known as position-based qubits) in a Schrödinger model is presented with omission of spin degrees of freedom. The concept of programmable quantum matter can be implemented in the chain of coupled semiconductor quantum dots. Highly integrated and developed cryogenic CMOS nanostructures can be mapped to coupled quantum dots, the connectivity of which can be controlled by a voltage applied across the transistor gates as well as using an external magnetic field. Using the anti-correlation principle arising from the Coulomb repulsion interaction between electrons, one can implement classical and quantum inverters (Classical/Quantum Swap Gate) and many other logical gates. The anti-correlation will be weakened due to the fact that the quantumness of the physical process brings about the coexistence of correlation and anti-correlation at the same time. One of the central results presented in this work relies on the appearance of dissipation-like processes and effective potential renormalization building effective barriers in both semiconductors and in superconductors between not bended nanowire regions both in classical and in quantum regimes. The presence of non-straight wire regions is also expressed by the geometrical dissipative quantum Aharonov–Bohm effect in superconductors/semiconductors when one obtains a complex value vector potential-like field. The existence of a Coulomb interaction provides a base for the physical description of an electrostatic Q-Swap gate with any topology using open-loop nanowires, with programmable functionality. We observe strong localization of the wavepacket due to nanowire bending. Therefore, it is not always necessary to build a barrier between two nanowires to obtain two quantum dot systems. On the other hand, the results can be mapped to the problem of an electron in curved space, so they can be expressed with a programmable position-dependent metric embedded in Schrödinger’s equation. The semiconductor quantum dot system is capable of mimicking curved space, providing a bridge between fundamental and applied science in the implementation of single-electron devices. Full article

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS₂ layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS₂, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT’s advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. Full article

In this paper, simulation modeling was carried out using Sentaurus Technology Computer-Aided Design. Two types of high electron mobility transistors (HEMT), an AlGaN/GaN/AlGaN double heterojunction and AlGaN/GaN single heterojunction, were designed and compared. The breakdown characteristics and damage mechanisms of the two devices under the injection of high-power microwaves (HPM) were studied. The variation in current density and peak temperature inside the device was analyzed. The effect of Al components at different layers of the device on the breakdown of HEMTs is discussed. The effect and law of the power damage threshold versus pulse width when the device was subjected to HPM signals was verified. It was shown that the GaN HEMT was prone to thermal breakdown below the gate, near the carrier channels. A moderate increase in the Al component can effectively increased the breakdown voltage of the device. Compared with the single heterojunction, the double heterojunction HEMT devices were more sensitive to Al components. The high domain-limiting characteristics effectively inhibited the overflow of channel electrons into the buffer layer, which in turn regulated the current density inside the device and improved the temperature distribution. The leakage current was reduced and the device switching characteristics and breakdown voltage were improved. Moreover, the double heterojunction device had little effect on HPM power damage and high damage resistance. Therefore, a theoretical foundation is proposed in this paper, indicating that double heterojunction devices are more stable compared to single heterojunction devices and are more suitable for applications in aviation equipment operating in high-frequency and high-voltage environments. In addition, double heterojunction GaN devices have higher radiation resistance than SiC devices of the same generation. Full article

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications. Full article

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO₂) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown ($Q_{BD}$) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO₂ grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO₂ grown on SiC and used to deduce the $Q_{BD}$ model of the device under test (DUT). Compared with the $Q_{BD}$ obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs. Full article

The amazing development of transistor technology has been the main driving force behind modern electronics. Over time, this process has slowed down introducing performance bottlenecks in data-intensive applications. A main cause is the classical von Neumann architecture, which entails constant data exchanges between processing units and data memory, wasting time and power. As a possible alternative, the Beyond von Neumann approach is now rapidly spreading. Although architectures following this paradigm vary a lot in layout and functioning, they all share the same principle: bringing computing elements as near as possible to memory while inserting customized processing elements, able to elaborate more data. Thus, power and time are saved through parallel execution and usage of processing components with local memory elements, optimized for running data-intensive algorithms. Here, a new memory-mapped co-processor (MeMPA) is presented to boost systems performance. MeMPA relies on a programmable matrix of fully interconnected processing blocks, each provided with memory elements, following the Multiple-Single Instruction Multiple Data model. Specifically, MeMPA can perform up to three different instructions, each on different data blocks, concurrently. Hence, MeMPA efficiently processes data-crunching algorithms, achieving energy and time savings up to 81.2% and 68.9%, respectively, compared with a RISC-V-based system. Full article

The ambipolar conduction property of graphene field-effect transistors (GFETs) and the inherent square-like dependence of the drain current on the gate voltage, enable the development of single-device architectures for analog nonlinear radiofrequency (RF) circuits. The use of GFETs in novel RF component topologies allows leveraging graphene’s attractive thermal and mechanical properties to improve the miniaturization and weight reduction of electronic components. These features are specifically appealing for integrated sensing, modulation, and transmission systems. However, given the innovative nature of emerging graphene-based technology, a complete performance analysis of any novel electronic component is essential for customizing the operating conditions accordingly. This paper presents a comprehensive circuital analysis of a GFET-based frequency doubler, exploiting a compact model for GFET circuit simulation to assess the device’s performance parameters, including power conversion gain bandwidth and saturation. The performed analysis proposes to support the design of GFET-based harmonic transponders, offering integrated sensing and signal manipulation capabilities. Full article

Flat panel displays are electronic displays that are thin and lightweight, making them ideal for use in a wide range of applications, from televisions and computer monitors to mobile devices and digital signage. The Thin-Film Transistor (TFT) layer is responsible for controlling the amount of light that passes through each pixel and is located behind the liquid crystal layer, enabling precise image control and high-quality display. As one of the important parameters to evaluate the display performance, the faster response time provides more frames in a second, which benefits many high-end applications, such as applications for playing games and watching movies. To further improve the response time, the single-pixel charging efficiency is investigated in this paper by optimizing the TFT dimensions in gate driver circuits in active-matrix liquid crystal displays. The accurate circuit simulation model is developed to minimize the signal’s fall time ($T_f$) by optimizing the TFT width-to-length ratio. Our results show that using a driving TFT width of 6790 $\mathsf{\mu }\mathrm{m}$ and a reset TFT width of 640 $\mathsf{\mu }\mathrm{m}$ resulted in a minimum $T_f$ of 2.6572 $\mathsf{\mu }\mathrm{s}$, corresponding to a maximum pixel charging ratio of 90.61275%. These findings demonstrate the effectiveness of our optimization strategy in enhancing pixel charging efficiency and improving display performance. Full article