Search Results (52)

Due to the Von Neumann bottleneck of traditional CMOS computing, there is an urgent need to develop in-memory logic devices with low power consumption. In this work, we demonstrate ferroelectric diode devices based on the TiN/Hf_0.5Zr_0.5O₂/HfO₂/TiN structure, implementing 16 Boolean logic operations through single-step or multi-step (2–3 steps) cascade and achieving attojoule-level one-bit full-adder computation. The TiN/Hf_0.5Zr_0.5O₂/HfO₂/TiN ferroelectric diode exhibits non-destructive readout and bidirectional rectification characteristics, with the conduction mechanism following Schottky emission behavior in the on-state. Based on its bidirectional rectification characteristics, we designed and simulated the circuit scheme of 16 Boolean logic and one-bit full-adder through cascaded operations. Both the input and output logic values are represented in the form of resistance, without the need for additional form conversion circuits. The state writing is performed by pulse-controlled polarization flipping, and the state reading is non-destructive. The logic circuits in this work demonstrate superior performance with ultralow computing power consumption in simulation. This breakthrough establishes a foundation for developing energy-efficient and scalable in-memory computing systems. Full article

In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D voltage plane for aging simulation of SRAM circuits. According to the physical mechanism of failure, based on the reaction–diffusion and hot carrier energy-driven theory, revised degradation models of threshold voltage shift (∆Vth) for the NBTI and HCD are established, respectively, with explicit expressions for gate voltage (V_G)/drain voltage (V_D). An NBTI/HCD coupling model is built on the 2-D {V_G, V_D} voltage plane with a weighting factor in the form of V_G and V_D power law. The model also takes into account the AC effect and long-term saturation behavior. The predicted ∆Vth under various stress conditions shows an average relative error of 11.6% with experimental data across the entire bias space. SRAM circuit simulation shows that the read static noise margin (RSNM) and write static noise margin (WSNM) have a maximum absolute error of 4.2% and 3.1%, respectively. This research provides a valuable reference for the reliability simulation of nanoscale integrated circuits. Full article

Astrocytes play a pivotal role in shaping synaptic function and in learning, memory, and emotion. Recent studies show that perisynaptic astrocytic processes form structured interactions with pre- and postsynaptic elements, which extends synaptic diversity beyond neuron–neuron connections. Accumulating evidence indicates that astrocytic Ca²⁺ signaling, gliotransmission, and local translation modulate synaptic efficacy and contribute to the formation and stabilization of memory traces. It is therefore essential to define how astrocytic microdomains, multisynaptic leaflet domains, and network-level ensembles cooperate to regulate circuit computation across space and time. Advances in super-resolution and volumetric in vivo imaging and spatial transcriptomics now enable detailed, cell-type- and compartment-specific analysis of astrocyte–synapse interactions in vivo. In this review, we highlight these approaches and synthesize classical and emerging mechanisms by which astrocytes read neuronal activity, write to synapses, and coordinate network states. We also discuss theoretical frameworks such as neuron–astrocyte associative memory models that formalize astrocytic calcium states as distributed substrates for storage and control. This integrated view provides new insight into the multicellular logic of memory and suggests paths toward understanding and treating neurological and psychiatric disorders. Full article

The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed PIM design performs Boolean operations directly within the 2T DRAM array, thereby minimizing data movement between the CPU and DRAM and effectively alleviating the bottleneck. The 2T DRAM array was implemented using the mixed-mode simulation capability of SILVACO TCAD, and its read, write, and hold operations were successfully verified. Building on this foundation, OR and AND logic operations were realized by modulating the gate voltages of MOSFETs within the 2T DRAM array. To enable XNOR functionality, an auxiliary circuit consisting of three additional MOSFETs was integrated. Furthermore, as the ultimate goal of PIM is to enable memory to perform computational tasks, support for MAC operations becomes essential. To facilitate this, we designed a refresh circuit capable of maintaining multi-state data, which is critical for MAC operations. This circuit, also composed of three MOSFETs, functions as a key component for multi-state data retention within the 2T DRAM array. In summary, we demonstrate the implementation of Boolean logic operations using the 2T DRAM array and a three-MOSFET auxiliary circuit and propose a compact refresh circuit to support MAC operations, advancing the potential of PIM architectures. Full article

With continued CMOS scaling, transistor miniaturization has significantly raised SRAM integration density while lowering the critical charge (Qc), increasing cell vulnerability to spaceborne high-energy particles. Single-event upset (SEU) and especially single-event multiple node upsets (SEMNU) due to charge sharing present major reliability challenges. To overcome these issues, this study introduces a radiation-hardened 20T SRAM cell with read/write optimization (RWO-20T) designed for space applications. Benchmarking against hardened cells RH14T, RHSCC16T, S8P8N16T, and CC18T reveals that RWO-20T delivers superior read static noise margin (RSNM), increased word-line write trip voltage (WWTV), and faster read and write access times. Although the higher transistor count incurs some area overhead and slightly lowers the hold static noise margin (HSNM), RWO-20T achieves improved recovery rates for dual-node upsets (DNU) and triple-node upsets (TNU) under SEMNU conditions. The circuits were simulated in a 90 nm CMOS process and operated at 1 V. Full article

Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability Function (VF) derived from Verilog fault injection. This framework guides targeted Engineering Change Orders (ECOs), such as clock-net remapping, re-routing, and the selective insertion of SET filters, within a reproducible open-source flow (Yosys, OpenROAD, OpenSTA). A new analytical Soft Error Rate (SER) model for clock trees is also proposed, which decomposes contributions from the root, intermediate levels, and leaves, and is calibrated by SPICE-measured propagation probabilities, area, and particle flux. When coupled with throughput, this model yields a frequency-aware system-level Bit Error Rate (${BER}_{sys}$). The methodology was validated on a First-In First-Out (FIFO) memory, demonstrating a significant vulnerability reduction of approximately 3.35× in READ mode and 2.67× in WRITE mode. Frequency sweeps show monotonic decreases in both clock-tree vulnerability and ${BER}_{sys}$ at higher clock frequencies, a trend attributed to temporal masking and throughput effects. Cross-node SPICE characterization between 65 nm and 28 nm reveals a technology-dependent effect: for the same injected charge, the 28 nm process produces a shorter root-level pulse, which lowers the propagation probability relative to 65 nm and shifts the optimal clock-tree partition. These findings underscore the framework’s key innovations: a technology-independent, early-stage VF for ranking critical clock nets; a clock-tree SER model calibrated by measured propagation probabilities; an ECO loop that converts VF insights into concrete hardening actions; and a fully reproducible open-source implementation. The paper’s scope is architectural and pre-layout, with extensions to broader circuit classes and a full electrical analysis outlined for future work. Full article

Introduction: Learning disabilities (LD) compromise academic achievement in approximately 5–10% of school-aged children, yet the neurophysiological signatures that could facilitate earlier detection or stratification remain poorly defined. Resting-state electroencephalography (rs-EEG) offers millisecond resolution and is cost-effective, but its findings have never been synthesized systematically across pediatric LD cohorts. Methods: Following a PROSPERO-registered protocol (CRD420251087821) and adhering to PRISMA 2020 guidelines, we searched PubMed, Embase, Web of Science, Scopus, and PsycINFO through 31 March 2025 for peer-reviewed studies that recorded eyes-open or eyes-closed rs-EEG using ≥ 4 scalp electrodes in children (≤18 years) formally diagnosed with LD, and compared the results with typically developing peers or normative databases. Four reviewers independently screened titles and abstracts, extracted data, and assessed the risk of bias using ROBINS-I. Results: Seventeen studies (704 children with LD; 620 controls) met the inclusion criteria. The overall risk of bias was moderate, primarily due to small clinic-based samples and inconsistent control for confounding variables. Three consistent electrophysiological patterns emerged: (i) a 20–60% increase in delta/theta power over mesial-frontal, fronto-central and left peri-Sylvian cortices, resulting in markedly elevated θ/α and θ/β ratios; (ii) blunting or anterior displacement of the posterior alpha rhythm, particularly in language-critical temporo-parietal regions; and (iii) developmentally immature connectivity, characterized by widespread slow-band hypercoherence alongside hypo-connected upper-alpha networks linking left-hemisphere language hubs to posterior sensory areas. These abnormalities were correlated with reading, writing, and IQ scores and, in two longitudinal cohorts, they partially normalized in parallel with academic improvement. Furthermore, a link between reduced posterior/overall alpha and neuroinflammation has been found. Conclusions: Rs-EEG reveals a robust yet heterogeneous electrophysiological profile of pediatric LD, supporting a hybrid model that combines maturational delay with persistent circuit-level atypicalities in some children. While current evidence suggests that rs-EEG features show promise as potential biomarkers for LD detection and subtyping, these findings remain preliminary. Definitive clinical translation will require multi-site, dense-array longitudinal studies employing harmonized pipelines, integration with MRI and genetics, and the inclusion of EEG metrics in intervention trials. Full article

With advancements in remote sensing technology and very-large-scale integration (VLSI) circuit technology, the Earth observation capabilities of spaceborne synthetic aperture radar (SAR) have continuously improved, leading to significantly increased performance demands for on-board SAR real-time imaging processors. Currently, the low data access efficiency of traditional direct memory access (DMA) engines remains a critical technical bottleneck limiting the real-time processing performance of SAR imaging systems. To address this limitation, this paper proposes a dedicated instruction set for spaceborne SAR data transfer control, leveraging the memory access characteristics of DDR4 SDRAM and common data read/write address jump patterns during on-board SAR real-time imaging processing. This instruction set can significantly reduce the number of instructions required in DMA engine data access operations and optimize data access logic patterns. While effectively reducing memory resource usage, it also substantially enhances the data access efficiency of DMA engines. Based on the proposed dedicated instruction set, we designed a DMA engine optimized for efficient data access in on-board SAR real-time imaging processing scenarios. Module-level performance tests were conducted on this engine, and full-process imaging experiments were performed using an FPGA-based SAR imaging system. Experimental results demonstrate that, under spaceborne SAR imaging processing conditions, the proposed DMA engine achieves a receive data bandwidth of 2.385 GB/s and a transmit data bandwidth of 2.649 GB/s at a 200 MHz clock frequency, indicating excellent memory access bandwidth and efficiency. Furthermore, tests show that the complete SAR imaging system incorporating this DMA engine processes a 16 k × 16 k SAR image using the Chirp Scaling (CS) algorithm in 1.2325 s, representing a significant improvement in timeliness compared to existing solutions. Full article

In space, high-energy particle radiation poses a serious threat to the data stability and reliability of SRAM. Existing radiation-tolerant techniques, such as Triple Modular Redundancy (TMR) and Error Correction Code (ECC), have disadvantages such as large area, high power consumption, and additional delay, making them unsuitable for small satellite systems. To overcome these limitations, this paper proposes a 16-transistor-based radiation-tolerant SRAM cell, WRTU-16T, which applies a read-decoupled structure and a charge-sharing suppression mechanism. The proposed structure effectively isolates the storage node from external disturbances and improves the recovery capability for single-event inversion (SEU) and multiple-node inversion (SEMNU) by reducing charge loss. WRTU-16T shows superior performance in terms of write delay, charge recovery capability (Qc), hold power, and word line write threshold voltage (WWTV) compared to existing radiation-tolerant SRAM designs. The integrated circuit is implemented using a 90 nm CMOS process and has an operating voltage of 1V. Full article

As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. Full article

Reconfigurable processor-based acceleration of deep convolutional neural network (DCNN) algorithms has emerged as a widely adopted technique, with particular attention on sparse neural network acceleration as an active research area. However, many computing devices that claim high computational power still struggle to execute neural network algorithms with optimal efficiency, low latency, and minimal power consumption. Consequently, there remains significant potential for further exploration into improving the efficiency, latency, and power consumption of neural network accelerators across diverse computational scenarios. This paper investigates three key techniques for hardware acceleration of sparse neural networks. The main contributions are as follows: (1) Most neural network inference tasks are typically executed on general-purpose computing devices, which often fail to deliver high energy efficiency and are not well-suited for accelerating sparse convolutional models. In this work, we propose a specialized computational circuit for the convolutional operations of sparse neural networks. This circuit is designed to detect and eliminate the computational effort associated with zero values in the sparse convolutional kernels, thereby enhancing energy efficiency. (2) The data access patterns in convolutional neural networks introduce significant pressure on the high-latency off-chip memory access process. Due to issues such as data discontinuity, the data reading unit often fails to fully exploit the available bandwidth during off-chip read and write operations. In this paper, we analyze bandwidth utilization in the context of convolutional accelerator data handling and propose a strategy to improve off-chip access efficiency. Specifically, we leverage a compiler optimization plugin developed for Vitis HLS, which automatically identifies and optimizes on-chip bandwidth utilization. (3) In coefficient-based accelerators, the synchronous operation of individual computational units can significantly hinder efficiency. Previous approaches have achieved asynchronous convolution by designing separate memory units for each computational unit; however, this method consumes a substantial amount of on-chip memory resources. To address this issue, we propose a shared feature map cache design for asynchronous convolution in the accelerators presented in this paper. This design resolves address access conflicts when multiple computational units concurrently access a set of caches by utilizing a hash-based address indexing algorithm. Moreover, the shared cache architecture reduces data redundancy and conserves on-chip resources. Using the optimized accelerator, we successfully executed ResNet50 inference on an Intel Arria 10 1150GX FPGA, achieving a throughput of 497 GOPS, or an equivalent computational power of 1579 GOPS, with a power consumption of only 22 watts. Full article

The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry. When a radiation particle strikes a sensitive node of a conventional 6T SRAM cell, a single event upset (SEU) can occur, flipping in the stored data in the cell. Additionally, charge sharing between transistors can cause single-event multi-node upsets (SEMNUs), where data in multiple nodes are flipped simultaneously due to a single particle strike. Therefore, this paper proposes a radiation-hardened high stability 16T (RHHS16T) cell for space applications. The characteristics of RHHS16T are evaluated and compared with previously proposed radiation-hardened SRAM cells such as QUCCE12T, WEQUATRO, RHBD10T, RHD12T, RSP14T, RHPD14T, and RHBD14T. Simulation results for RHHS16T indicated that the proposed cell demonstrates improved performance in read stability, write access time, and write stability compared to all comparison cells. These improvements in the proposed cell are achieved with higher power consumption and a minor area penalty. Notably, isolating the storage node from the bit line during read operations and the feedback loop between nodes during write operations enables the proposed RHHS16T to achieve enhanced read stability and write stability, respectively. The proposed integrated circuit was implemented using a 90 nm CMOS process and operates at a supply voltage of 1V. Furthermore, RHHS16T provides high immunity against SEUs and SEMNUs. Through its enhanced read and write stability, it ensures reliable data retention for space applications. Full article

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications. Full article

Lithium niobate (LiNbO₃) single-crystal nanodevices featuring elevated readout domain wall currents exhibit significant potential for integrated circuits in memory computing applications. Nevertheless, challenges stem from suboptimal electrode–LiNbO₃ single crystal contact characteristics, which impact the stability of high currents within these devices. In this work, we concentrate on augmenting the domain wall current by refining the fabrication processes of domain wall random access memory (DWRAM). Each LiNbO₃ domain wall nanodevice was fabricated using a self-aligned process. Device performance was significantly enhanced by introducing a 10 nm interlayer between the LiNbO₃ and Cu electrodes. A comparative analysis of electrical properties was conducted on devices with interlayers made of chromium (Cr) and titanium (Ti), as well as devices without interlayers. After the introduction of the Ti interlayer, the device’s coercive voltage demonstrated an 82% reduction, while the current density showed a remarkable 94-fold increase. A 100 nm sized device with the Ti interlayer underwent positive down–negative up pulse testing, demonstrating a writing time of 82 ns at 8 V and an erasing time of 12 μs at −9 V. These operating speeds are significantly faster than those of devices without interlayers. Moreover, the enhanced devices exhibited symmetrical domain switching hysteresis loops with retention times exceeding 10⁶ s. Notably, the coercive voltage (V_c) dispersion remained narrow after more than 1000 switching cycles. At an elevated temperature of 400 K, the device’s on/off ratio was maintained at 10⁵. The device’s embedded selector demonstrated an ultrahigh selectivity (>10⁶) across various reading voltages. These results underscore the viability of high-density nanoscale integration of ferroelectric domain wall memory. Full article

Spintronics, utilizing both the charge and spin of electrons, benefits from the nonvolatility, low switching energy, and collective behavior of magnetization. These properties allow the development of magnetoresistive random access memories, with magnetic tunnel junctions (MTJs) playing a central role. Various spin logic concepts are also extensively explored. Among these, spin logic devices based on the motion of magnetic domain walls (DWs) enable the implementation of compact and energy-efficient logic circuits. In these devices, DW motion within a magnetic track enables spin information processing, while MTJs at the input and output serve as electrical writing and reading elements. DW logic holds promise for simplifying logic circuit complexity by performing multiple functions within a single device. Nevertheless, the demonstration of DW logic circuits with electrical writing and reading at the nanoscale is still needed to unveil their practical application potential. In this review, we discuss material advancements for high-speed DW motion, progress in DW logic devices, groundbreaking demonstrations of current-driven DW logic, and its potential for practical applications. Additionally, we discuss alternative approaches for current-free information propagation, along with challenges and prospects for the development of DW logic. Full article