Search Results (25)

Next-generation smart sensing devices necessitate on-chip integration of power-efficient reference circuits. The latters are required to provide other circuit blocks with highly reliable bias signals, even in the presence of temperature shifts and supply voltage disturbances, while draining a small fraction of the overall power budget. In particular, it is especially challenging to design current references with enhanced robustness and efficiency; hence, thorough exploration of novel architectures and design approaches is needed for this type of circuits. In this work, we propose a novel CMOS-only current reference, achieving temperature compensation by exploiting geometry dependences of the threshold voltage (specifically, the reverse short-channel effect and the narrow-channel effect). This allows reaching first-order temperature compensation within a single current reference core. Implemented in 0.18 µm CMOS, a version of the proposed current reference designed to deliver 141 nA (with 377 nW of total power consumption) achieved an average temperature coefficient equal to 194 ppm/°C (from −20 °C to 80 °C) and an average line sensitivity of −0.017%/V across post-layout statistical Monte Carlo simulations. Based on such findings, the newly proposed design methodology stands out as a noteworthy solution to design robust current references for power-constrained mixed-signal systems-on-chip. Full article

This paper presents a CMOS-based optoelectronic receiver integrated circuit (CORIC) realized in a standard 180 nm CMOS technology for the applications of short-distance optical interconnects. The CORIC comprises a spatially modulated P⁺/N-well on-chip avalanche photodiode (P⁺/NW APD) for optical-to-electrical conversion, a dummy APD at the differential input for enhanced common-mode noise rejection, a cross-coupled differential transimpedance amplifier (CCD-TIA) for current-to-voltage conversion, a 3-bit continuous-time linear equalizer (CTLE) for adaptive equalization by using NMOS registers, and a $f_T$-doubler output buffer (OB). The CTLE and $f_T$-doubler OB combination not only compensates the frequency-dependent signal loss, but also provides symmetric differential output signals. Post-layout simulations of the proposed CORIC reveal a transimpedance gain of 53.2 dBΩ, a bandwidth of 4.83 GHz even with a 490 fF parasitic capacitance from the on-chip P⁺/NW APD, a dynamic range of 60 dB that handles the input photocurrents from 1 μA_pp to 1 mA_pp, and a DC power consumption of 33.7 mW from a 1.8 V supply. The CORIC chip core occupies an area of 260 × 101 μm². Full article

This paper introduces an analog differential optoelectronic receiver (ADOR) integrated with digital slicers for short-range LiDAR systems, consisting of a spatially modulated P⁺/N-well on-chip avalanche photodiode (APD), a cross-coupled differential transimpedance amplifier (CCD-TIA) with cross-coupled active loads, a continuous-time linear equalizer (CTLE), a limiting amplifier (LA), and dual digital slicers. A key feature is the integration of an additional on-chip dummy APD at the differential input node, which enables the proposed ADOR to outperform a traditional single-ended TIA in terms of common-mode noise rejection ratio. Also, the CCD-TIA utilizes cross-coupled PMOS-NMOS active loads not only to generate the symmetric output waveforms with maximized voltage swings, but also to provide wide bandwidth characteristics. The following CTLE extends the receiver bandwidth further, allowing the dual digital slicers to operate efficiently even at high sampling rates. The LA boosts the output amplitudes to suitable levels for the following slicers. Then, the inverter-based slicers with low power consumption and a small chip area produce digital outputs. The fabricated ADOR chip using a 180 nm CMOS process demonstrates a 20 dB dynamic range from 100 μA_pp to 1 mA_pp, 2 Gb/s data rate with a 490 fF APD capacitance, and 22.7 mW power consumption from a 1.8 V supply. Full article

This paper presents an ultra-wideband transformer feedback (TFB) monolithic microwave integrated circuit (MMIC) power amplifier (PA) developed using a 0.25 μm gallium nitride (GaN) process. To broaden the bandwidth, a drain-to-gate TFB technique is employed in this PA design, achieving a 117% relative −3 dB bandwidth, extending from 5.4 GHz to 20.3 GHz. At a 28 V supply, the designed PA circuit achieves an output power of 25.5 dBm and a 14 dB small-signal gain in the frequency range of 6 to 19 GHz. Within the 6 to 19 GHz frequency range, the small-signal gain exhibits a flatness of less than 0.78 dB. The PA chip occupies an area of 1.571 mm². This work is the first to design a power amplifier with on-chip transformer feedback in a compound semiconductor MMIC process, and it enables the use of the widest bandwidth power amplifier on-chip transformer matching network. Full article

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process. Full article

In this paper, a fully integrated capacitive DC-DC boost converter for ultra-low-power internet of things (IoT) applications operating with RF energy harvesting is proposed. A DC-DC boost converter is needed to boost the low output voltage of the RF energy harvester to provide a high voltage to the load. However, a boost converter operating at a low voltage supplied by ambient RF energy harvesting has a problem in that power conversion efficiency is significantly lowered. The proposed on-chip capacitive DC-DC boost converter simultaneously applies gate bias boosting and dynamic body biasing techniques using only the internal boosted voltage without an additional circuit that increases power loss to boost the voltage, achieving high efficiency at an input voltage as low as 0.1 V. The designed capacitive boost converter achieves a peak power conversion efficiency (PCE) of 33.8% at a very low input voltage of 0.1 V, a 14% improvement over the peak PCE of the conventional cross-coupled charge pump. A maximum peak PCE of 80.1% is achieved at an input voltage of 200 mV and a load current of 3 μA. The proposed capacitive boost converter is implemented with a total flying capacitance of 60 pF, suitable for on-chip integration. Full article

This paper describes a 2.4-GHz fully-integrated front-end receiver including a single-pole triple-throw (SP3T) switch and a low-noise amplifier (LNA) with bypass function, which was fabricated in a 0.25 μm GaAs pHEMT process. An asymmetrical SP3T switch architecture is incorporated to enable the receiver to operate in four modes. The exploration of impedance and voltage gain behavior of the proposed LNA help to establish the matching network and alleviate the trade-off between noise figure (NF) and gain performance. In LNA high gain mode, the implemented front-end receiver shows 1.7 dB of NF and 6dBm of input third-order intercept point (IIP3) with 20 dB of power gain drawing 11 mA of current from 5 V power supply at 2.4 GHz. All input and output return loss had exceeded 10 dB with fully on-chip impedance matching network. In bypass mode, the measured insertion loss of typically 7.5 dB is achieved. Full article

With the wide application of autonomous mobile robots (AMRs), the visual inertial odometer (VIO) system that realizes the positioning function through the integration of a camera and inertial measurement unit (IMU) has developed rapidly, but it is still limited by the high complexity of the algorithm, the long development cycle of the dedicated accelerator, and the low power supply capacity of AMRs. This work designs a reconfigurable accelerated core that supports different VIO algorithms and has high area and energy efficiency, precision, and speed processing characteristics. Experimental results show that the loss of accuracy of the proposed accelerator is negligible on the most authoritative dataset. The on-chip memory usage of 70 KB is at least 10× smaller than the state-of-the-art works. Thus, the FPGA implementation’s hardware-resource consumption, power dissipation, and synthesis in the 28 nm CMOS outperform the previous works with the same platform. Full article

This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 ${\mathrm{mm}}^2$, 0.063 ${\mathrm{mm}}^2$, 0.045 ${\mathrm{mm}}^2$, and 0.03 ${\mathrm{mm}}^2$ of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively. Full article

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of $2.34$ $\mathrm{m}$$\mathrm{m}$${}^2$. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current. Full article

In this study, we developed a single-channel channel emulator module with an operating frequency covering 66–67 GHz, including a 66–76 GHz wide dynamic range monolithic integrated circuit designed based on 0.1 µm pHEMT GaAs process, a printed circuit board (PCB) power supply bias network, and low-loss ridge microstrip line to WR12 (60–90 GHz) waveguide transition structure. Benefiting from the on-chip multistage band-pass filter integrated at the local oscillator (LO) and radio frequency (RF) ends, the module’s spurious components at the RF port were greatly suppressed, making the module’s output power dynamic range over 50 dB. Due to the frequency-selective filter integrated in the LO chain, each clutter suppression in the LO chain exceeds 40 dBc. Up and down conversion loss of the module is better than 14 dB over the 66–67 GHz band, the measured IF input P1 dB is better than 10 dBm, and the module consumes 129 mA from a 5 V low dropout supply. A low-loss ridged waveguide ladder transition was designed (less than 0.4 dB) so that the output interface of the module is a WR12 waveguide interface, which is convenient for direct connection with an instrument with E-band (60–90 GHz) waveguide interface. Full article

A silicon-chip-based 3D metal solenoidal transformer is proposed and developed to achieve AC-DC conversion for integrated power supply applications. With wafer-level micro electromechanical systems (MEMS) fabrication technique to form the metal casting mold and the following micro-casting technique to rapidly (within 6 min) fill molten ZnAl alloy into the pre-micromachined silicon mold, 45-turns primary solenoid and 7-turns secondary solenoid are fabricated in silicon wafers, where the two intertwining solenoids are located at inner deck and outer deck, respectively. Permalloy soft magnetic core is inserted into a pre-etched channel in the silicon chip, which is surrounded by the solenoids. The size of the chip-style transformer is as small as 8.5 mm × 6.6 mm × 2.5 mm. The internal resistance of the primary solenoid is 1.82 Ω and that of the secondary solenoid is 0.16 Ω. The working frequency of the transformer is 60 kHz. Combined with the testing circuit of the switch mode power supply, the DC voltage of 13.02 V is obtained when the input is 110 V at 50 Hz/60 Hz. Furthermore, the on-chip 3D solenoidal transformer is used for lighting four LEDs, which shows great potential for AC-DC power supply. The wafer-level fabricated chip-style solenoidal AC-DC transformer for integrated power supply is advantageous in uniform fabrication, small size and volume applications. Full article

An intracortical visual prosthesis plays a vital role in partially restoring the faculty of sight in visually impaired people. Reliable high date rate wireless links are needed for transcutaneous communication. Such wireless communication should receive stimulation data (downlink) and send out neural recorded data (uplink). Hence, there is a need for an implanted transceiver that is low-power and delivers sufficient data rate for both uplink and downlink. In this paper, we propose an integrated circuit (IC) solution based on impulse radio ultrawideband using on-off keying modulation (OOK IR-UWB) for the uplink transmitter, and binary phase-shift keying (BPSK) with sampling and digital detection for the downlink receiver. To make the solution low-power, predominantly digital components are used in the presented transceiver test-chip. Current-controlled oscillators and an impulse generator provide tunability and complete the on-chip integration. The transceiver test-IC is fabricated in 180 nm CMOS technology and occupies only 0.0272 mm${}^2$. At 1.3 V power supply, only 0.2 mW is consumed for the BPSK receiver and 0.3 mW for the IR-UWB transmitter in the transceiver IC, while delivering 1 Mbps and 50 Mbps, respectively. Our link budget analysis shows that this test chip is suitable for intracortical integration considering the future off-chip antennas/coils transcutaneous 3–7 mm communication with the outer side. Hence, our work will enable realistic wireless links for the intracortical visual prosthesis. Full article

This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout regulator (LDO), which is more suitable for a high operating frequency. An area-efficient threshold-based digital control structure is used to detect the bootstrap voltage, thereby effectively preventing bootstrap under-voltage or over-voltage that may result in insufficient driving capability, increased loss, or breakdown of the power device. The design and implementation of the circuit are based on CSMC 0.25 µm 60 V BCD technology, with an overall chip area of 1.4 × 1.3 mm², of which the bootstrap area is 0.149 mm² and the figure-of-merit (FOM) is 0.074. The experimental results suggest that the bootstrap circuit can normally operate at 5 MHz with a maximum buck converter efficiency of 83.6%. This work plays a vital role in promoting the development of a wide range of new products and new technologies, such as integrated power supplies, new energy vehicles, and data storage centers. Full article

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit. Full article