Search Results (30)

Dynamic on-resistance (R_ON) of commercial GaN on Si normally off high-electron-mobility transistor (HEMT) devices is a very important parameter because it is responsible for conduction losses that limit the power conversion efficiency of high-power switching converters. Due to charge trapping effects, dynamic R_ON is always higher than in DC, a behavior known as current collapse. To study how short-time dynamics of charge trapping and release affects R_ON we use rectangular 0–5 V gate voltage pulses with durations in the 1 μs to 100 μs range. Measurements are first carried out for single pulses of increasing duration, and it is found that R_ON depends on both pulse duration and drain current I_D, being higher at shorter pulse durations and lower I_D. For a train of five pulses, R_ON decreases with pulse number, reaching a steady state after a time interval of 100 μs. The response to a five pulses train is compared to that of a square-wave signal to study the time evolution of R_ON toward a dynamic steady state. The DC R_ON is also measured, and it is a factor of ten smaller than dynamic R_ON at the same I_D. This confirms that a reduction in trapped charges takes place in DC as compared to the square-wave switching operation. Additional off-state stress tests at V_DS = 55 V reveal the presence of residual surface traps in the drain access region, leading to four times increase in R_ON in comparison to pristine devices. Finally, the dynamic R_ON is also measured by the double-pulse test (DPT) technique with inductive load, giving a good agreement with results from single-pulse measurements. Full article

A series of problems, such as material damage and charge trap, can be caused when GaN HEMT power devices are subjected to high field stress in the off-state. The reliability of GaN HEMT power devices affects the safe operation of the entire power electronic system and seriously threatens the stability of the equipment. Therefore, it is particularly important to study the damage mechanism of GaN HEMT power devices under high field conditions. This work studies the degradation of Cascode GaN HEMT power devices under off-state high-field stress and analyzes the related damage mechanism. It is found that the high field stress in the off-state will generate a positive charge trap in the oxide layer of the MOS device in the cascade structure. Moreover, defects occur in the barrier layer and buffer layer of GaN HEMT devices, and the threshold voltage of Cascode GaN HEMT power devices is negatively shifted, and the transconductance is reduced. This study provides an important theoretical basis for the reliability of GaN HEMT power devices in complex and harsh environments. Full article

Charge carrier traps due to crystal defects in GaN on Si HEMT devices are responsible for dynamic performance degradation, long-term reliability limitations, and peculiar failure modes. The behavior of traps depends on many variables including heterostructure quality, the specific device structure, and operating conditions. To study the short time dynamics of charge trapping and release on the threshold voltage shift and hysteresis of commercial normally off GaN HEMTs we use triangular 0–5 V gate voltage pulses in the μs to ms duration range. Measurements are performed for single pulses by varying pulse duration and for a train of a few pulses by varying their number. The results indicate that hysteresis and related threshold voltage shift occur after repeated pulses, suggesting an accumulation of trapped charges. However, for a triangular wave hysteresis vanishes, meaning that a dynamic balance between charge trapping and release is established in the device. This can be considered as a positive indicator of device robustness and reliability. The same method, used to measure the gate threshold voltage shift and dynamic R_ON after a 30 min off-state DC stress at V_DS = 55 V with a floating gate, highlights an appreciable performance degradation of the device. Full article

The explosive demand for high-performance secondary power sources in artificial intelligence (AI) has brought significant opportunities for low-voltage GaN devices. This paper focuses on research on high-efficiency and high-reliability low-voltage p-GaN gate HEMTs with a gate–drain distance, L_GD, of 1 to 3 μm in our pilot line, manufactured on 6-inch Si using a CMOS-compatible process, with extraordinary wafer-level uniformity. Specifically, these fabricated p-GaN gate HEMTs with an L_GD of 1.5 μm demonstrate a blocking voltage of over 180 V and a high V_TH of 1.6 V and exhibit a low R_ON of 2.8 Ω·mm. It is found that device structure optimization can significantly enhance device reliability. That is, through the dedicated optimization of source field plate structure and interlayer dielectric (ILD) thickness, the dynamic ON-resistance, R_ON, degradation of devices with an L_GD of 1.5 µm was successfully suppressed from 60% to 20%, and the V_TH shift was significantly reduced from 1.1 to 0.5 V. Further, the devices also passed preliminary gate bias stress and high-voltage OFF-state stress tests, providing guidance for preparing high-performance, low-voltage p-GaN gate HEMTs in the future. Full article

Devices under semi-on-state stress often suffer from more severe current collapse than when they are in the off-state, which causes an increase in dynamic on-resistance. Therefore, characterization of the trap states is necessary. In this study, temperature-dependent transient recovery current analysis determined a trap energy level of 0.08 eV under semi-on-state stress, implying that interface traps are responsible for current collapse. Multi-frequency capacitance–voltage (C-V) testing was performed on the MIS diode, calculating that interface trap density is in the range of $1.37\times {10}^{13}$ to $6.07\times {10}^{12}$${\mathrm{cm}}^{-2}$${\mathrm{eV}}^{-1}$ from $E_C-E_T=0.29$ eV to 0.45 eV. Full article

In this study, a KrF excimer laser with a high-absorption coefficient in metal oxide films and a wavelength of 248 nm was selected for the post-processing of a film and metal oxide thin film transistor (MOTFT). Due to the poor negative bias illumination stress (NBIS) stability of indium gallium zinc oxide thin film transistor (IGZO-TFT) devices, terbium-doped Tb:In₂O₃ material was selected as the target of this study. The XPS test revealed the presence of both Tb³⁺ and Tb⁴⁺ ions in the Tb:In₂O₃ film. It was hypothesized that the peak of the laser thermal effect was reduced and the action time was prolonged by the f-f jump of Tb³⁺ ions and the C-T jump of Tb⁴⁺ ions during the laser treatment. Studies related to the treatment of Tb:In₂O₃ films with different laser energy densities have been carried out. It is shown that as the laser energy density increases, the film density increases, the thickness decreases, the carrier concentration increases, and the optical band gap widens. Terbium has a low electronegativity (1.1 eV) and a high Tb-O dissociation energy (707 kJ/mol), which brings about a large lattice distortion. The Tb:In₂O₃ films did not show significant crystallization even under laser energy density treatment of up to 250 mJ/cm². Compared with pure In₂O₃-TFT, the doping of Tb ions effectively reduces the off-state current (1.16 × 10⁻¹¹ A vs. 1.66 × 10⁻¹² A), improves the switching current ratio (1.63 × 10⁶ vs. 1.34 × 10⁷) and improves the NBIS stability (ΔV_ON = −10.4 V vs. 6.4 V) and positive bias illumination stress (PBIS) stability (ΔV_ON = 8 V vs. 1.6 V). Full article

Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. This is achieved by systematically extracting the corresponding model parameters from single device measurements at different frequency ranges, and then the methodology is applied to analyze the evolution of these parameters when the device is submitted to non-conducting electrical stress. This approach not only allows to inspect the impact of effects not occurring under DC conditions, such as the current due to the time varying dielectric polarization, but also to clearly distinguish effects in accordance with the functional form of their contribution to the device’s impedance. In fact, it is shown that minor changes in the model of the gate capacitance by including additional resistive and capacitive components allows for an excellent model-experiment correlation up to 30 GHz. Moreover, the accuracy of the correlation is shown to be maintained when applying the proposal to the device under different gate-to-source bias conditions and at several stages during off-state degradation. Full article

The body diode degradation in SiC power MOSFETs has been demonstrated to be caused by basal plane dislocation (BPD)-induced stacking faults (SFs) in the drift region. To enhance the reliability of the body diode, many process and structural improvements have been proposed to eliminate BPDs in the drift region, ensuring that commercial SiC wafers for 1.2 kV devices are of high quality. Thus, investigating the body diode reliability in commercial planar and trench SiC power MOSFETs made from SiC wafers with similar quality has attracted attention in the industry. In this work, current stress is applied on the body diodes of 1.2 kV commercial planar and trench SiC power MOSFETs under the off-state. The results show that the body diodes of planar and trench devices with a shallow P+ depth are highly reliable, while those of the trench devices with the deep P+ implantation exhibit significant degradation. In conclusion, the body diode degradation in trench devices is mainly influenced by P+ implantation-induced BPDs. Therefore, a trade-off design by controlling the implantation depth/dose and maximizing the device performance is crucial. Moreover, the deep JFET design is confirmed to further improve the body diode reliability in planar devices. Full article

With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling. Full article

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (I_d) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to I_d degradation including increased off-state current (I_off) and decreased on-state current (I_on). The increased I_off further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy. Full article

Many studies on magnetorheological fluid (MRF) have been carried out over the last three decades, highlighting several salient advantages, such as a fast phase change, easy control of the yield stress, and so forth. In particular, several review articles of MRF technology have been reported over the last two decades, summarizing the development of MRFs and their applications. As specific examples, review articles have been published that include the optimization of the particles and carrier liquid to achieve minimum off-state viscosity and maximum yield stress at on-state, the formulation of many constitutive models including the Casson model and the Herschel–Bulkley (H–B) model, sedimentation enhancement using additives and nanosized particles, many types of dampers for automotive suspension and civil structures, medical and rehabilitation devices, MRF polishing technology, the methods of magnetic circuit design, and the synthesis of various controllers. More recently, the effect of the temperature and thermal conductivity on the properties of MRFs and application systems are actively being investigated by several works. However, there is no review article on this issue so far, despite the fact that the thermal problem is one of the most crucial factors to be seriously considered for the development of advanced MRFs and commercial products of application systems. In this work, studies on the thermal conductivity and temperature in MRFs themselves and their temperature-dependent application systems are reviewed, respectively, and principal results are summarized, emphasizing the following: how to reduce the temperature effect on the field-dependent properties of MRFs and how to design an application system that minimizes the thermal effect. It is noted here that the review summary is organized in a chronological format using tables. Full article

In today’s digital circuits, Si-based MOS devices have become the most widely used technology in medical, military, aerospace, and aviation due to their advantages of mature technology, high performance, and low cost. With the continuous integration of transistors, the characteristic size of MOSFETs is shrinking. Time-dependent dielectric electrical breakdown (TDDB) is still a key reliability problem of MOSFETs in recent years. Many researchers focus on the TDDB life of advanced devices and the mechanism of oxide damage, ignoring the impact of the TDDB effect on device parameters. Therefore, in this paper, the critical parameters of partially depleted silicon-on-insulator (PDSOI) under time-dependent dielectric electrical breakdown (TDDB) stress are studied. By applying the TDDB acceleration stress experiment, we obtained the degradation of the devices’ critical parameters including transfer characteristic curves, threshold voltage, off-state leakage current, and the TDDB lifetime. The results show that TDDB acceleration stress will lead to the accumulation of negative charge in the gate oxide. The negative charge affects the electric field distribution. The transfer curves of the devices are positively shifted, as is the threshold voltage. Comparing the experimental data of I/O and Core devices, we can conclude that the ultra-thin gate oxide device’s electrical characteristics are barely affected by the TDDB stress, while the opposite is true for a thick-gate oxide device. Full article

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (V_TH) depended on the range of the gate stress voltage (V_G.stress) at room temperature. However, the positive shift of V_TH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of V_TH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (I_GD and I_GS) before and after the stress test. The difference between the gate–source current and the gate–drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected. Full article

The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (~10⁻²² A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it’s essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in Al₂O₃ gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/−1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in Al₂O₃ gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at −0.73~−0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in Al₂O₃ dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process. Full article

In this paper, DC, transient, and RF performances among AlGaN/GaN HEMTs with a no field plate structure (basic), a conventional gate field plate structure (GFP), and a double floating field plate structure (2FFP) were studied by utilizing SILVACO ATLAS 2D device technology computer-aided design (TCAD). The peak electric fields under the gate in drain-side can be alleviated effectively in 2FFP devices, compared with basic and GFP devices, which promotes the breakdown voltage (BV) and suppresses the current collapse phenomenon. As a result, the ON-resistance increase caused by the current collapse phenomena is dramatically suppressed in 2FFP ~19.9% compared with GFP ~49.8% when a 1 ms duration pre-stress was applied with V_ds = 300 V in the OFF-state. Because of the discontinuous FP structure, more electric field peaks appear at the edge of the FFP stacks, which leads to a higher BV of ~454.4 V compared to the GFP ~394.3 V and the basic devices ~57.6 V. Moreover, the 2FFP structure performs lower a parasitic capacitance of C_gs = 1.03 pF and C_gd = 0.13 pF than those of the GFP structure (i.e., C_gs = 1.89 pF and C_gd = 0.18 pF). Lower parasitic capacitances lead to a much higher cut-off frequency (f_t) of 46 GHz and a maximum oscillation frequency (f_max) of 130 GHz than those of the GFP structure (i.e., f_t = 27 GHz and f_max = 93 GHz). These results illustrate the superiority of the 2FFP structure for RF GaN HEMT and open up enormous opportunities for integrated RF GaN devices. Full article