Search Results (57)

Two-dimensional indium selenide (InSe) is a promising material for next-generation electronics, characterized by a small electron effective mass and ultrahigh room-temperature mobility. This review systematically examines the fundamental physics and emerging quantum phenomena intrinsic to InSe. It also addresses the recent discovery of sliding ferroelectricity, which breaks macroscopic spatial inversion symmetry and yields robust polarization states without conventional displacive ionic dynamics. Technological progress from mechanical exfoliation to scalable bottom-up metal–organic chemical vapor deposition is evaluated. The review also covers advanced architecture enabled by InSe, including sub-3 nm-node logic transistors and nonvolatile ferroelectric synaptic devices. Finally, key challenges involving stoichiometric control, back-end-of-line-compatible integration, and environmental instability are discussed in the context of future low-power and neuromorphic computing. Full article

Data movement has become a dominant bottleneck in modern artificial intelligence hardware, making in-memory computing a critical direction for energy-efficient and memory-centric architectures. Ferroelectric hafnium oxide provides a distinctive materials platform for this transition because field-driven polarization switching, non-volatility, CMOS compatibility, and nanoscale thickness scalability can be combined within a process-relevant oxide system. This review establishes a device-to-system perspective on HfO₂-based and Hf_0.5Zr_0.5O₂-based ferroelectric memories for in-memory computing. Instead of treating ferroelectric materials, memory devices, circuit primitives, and computing architectures as separate research topics, we examine how their mutual constraints define the achievable efficiency, precision, reliability, and scalability of hafnia-based computing systems. The discussion connects polarization engineering and defect control with charge-domain computation, threshold-state logic, associative search, analog weight representation, neuromorphic plasticity, and sensor-side processing. Particular emphasis is placed on the translation of ferroelectric functionality from individual devices to arrays, macros, and system-level accelerators. We identify variability, fatigue, charge trapping, multilevel-state uncertainty, peripheral overhead, and benchmarking inconsistency as the central barriers that prevent device-level advantages from directly becoming system-level gains. Finally, we outline a cross-layer roadmap in which ferroelectric stack engineering, variability-tolerant arrays, precision-scalable architectures, and SoC-level integration are co-optimized to enable reliable HZO-based memory-centric computing. Full article

The proliferation of intelligent edge devices demands compact, low-power hardware capable of dynamically switching between sensing, logic, and learning tasks—a versatility that traditional multi-chip solutions fundamentally lack. Here, we demonstrate a reconfigurable spin–orbit torque (SOT) device based on an FeTb/Ru/Co synthetic antiferromagnetic (SAF) heterostructure. By modulating the input current amplitude, the device dynamically switches between two distinct operating modes: saturation and activation. In the saturation regime (>80 mA), deterministic magnetization reversal enables Boolean logic operations (AND, NOR). In the activation regime (<80 mA), gradual, non-volatile conductance modulation emulates synaptic plasticity. Benefiting from the strong antiferromagnetic coupling and near-zero net magnetization of the SAF structure, all operations are achieved without external magnetic fields. This single-device, dual-mode reconfigurable architecture establishes a new paradigm for high-density, low-power, multifunctional in-memory computing units, with promise for advancing adaptive edge computing chips. Full article

Memristor-based configuration memory offers an alternative solution to the volatility and large area overhead of conventional Static Random Access Memory (SRAM)-based FPGA configuration memory. Their non-volatile nature and the possibility of stacking them on top of the logic layer in a process called Back-End-Of-Line (BEOL) manufacturing help not only dramatically reduce area consumption but also significantly reduce startup time. However, due to the comparatively high defect probability caused by manufacturing defects, traditional approaches for defect tolerance are not fit to address these defects. This work introduces an approach to defect-aware and tolerant synthesis. Based on this, an investigation into the defect tolerance of different architecture choices regarding the size of LUTs and the fracturability of LUTs is presented. We can show that smaller, non-fracturable LUTs exhibit a higher defect tolerance. Moreover, multiple strategies to improve the mapping result based on the properties of the logic functions are introduced. Notably, reducing the mapping complexity of logic clusters during the packing stage significantly improves the mapping success rate. Full article

Asymmetric error characteristics in spin-transfer torque magnetic random-access memory (STT-MRAM), particularly the imbalance between logical ‘0’ and ‘1’ error probabilities, can significantly degrade system reliability under conventional modulation and error-correcting schemes. This issue is especially critical in sensor network applications, where STT-MRAM is widely adopted for its non-volatility, low standby power, and robustness under energy-constrained and intermittently active operation. Existing approaches typically optimize the detection threshold under the assumption of a fixed or equiprobable bit distribution, while sparse coding techniques impose a predefined imbalance without explicitly accounting for its interaction with threshold detection. In this paper, we formulate the bit error rate (BER) minimization problem as a joint optimization of the codeword bit distribution and the detection threshold over an asymmetric cascaded STT-MRAM channel. Analytical results reveal that the minimum BER is achieved when the error probabilities associated with transmitted ‘0’ and ‘1’ bits are balanced, which induces an intrinsic coupling between the optimal detection threshold and the codeword composition. Motivated by this insight, we propose a new family of threshold-matched probability codes (TMPCs), in which the proportion of logical ‘1’s in each codeword is explicitly designed to match the optimal detection threshold of the underlying channel. The proposed coding framework generalizes conventional sparse modulation by enabling adjustable bit distributions while preserving low-complexity linear encoding and syndrome-based decoding. Numerical evaluations demonstrate that the TMPC achieves consistently lower BERs than existing sparse and fixed-distribution coding schemes across a wide range of STT-MRAM operating conditions, particularly under severe write asymmetry and resistance variation. These results indicate that the proposed joint design offers a principled and flexible approach for improving reliability in STT-MRAM-based sensor networks and non-volatile memory systems. Full article

Recent advancements in nanotechnology have intensified research efforts to address security concerns like hardware trojans and intellectual property (IP) piracy, particularly by exploring novel alternatives to traditional MOSFET devices. Spin-based devices, known for their low power consumption, non-volatility, and seamless integration with silicon substrates, have emerged as promising candidates. This research proposes a novel approach to enhance the security of integrated circuits using spin-based devices known as magnetic tunnel junctions (MTJs). A Non-volatile Polymorphic Logic (NPL) is optimized and designed to perform multiple operations, effectively concealing its true functionality. The analytical studies conducted on the Cadence Virtuoso platform using TSMC 65 nm MOS technology demonstrate the feasibility and efficacy of the proposed approach. The proposed NPL circuit enables polymorphism by allowing the circuit to perform all one- and two-input Boolean logic operations, including NOT, AND/NAND, OR/NOR, and XOR/XNOR, through adjustments of applied keys. This dynamic functionality makes it challenging for attackers to determine the circuit’s true operation. The proposed design exhibits similar timing characteristics for different logic operations, which further complicates the tampering attempts. Additionally, the circuit’s layout is designed to be symmetric, ensuring the execution of all possible operations by the same physical layout. This provides post-manufacturing security from reverse engineering and finds its applications in securing custom IC designs against the evolving landscape of hardware-based threats. Full article

Ferroelectricity in hafnium oxide (HfO₂)-based thin films has emerged as a scalable pathway toward CMOS-compatible non-volatile memories and logic devices. This study examines how dopant chemistry and film thickness influence the stabilization of the ferroelectric phase in ALD-grown HfO₂ thin films doped with Zr, Al, and Y. Structural, morphological, and electrical characterizations were carried out using AFM, GIXRD, P–E, in-plane I/W–E, and C–V measurements on films with thicknesses of 7 nm and 100 nm. AFM revealed atomically smooth and dense surfaces (R_q < 0.5 nm), while GIXRD confirmed the stabilization of the orthorhombic Pca2₁ phase in doped 7 nm films and its relaxation toward the monoclinic phase at 100 nm. The 7 nm HfZrO and HfYO films exhibited robust ferroelectric hysteresis with remanent polarization values up to 60 μC·cm⁻², whereas HfAlO showed a narrower but still distinct switching response. In-plane I/W–E characteristics indicated a combination of Poole–Frenkel and injection-limited conduction, consistent with defect-assisted polarization reversal and asymmetric contact barriers. At 100 nm, all films showed reduced polarization and partially dielectric behavior, as corroborated by the C–V data. These results demonstrate that nanoscale confinement, dopant-induced strain, and oxygen vacancy related defect chemistry collectively stabilize the orthorhombic ferroelectric phase, with Zr doping providing the most favorable balance between polarization strength and leakage control. Full article

By combining density functional theory with the non-equilibrium Green’s function method, we conducted a first-principles investigation of spin-dependent transport properties in a molecular device featuring a dynamic covalent chemical bridge connected to zigzag graphene nanoribbon electrodes. The effects of spin-filtering and spin-rectifying on the I–V characteristics are revealed and explained for the proposed molecular device. Interestingly, our results demonstrate that all three devices exhibit significant single-spin-filtering behavior in parallel (P) magnetization and dual-spin-filtering effects in antiparallel (AP) configurations, achieving nearly 100% spin-filtering efficiency. At the same time, from the I–V curves, we find that there is a weak negative differential resistance effect. Moreover, a high rectifying ratio is found for spin-up electron transport in AP magnetization, which is explained by the transmission spectrum and local density of state. The fundamental mechanisms governing these phenomena have been elucidated through a systematic analysis of spin-resolved transmission spectra and spin-polarized electron transport pathways. These results extend the design principles of spin-controlled molecular electronics beyond graphene-based systems, offering a universal strategy for manipulating spin-polarized currents through dynamic covalent interfaces. The nearly ideal spin-filtering efficiency and tunable rectification suggest potential applications in energy-efficient spintronic logic gates and non-volatile memory devices, while the methodology provides a framework for optimizing spin-dependent transport in hybrid organic–inorganic nanoarchitectures. Our findings suggest that such systems are promising candidates for future spintronic applications. Full article

Magnetic random-access memory, recognized as a breakthrough in spintronics, demonstrates substantial potential for next-generation nonvolatile memory and logic devices due to its unique magnetization-switching mechanism. However, realizing reliable perpendicular magnetization switching via spin–orbit torque necessitates an externally applied in-plane magnetic bias, a requirement that complicates integration in high-density device architectures. This study proposes a novel device architecture where geometric asymmetry engineering in an interlayer design generates an intrinsic equivalent in-plane magnetic field. By strategically introducing a non-symmetrical spacer between the heavy metal and ferromagnetic layers, we establish deterministic magnetization reversal while eliminating external field dependency. Furthermore, the energy barrier during magnetization switching is dynamically adjusted by applying a voltage across a perpendicular-anisotropy magnetic tunnel junction, leveraging the voltage-controlled magnetic anisotropy effect. We established a physics-driven compact model to assess the design and performance of voltage-controlled spin–orbit torque magnetic tunnel junction (VCSOT-MTJ) devices. Simulations reveal that the introduction of a minimally asymmetric light metal layer effectively resolves the issue of incomplete switching in field-free spin-orbit torque systems. Full article

With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric field-effect transistor (FeFET) is one of NVM and has been used in CiM digital circuit design. However, in the implementation of logical functions, different input forms, such as FeFET state and gate voltage, limit the logic cascade and restrict the rapid development of CiM digital circuits. To address this problem, this paper proposes a Vin–Vout CiM unit circuit with the built-in state of FeFET as a bridge. The proposed unit circuit unifies the form of logic inputs and describes the basic structure of FeFET to realize logic functions under the application of gate-source voltage. Based on the proposed unit circuit, basic logic gates are designed and used to realize CiM Full Adder (FA). The simulation results verify the feasibility of FeFET as the core of logic operations and prove the scalability of FeFET-based unit circuit, which is expected to develop more efficient CiM circuits. Full article

Typically, organic multiferroic junctions (OMFJs) are formed of an organic ferroelectric layer sandwiched between two ferromagnetic electrodes. The main scientific interest in OMFJs focuses on the magnetoresistive properties of the magnetic spin valve combined with the electroresistive properties associated with the ferroelectric junction. In consequence, memristive properties that couple magnetoelectric functionalities, which are one of the most active fields of research in material sciences, are opening a large spectrum of technological applications from nonvolatile memory to elements in logic circuits, sensing devices, energy harvesting and biological synapsis models in the emerging area of neuromorphic computing. The realization of these multifunctional electronic elements using organic materials is presenting various advantages related to their low-cost, versatile synthesis and low power consumption functioning for sustainable electronics; green disintegration for transient electronics; and flexibility, light weight and/or biocompatibility for flexible electronics. The purpose of this review is to address the advancement of all OMFJs including not only the achievements in the charge and spin transport through OMFJs together with the effects of electroresistance and magnetoresistance but also the challenges and ways to overcome them for the most used materials for OMFJs. Full article

Spintronics, utilizing both the charge and spin of electrons, benefits from the nonvolatility, low switching energy, and collective behavior of magnetization. These properties allow the development of magnetoresistive random access memories, with magnetic tunnel junctions (MTJs) playing a central role. Various spin logic concepts are also extensively explored. Among these, spin logic devices based on the motion of magnetic domain walls (DWs) enable the implementation of compact and energy-efficient logic circuits. In these devices, DW motion within a magnetic track enables spin information processing, while MTJs at the input and output serve as electrical writing and reading elements. DW logic holds promise for simplifying logic circuit complexity by performing multiple functions within a single device. Nevertheless, the demonstration of DW logic circuits with electrical writing and reading at the nanoscale is still needed to unveil their practical application potential. In this review, we discuss material advancements for high-speed DW motion, progress in DW logic devices, groundbreaking demonstrations of current-driven DW logic, and its potential for practical applications. Additionally, we discuss alternative approaches for current-free information propagation, along with challenges and prospects for the development of DW logic. Full article

Current encryption technologies mostly rely on complex algorithms or difficult mathematical problems to improve security. Therefore, it is difficult for these encryption technologies to possess both high security and high efficiency, which are two properties that people desire. Trying to solve this dilemma, we built a new encryption technology, called configurable encryption technology (CET), based on the typical structure of reconfigurable quaternary logic operator (RQLO) that was invented in 2018. We designed the CET as a block cipher for symmetric encryption, where we use four 32-quit RQLO typical structures as the encryptor, decryptor, and two key derivation operators. Taking advantage of the reconfigurability of the RQLO typical structure, the CET can automatically reconfigure the keys and symbol substitution rules of the encryptor and decryptor after each encryption operation. We found that a chip containing about 70,000 transistors and 500 MB of nonvolatile memory could provide all the CET devices and generalized keys needed for any user’s lifetime, to implement a practical one-time pad encryption technology. We also developed a strategy to solve the current key distribution problem with prestored generalized key source data and on-site appointment codes. The CET is expected to provide a theoretical basis and core technology for using the RQLO to build a new cryptographic system with high security, fast encryption/decryption speed, and low manufacturing cost. Full article

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively. Full article

Flip-flop (FF) serves as a fundamental unit in various sequential logic circuits and complex digital electronic systems for generating, transforming, and temporarily storing digital signals. Nonvolatility plays a crucial role in FFs by ensuring instant data recovery after unexpected data loss. Nonvolatile flip-flop can quickly recover in a self-powered environment, making it suitable for application environments such as the Internet of Things (IOT). Unfortunately, most existing nonvolatile FFs (NVFFs) suffer from extended delays and high energy consumption during data backup and restore operations. In this paper, we propose two innovative voltage-controlled nonvolatile FFs (VC-FFs), namely VC-DFF (voltage-controlled D-FF) and VC-SRFF (voltage-controlled SR-FF), which address these challenges using voltage-controlled spin-orbit torque (VC-SOT) devices. The proposed designs are evaluated using a 40 nm CMOS process. Simulation results demonstrate that the proposed designs achieve significant improvements in write (recovery) energy consumption, with over 7.2× (1.54×) and 18.7× (2×) enhancements compared to their STT- and SOT-based counterparts, respectively. Full article