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6 Results Found

  • Communication
  • Open Access
2 Citations
2,732 Views
13 Pages

23 July 2021

Time synchronization plays an important role in the scheduling and position technologies of sensor nodes in underwater acoustic networks (UANs). The time synchronization (TS) algorithms face challenges such as high requirements of energy efficiency,...

  • Article
  • Open Access
5 Citations
4,400 Views
24 Pages

Homomorphic Filtering for Improving Time Synchronization in Wireless Networks

  • José María Castillo-Secilla,
  • José Manuel Palomares,
  • Fernando León and
  • Joaquín Olivares

20 April 2017

Wireless sensor networks are used to sample the environment in a distributed way. Therefore, it is mandatory for all of the measurements to be tightly synchronized in order to guarantee that every sensor is sampling the environment at the exact same...

  • Article
  • Open Access
6 Citations
5,289 Views
17 Pages

3 September 2015

Time synchronization is essential for node localization, target tracking, data fusion, and various other Wireless Sensor Network (WSN) applications. To improve the estimation accuracy of continuous clock offset and skew of mobile nodes in WSNs, we pr...

  • Article
  • Open Access
13 Citations
8,070 Views
12 Pages

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

  • Dong Wang,
  • Xiaoge Zhu,
  • Xuan Guo,
  • Jian Luan,
  • Lei Zhou,
  • Danyu Wu,
  • Huasen Liu,
  • Jin Wu and
  • Xinyu Liu

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-emb...

  • Article
  • Open Access
9 Citations
4,974 Views
16 Pages

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

  • Jianwen Li,
  • Xuan Guo,
  • Jian Luan,
  • Danyu Wu,
  • Lei Zhou,
  • Yinkun Huang,
  • Nanxun Wu,
  • Hanbo Jia,
  • Xuqiang Zheng and
  • Xinyu Liu
  • + 1 author

16 December 2019

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparis...

  • Article
  • Open Access
9 Citations
4,984 Views
16 Pages

8 November 2022

In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs that utilize delay lines. Additionally, this generic method allows for trade-offs between resolutio...