Search Results (121)

To address the limitations of existing chaotic systems such as complex structure and potential chaotic degradation, this paper proposes a novel four-dimensional discrete chaotic system (4D-DCS) and an image encryption algorithm based on it. The 4D-DCS is constructed by integrating a feedback controller and modulo operation into a linear discrete-time system, featuring a simple structure without the need for intricate matrix reconstruction or memristor circuits. Mathematical analysis confirms its chaos in the sense of Li–Yorke and numerical simulations including Lyapunov exponent (LE) analysis, 0–1 test, and NIST SP 800-22 test demonstrate its hyperchaotic characteristics and excellent pseudorandomness. Based on the 4D-DCS, the proposed encryption algorithm employs SHA-256 to generate initial states for key uniqueness, combines row–column permutation to disrupt pixel correlation, and adopts a reversible neural network for diffusion to enhance confusion capability. Comprehensive security analysis shows that the algorithm achieves an NPCR of ∼99.61% and a UACI of ∼33.46%, a key space of $2^{216}$, information entropy close to 8, and correlation coefficients of encrypted images near 0. It also exhibits strong robustness against differential, cropping, noise, and chosen-plaintext attacks. Comparative analysis with state-of-the-art algorithms validates the 4D-DCS’s advantages in structural simplicity and stability, and the encryption algorithm’s superiority in security and practicality, making it suitable for security-critical applications such as image encryption. Full article

Memristors are state-of-the-art electronic elements with nano sizes, about 3 nm dimensions, with very good nano-second switching and memory properties, low power usage of about 100 µW, and good compatibility with the current technology of CMOS-integrated chips and circuits. These components are potentially applicable in T-byte memory arrays, artificial neural networks, logic gates and many other digital and analog electronic schemes and devices for artificial intelligence. This paper presents the application of some simple and fast-operating modified memristor models with activation thresholds in neural networks and logic circuits. MATLAB ver. 2016a and LTSPICE ver. XVII products are used for the analysis of memristor neural nets and logical circuits for artificial intelligence. Several simple, accurate and fast-operating existing modified memristor models, together with several frequently used standard memristor models, are utilized for the associated analyses and simulations. A comparison between the used memristor models is conducted. The considered memristor models are tuned, using experimentally recorded i-v relations of tungsten-sulfide Knowm memristors. An accurate functioning of the analyzed neural nets and logic functions is confirmed by the derived results. The considered modified memristor models, neural networks and logic schemes are important in modeling and analysis of memristor-based circuits for ultra-high-density artificial intelligence-integrated chips. Full article

Physical unclonable function (PUF) based on intrinsic device randomness has emerged as promising hardware security primitives, yet combining secure encryption with neuromorphic recognition within a single device platform remains challenging. Here, we demonstrate a photosensing PUF based on an intrinsically random SnTe memristor capable of both image encryption and memristive neural network recognition. The SnTe memristor, fabricated with an In₂O₃:SnO₂/SnTe/Nb:SrTiO₃ structure, exhibits stable resistive switching and stable retention exceeding 4000 s. Synaptic biomimetic behaviors including learning-experience emulation, short-term plasticity and long-term plasticity are also realized. Notably, the device displays pronounced optical sensitivity that produces stochastic photocurrent fluctuations originating from unavoidable device-to-device variations under illumination. By quantizing these random photocurrents, an encryption key stream is generated and utilized for image scrambling and diffusion. A memristive neural network is constructed to classify the encrypted images, achieving a recognition accuracy of 95.1% with a loss of 0.15 after 300 training epochs. This work establishes a viable pathway from intrinsic optical randomness to secure neuromorphic computing, highlighting the multifunctional potential of SnTe memristors in integrated hardware security and brain-inspired computation. Full article

This paper presents a behavioral-level, pre-silicon analytical co-design framework for memristor read–write interfaces, intended to establish closed-form design rules that subsequently guide SPICE-level and silicon-level realizations. Memristor-based neural hardware requires interfaces that can program resistance states efficiently while suppressing read disturbance, yet existing designs typically rely on empirical tuning without closed-form analytical rules. We close this gap by deriving a single closed-form operating-window inequality $(v_{\mathrm{on}}<V_{\mathrm{rd}}<v_{\mathrm{off}},V_{\mathrm{wr}}\ge V_{\mathrm{wr}}^{min}\left(T_{\mathrm{wr}}\right))$ from the VTEAM state equation, embedding it in an Energy–Delay–Accuracy (EDA) cost function, and validating the resulting parameter set hierarchically up to MNIST-scale inference. The main finding is that this analytically derived parameter set simultaneously achieves a 96.08% set-cycle energy saving and 90.6% MNIST top-1 accuracy (1.2% below software baseline) under realistic D2D/C2C variability, with every measured number agreeing with its analytical prediction within 2%. The framework is instantiated with a two-phase over-threshold-write and sub-threshold-read timing strategy together with a mutually exclusive PMOS-NMOS path-isolation topology, evaluated through behavioral-level MATLAB simulation under linear-drift and VTEAM models. Behavioral simulation confirms each analytical bound within 2%: a 13.78× resistance window with $\le 0.008\%$ cycle-to-cycle drift, 5.01% read-current CV, and 30.94%/96.08% Reset/Set energy savings versus a no-separation baseline. Transistor-level non-idealities (slew rate, charge injection, RTN, retention aging, peripheral overhead) are bounded analytically; full SPICE/silicon validation is identified as immediate follow-up work. These results establish a reusable, analytically grounded reference design that bridges memristive device modeling, circuit-level interface implementation, and neural network-level usability. Full article

Memristors, as programmable resistive switching devices, offer two fundamental computational modalities for artificial intelligence: static conductance for parallel data processing and dynamic switching for temporal, logical, and stochastic operations. This Review systematically distinguishes these two modalities and evaluates their respective hardware implementations. In terms of our review scope, we first examine how static conductance modality is exploited in analog matrix computing, which encompasses matrix–vector multiplication and matrix equation solving, and discuss how these primitives enable efficient neural network inference and training. Second, we survey dynamic switching modality and its algorithmic applications, including stateful logic for digital in-memory acceleration, attractor networks for associative memory, reservoir computing and spatiotemporal signal processing using transient device dynamics, biologically inspired spike-timing-dependent plasticity, and stochastic computation. In addition, we discuss key challenges such as device variability, stochastic switching, interconnect parasitics, peripheral circuit overhead, and endurance limitations. We also highlight opportunities for future development, emphasizing algorithm–hardware co-design to leverage application-specific error tolerance and mitigate device non-idealities. Finally, we outline promising research directions aimed at realizing robust, scalable, and energy-efficient memristor-based AI systems. Full article

Despite the success of artificial neural networks in solving numerous tasks, they face significant challenges, including difficulties in online adaptation and rapidly increasing energy consumption. As a biologically plausible alternative, spiking neural networks offer promising capabilities for efficient cognitive computing. Recently, a three-element spiking neuron model consisting of a threshold selector, a tunnel diode, and a capacitor was proposed. In this work, we experimentally validate this model using a threshold selector hardware emulator and demonstrate its dynamical equivalence to the biologically plausible Izhikevich neuron model. To evaluate the novel neuron’s applicability for cognitive computing, we implement a liquid state machine (LSM) reservoir architecture with spatially dependent random topology for synaptic weight distribution. Our simulations on the MNIST and Fashion-MNIST benchmarks demonstrate competitive classification accuracy (97.9% and 89.5%, respectively) while offering estimated energy efficiency and processing speed enhancements compared to existing FPGA-based and memristor-based spiking reservoir implementations. The developed reservoir is feasible for processing neuromorphic sensors output, including visual perception tasks. Full article

Memristors, whose magnetic flux is inherently dependent on external excitation, have been widely employed to model electromagnetic induction effects in neural systems. However, when such induction mechanisms are incorporated into fractional-order neurons, the resulting nonlinear dynamics remain largely unexplored. This paper proposes a novel fractional-order memristive neural network (FO-MNN) by embedding two memristors into a single Hopfield-type neuron, both serving to characterize electromagnetic induction behavior. The complex nonlinear dynamics induced by the two memristive modules are systematically investigated. Numerical simulations reveal that, by tuning the parameters of the first memristive module, Lorenz-like double-wing butterfly attractors can be generated. When both memristive modules act simultaneously, the network exhibits highly complex multi-double-wing butterfly chaotic attractors, whose wing numbers can be flexibly adjusted via the control parameter of the second memristive module. Moreover, variations in the initial state of the second memristor lead to initial-condition-dependent coexistence of multiple double-wing butterfly attractors. These rich dynamical behaviors highlight the strong potential of the proposed FO-MNN for chaos-based engineering and security applications. Finally, a novel privacy-protection scheme for the Industrial Internet of Things (IIoT) is constructed based on the FO-MNN, and its effectiveness is validated through encryption experiments. Full article

The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence. Full article

Memristors are valuable elements with very good memory and switching features. They have minimal power consumption, nano-scale sizes, and a possibility for integration with high-density Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. They are applicable in neural networks, memory crossbars, and different electronic devices. This work considers some improved and existing models for memristors, functioning at high-frequency signals with a high speed and very good effectiveness. The main parasitic parameters—series resistance, capacitance, and small-signal direct current (DC) voltage and current shifting signals—are taken into account. An additional leakage conductance is analyzed as a parasitic component. The influence of the parasitic parameters on the normal functioning of memristor-based circuits is analyzed and evaluated at hard-switching and soft-switching modes. For investigations of the main characteristics of the considered models and their applicability in memory arrays, Linear Technology Simulation Program with Integrated Circuits Emphasis (LTSPICE) library models are generated and analyzed. The considered models operate at low-, middle- and high-frequency signals, clearly demonstrating the main properties of memristors. Their appropriate operation in passive memory arrays is analyzed and established. The proposed models have a 26% enhanced accuracy in fitting experimental i-v relations. They ensure good memory and switching properties for memory arrays. This work could be a suitable step towards the design and manufacturing of ultra-high-density memristor-based integrated chips. Full article

The memristor has long been known as a nonvolatile memory technology alternative and has recently been explored for neuromorphic computing, owing to its capability to mimic the synaptic plasticity of the human brain. The architecture of a memristor synapse device allows ultra-high-density integration by internetworking with crossbar arrays, which benefits large-scale training and learning using advanced machine-learning algorithms. In this review, we present a statistical analysis of neuromorphic computing device publications from 2018 to 2025, focusing on various memristive systems. Furthermore, we provide a device-level perspective on biomimetic properties in hardware neural networks such as short-term plasticity (STP), long-term plasticity (LTP), spike timing-dependent plasticity (STDP), and spike rate-dependent plasticity (SRDP). Herein, we highlight the utilization of optoelectronic synapses based on 2D materials driven by a sequence of optical stimuli to mimic the plasticity of the human brain, further broadening the scope of memristor controllability by optical stimulation. We also highlight practical applications ranging from MNIST dataset recognition to hardware-based pattern recognition and explore future directions for memristor synapses in healthcare, including artificial cognitive retinal implants, vital organ interfaces, artificial vision systems, and physiological signal anomaly detection. Full article

The use of neural network technologies is becoming more widespread today, from automating routine office tasks to developing new medicines. However, at the same time, the load on power grids and generation systems increases significantly, which, alongside the desire to increase equipment performance, further motivates the development of specialized architectures for hardware implementation and training of neural networks. Memristor-based systems are considered one of the promising areas for creating energy-efficient platforms for artificial intelligence (AI) due to their ability to implement in-memory computing at the hardware level. A crucial step towards the realization of such systems is the comprehensive characterization of memristive devices. This work presents the implementation of a hardware platform for the automated measurement of key memristor characteristics, including current-voltage (I-V) curves, retention time, and endurance. The developed device features a modular architecture for validating the functionality of individual subsystems and incorporates a unipolar pulse switching scheme to mitigate the risk of gate-oxide breakdown in 1T1R active arrays that can occur when applying negative voltages during synaptic weight programming. Full article

Memristor is widely used to construct various memristive neural networks with complex dynamical behaviors. However, hidden multiple attractors have never been realized in memristive neural networks. This paper proposes a novel chaotic system based on a memristive Hopfield neural network (HNN) capable of generating hidden multiple attractors. A multi-segment memristor model with multistability is designed and serves as the core component in constructing the memristive Hopfield neural network. Dynamical analysis reveals that the proposed network exhibits various complex behaviors, including hidden multiple attractors and a super multi-stable phenomenon characterized by the coexistence of infinitely many double-chaotic attractors—these dynamical features are reported for the first time in the literature. This encryption process consists of three key steps. Firstly, the original chaotic sequence undergoes transformation to generate a pseudo-random keystream immediately. Subsequently, based on this keystream, a global permutation operation is performed on the image pixels. Then, their positions are disrupted through a permutation process. Finally, bit-level diffusion is applied using an Exclusive OR(XOR) operation. Relevant research shows that these phenomena indicate a high sensitivity to key changes and a high entropy level in the information system. The strong resistance to various attacks further proves the effectiveness of this design. Full article

Memristors, as novel one-port electronic elements, have very good memory and commutating properties, insignificant power consumption, and a good compatibility to present CMOS integrated chips. They are applicable in neural networks, memory arrays, and various electronic devices. This paper proposes a simple LTSPICE model of an adapted activation function and a neuron built on memristors. In the neuron, synaptic bonds are implemented by single memristors, allowing a decreased circuit complexity. The summing and scaling schemes are based on op-amps and memristors. The applied modified tangent-sigmoidal activation function is implemented with MOS transistors and memristors. Analyses and simulations are conducted using a simple and high-rate operating memristor model with parasitic parameters—resistance, inductance, capacitance, and small-signal DC components. Their influence on the normal operation of the memristors in the neuron is analyzed, paying attention to their usage and adjustment. The proposed memristor-based artificial neuron is analyzed in MATLAB–Simulink and LTSPICE simulators. A comparison between the derived results confirms the correct operation of the proposed memristor neuron. The generation and analyses of the suggested memristor-based neuron is a significant and promising step for the design and engineering of high-complexity neural networks and their realization in ultra-high-density integrated neural circuits and chips. Full article

Traditional Hopfield neural networks (HNNs) suffer from limitations in generating controllable chaotic dynamics, which are essential for applications in neuromorphic computing and secure communications. Memristors, with their memory-dependent nonlinear characteristics, provide a promising approach to regulate neuronal activities, yet systematic studies on attractor offset behaviors remain scarce. In this study, we propose a fully memristive electromagnetic radiation neural network by incorporating three distinct memristors as external electromagnetic stimuli into an HNN. The parameters of the memristors were tuned to modulate chaotic oscillations, while variations in initial conditions were employed to explore multistability through bifurcation and basin stability analyses. The results demonstrate that the system enables large-scale amplitude control of chaotic signals via memristor parameter adjustments, allowing arbitrary scaling of attractor amplitudes. Various offset behaviors emerge, including parameter-driven symmetric double-scroll relocations in phase space and initial-condition-induced offset boosting that leads to extreme multistability. These dynamics were experimentally validated using an STM32-based electronic circuit, confirming precise amplitude and offset control. Furthermore, a multi-channel pseudo-random number generator (PRNG) was implemented, leveraging the initial-boosted offset to enhance security entropy. This offers a hardware-efficient chaotic solution for encrypted communication systems, demonstrating strong application potential. Full article

Spiking Neural Networks (SNNs), with their event-driven and energy-efficient characteristics, have shown great promise in processing data from neuromorphic sensors. However, the sparse and non-stationary nature of event-based data poses significant challenges to optimization, particularly when using conventional algorithms such as AdamW, which assume smooth gradient dynamics. To address this limitation, we propose MemristiveAdamW, a novel algorithm that integrates memristor-inspired dynamic adjustment mechanisms into the AdamW framework. This optimization algorithm introduces three biologically motivated modules: (1) a direction-aware modulation mechanism that adapts the update direction based on gradient change trends; (2) a memristive perturbation model that encodes history-sensitive adjustment inspired by the physical characteristics of memristors; and (3) a memory decay strategy that ensures stable convergence by attenuating perturbations over time. Extensive experiments are conducted on two representative event-based datasets, Prophesee NCARS and GEN1, across three SNN architectures: Spiking VGG-11, Spiking MobileNet-64, and Spiking DenseNet-121. Results demonstrate that MemristiveAdamW consistently improves convergence speed, classification accuracy, and training stability compared to standard AdamW, with the most significant gains observed in shallow or lightweight SNNs. These findings suggest that memristor-inspired optimization offers a biologically plausible and computationally effective paradigm for training SNNs on event-driven data. Full article