Neurosynaptic Core Prototype for Memristor Crossbar Arrays Diagnostics

Abstract

The use of neural network technologies is becoming more widespread today, from automating routine office tasks to developing new medicines. However, at the same time, the load on power grids and generation systems increases significantly, which, alongside the desire to increase equipment performance, further motivates the development of specialized architectures for hardware implementation and training of neural networks. Memristor-based systems are considered one of the promising areas for creating energy-efficient platforms for artificial intelligence (AI) due to their ability to implement in-memory computing at the hardware level. A crucial step towards the realization of such systems is the comprehensive characterization of memristive devices. This work presents the implementation of a hardware platform for the automated measurement of key memristor characteristics, including current-voltage (I-V) curves, retention time, and endurance. The developed device features a modular architecture for validating the functionality of individual subsystems and incorporates a unipolar pulse switching scheme to mitigate the risk of gate-oxide breakdown in 1T1R active arrays that can occur when applying negative voltages during synaptic weight programming.

1. Introduction

The rapid development and widespread adoption of artificial intelligence (AI) across various domains are underpinned by advances in two interconnected fields: neural network algorithms and microelectronics.

On one hand, neural network algorithms have achieved remarkable success in tasks such as image and speech processing, autonomous vehicle control, and big data analytics. Notably, breakthroughs in text generation and understanding models are revolutionizing technologies like search engines [1,2,3].

On the other hand, the growing complexity of these algorithms drives the need for ever-greater computational power. This has established a positive feedback loop: more sophisticated algorithms drive the development of more powerful hardware, which in turn enables the creation of even more advanced algorithms. However, this progress comes at a significant energy cost. The rapidly rising electricity consumption of data centers is now a critical concern, prompting major technology firms to explore novel solutions, including partnerships with the nuclear energy sector. This energy challenge intensifies the pressure on the microelectronics industry to not only improve performance but also to develop fundamentally new, energy-efficient computing architectures.

Currently, graphics processing units (GPUs) are the dominant hardware platform for training and inference of neural networks, leveraging their massive parallel processing capabilities and widespread adoption, initially driven by the graphics and gaming industries. Furthermore, modern GPU architectures increasingly incorporate specialized cores (e.g., Tensor Cores) designed explicitly to accelerate neural network operations.

Beyond GPUs, dedicated digital hardware for AI can be broadly categorized into two types. The first comprises tensor processing units (TPUs) or systems on a chip (SoCs) that integrate specialized tensor cores for accelerated AI computation [4,5,6]. The second category features computing systems based on a multicore architecture, organized as a two-dimensional array of interconnected neurosynaptic cores (see Figure 1). Each core consists of specialized functional modules that implement a segment of a neural network layer directly in hardware. This architecture enables the entire network to be mapped onto the processor, significantly enhancing energy efficiency. Depending on their design, neuromorphic systems can be tailored for formal (non-spiking) [7,8] or spiking neural networks [9] with local training capabilities, or can support both paradigms simultaneously [10].

A promising direction in the field of neuromorphic computing is the integration of memristors into such systems. Memristors are nanoscale electrical resistances with a threshold-based change in their conductivity (the resistive switching effect) [11]. By organizing memristors into two-dimensional crossbar arrays, applying input data encoded as voltage vectors to the rows, and reading the resulting output currents from the columns, it becomes possible to transition to in-memory computing [12,13,14,15,16,17,18,19,20,21,22]. This approach physically implements vector-matrix multiplication at the hardware level—one of the fundamental operations in neural network algorithms. Furthermore, by configuring the states of the memristors, it becomes feasible to load an entire neural network into the neuromorphic system. On the other hand, working with such arrays presents certain challenges. For instance, accurately reading memristor conductance is complicated by sneak currents. This issue necessitates architectural complexity, such as the integration of transistors (in 1T1R arrays—one transistor, one memristor), diodes, or selectors [23,24,25,26].

Nevertheless, despite these challenges, both standalone laboratory systems and microprocessor implementations based on memristor crossbar arrays with 1T1R-type cells have been developed, demonstrating a transition to a new level of energy-efficient computing compared to fully digital systems [27,28,29,30,31]. Furthermore, it should be noted that recent years have witnessed a significant increase in research efforts aimed at developing memristor-based hardware for computer vision systems [32,33].

An integral part of developing such systems is the characterization of memristive devices—measuring their current-voltage characteristics, retention time of intermediate resistive states, and endurance. However, a comprehensive characterization of memristive devices remains a time-consuming and non-trivial task, often requiring custom and expensive laboratory setups.

While numerous studies demonstrate successful neural network operation on memristor arrays, the critical engineering phase of building the underlying hardware platform—including its analog and digital subsystems—is often treated as a preliminary step that deserves more attention. To bridge this gap, this work presents a custom-designed hardware neurosynaptic core prototype that addresses these challenges by offering the following key features:

• A modular architecture for independent validation and testing of subsystems.
• An automated measurement suite for efficient characterization of I-V curves, retention, and endurance.
• A unipolar pulse switching scheme to mitigate gate-oxide breakdown risks in transistor-integrated arrays, enhancing testing reliability.
• A scalable switching circuit that supports arrays of up to 64 × 64 elements while minimizing the number of analog components.

Therefore, this work shifts the focus from demonstrating neural network operation on memristors to solving the underlying engineering challenges. The developed platform thus serves as a key enabler for the rigorous testing and co-design of materials, devices, and architectures essential for future neuromorphic systems.

2. Methods and Prototype Overview

The proposed architecture of the neurosynaptic core is based on three principles.

The first aspect involves implementing state control of bipolar memristors using unipolar voltage pulses. This approach is driven by the need to scale up the number of elements in a crossbar array—equivalent to increasing the number of synaptic weights per core—through the integration of n-channel transistors, transitioning to 1T1R cells. This architecture is essential for maintaining accurate readout of memristor conductance in large-scale arrays (larger than 16 × 16) by mitigating sneak currents. However, this integration introduces a reliability constraint: applying voltage pulses with a negative level to the array input risks breaking down the gate dielectric of transistors in the selected column, particularly when a positive voltage is applied to their gates to turn them on. The risk of breakdown is inherently linked to the memristor’s threshold voltage levels. While control using bipolar pulses remains feasible if these thresholds are sufficiently low and within the transistor’s operational range, the potential for significant device-to-device variation in this parameter (on the order of tens of percent) necessitates a cautious approach towards such bipolar driving schemes. Furthermore, when negative pulses are applied, substrate leakage may occur in the transistors if they are not fabricated using SOI (Silicon-on-Insulator) technology (leading to forward biasing of the pn-junction), which would at the very least increase the system’s power consumption.

Figure 2 provides a conceptual overview of the architecture proposed for memristor programming via unipolar pulses. The digital control system sends data on the amplitude of the generated voltages to a digital-to-analog converter (DAC). These voltages are then applied to the memristor crossbar array through a set of switches and multiplexers, having first passed through a current buffer (labeled ‘B’ in the diagram) for signal amplification. The system features three independent circuits, each connected to two DAC channels. This configuration allows each circuit to generate a 64-bit voltage vector, sourced from either of its two assigned DAC channels. The first circuit is responsible for generating the voltage vector that controls the transistors in the memristor array. The second and third circuits are dedicated to increasing and decreasing memristor conductance, respectively. Depending on the selected operation mode—to increase or decrease the memristor conductance—one of the two control circuits is activated. The output signal from the matrix, in the form of a current, is fed into a current-to-voltage converter. Subsequently, the data is digitized by an analog-to-digital converter (ADC) and sent back to the control system.

The hardware implementation of the neurosynaptic core with the presented architecture was based on the second principle: modular system design. This approach offers several critical advantages for complex system development: it localizes potential faults in circuitry or printed circuit board (PCB) layout, simplifies the validation process for individual subsystems, and provides the flexibility to test and integrate upgraded versions of specific modules without requiring a full system redesign. The proposed prototype architecture, shown in Figure 3, consists of eight dedicated modules:

• Control module.
• DAC module (signal generation).
• Current control module.
• Switching module.
• Current to voltage (I-to-V) converter module.
• ADC module (signal digitization).
• Power supply module.
• Interface module (integrating all components into a unified system).

The data flow sequence in it corresponds to the concept shown schematically in Figure 2, extended with a current control module (previously labeled as Buffer B) essential for preventing electrical breakdown within the memristor crossbar array. Let us look at each module sequentially and trace the data flow through the system.

The switching module—the first component developed as part of this modular design—implements the three matrix control circuits described earlier. Figure 4 displays its conceptual floorplan and final PCB layout, designed in the Altium Designer CAD environment (version 23.8.1). The board incorporates three types of multiplexers: twelve MAX14661ETI+ (2:16) and eight ADG706BRUZ (16:1) from Analog Devices Inc. (Wilmington, MA, USA) for generating input vectors for the memristor array, along with three TS5A23166DCUR devices from Texas Instruments Inc. (Dallas, TX, USA) for DAC signal distribution. To manage the extensive control signals required by this configuration and to enable autonomous operation with external measurement systems, such as an NI PXI platform equipped with a PXI-4140 module from National Instruments (Austin, TX, USA), an STM32F030R8T6 microcontroller from STMicroelectronics (Geneva, Switzerland) was integrated onto the board.

The module is controlled via a universal asynchronous receiver-transmitter (UART) interface or an FT232-based USB-UART bridge (FTDI, Glasgow, UK), through which data packets are transmitted to configure the multiplexers and activate the control circuits. Its central section features three connectors, for a custom board housing the memristor crossbar array’s bare die—a solution that proved faster and more practical than sourcing specialized integrated circuit (IC) packages incompatible with our specific die geometry. A distinctive feature of this device, representing the third core architectural principle, is the use of only six DAC channels to manage the memristor array—two per every control circuit—for conductance increase, decrease, and matrix transistor control (see Figure 2). With this configuration, the memristor crossbar array size (16 × 16, 64 × 64, etc.) is arbitrary and limited only by the number of multiplexers in the control circuits and their placement constraints on the compact PCB. We expect that this approach will represent a step toward minimizing area utilization in future integrated versions of the core.

Next, a block of three modules was developed to generate input signals for the switching module. The first of these is the digital control module. Implemented around the STM32F407VGT6 microcontroller from STMicroelectronics (Geneva, Switzerland), it manages all core modules via its built-in interfaces and single-bit logic signals (discussed later in the description of the remaining modules). It also handles user interaction through either a USB-UART bridge or an Ethernet interface, implemented using FT232 and W5500 (WIZnet, Seongnam, South Korea) chips, respectively.

The second module in this group is the DAC module, built around the 16-channel DAC61416RHA converter from Texas Instruments Inc. (Dallas, TX, USA), which is configured via SPI by the digital control module. Of its nine utilized channels, six provide the primary voltage signals to the switching module. The remaining three channels are allocated for auxiliary functions: one sets the current limit in the current control module, one provides a bias voltage for the transimpedance amplifier, and one is reserved for testing.

Completing this group is the current control module, a custom circuit for amplification and limiting. It features eight parallel feedback channels, six of which are dedicated to driving the switching module, aligning with the DAC’s output structure. The other two channels interface with the current-to-voltage converter and serve testing purposes, respectively. Each channel uses a 1 Ω shunt resistor for current sensing, with a feedback system that attenuates the amplifier signal when currents exceed thresholds set by a DAC voltage (scaling: 0.1 V/mA). The circuit was implemented with the OPA197 operational amplifier (Texas Instruments Inc., Dallas, TX, USA) and the AD8421 instrumentation amplifier (Analog Devices Inc., Wilmington, MA, USA) and validated through simulations in NI Multisim (National Instruments, Austin, TX, USA) version 14.2 (see Supplementary Materials, Figures S1 and S2).

The hardware implementation of the prototype core’s data flow is completed by two modules in the readout circuit. The first is the current-to-voltage converter module, implemented using a well-established transimpedance amplifier approach [21,22]. Our design utilizes the THS4631 amplifier IC (Texas Instruments Inc., Dallas, TX, USA). The converted signal is then passed to the second component—the ADC module based on the AD7323 chip (Analog Devices Inc., Wilmington, MA, USA)—where it is digitized, and the final result is transmitted to the control module.

The prototype’s hardware implementation was completed with two key subsystems: a power supply module using PTN78020AAH/PTH08080WAH regulators (Texas Instruments Inc., Dallas, TX, USA) to generate ±12 V/±5 V from a 12 V input, and an interface motherboard that integrates all modules through physical interconnects, power distribution, and mechanical support, realizing the conceptual design in hardware. Figure 5 shows the fully assembled core prototype alongside its corresponding block diagram, which includes the final dimensions of the system.

Following assembly, a bottom-up testing approach was employed, gradually integrating and validating individual modules to build system functionality. The verification process began with the power supply module, confirming its ability to generate correct voltages and distribute them to the appropriate connectors via the interface board. Subsequently, the conductance measurement subsystem was validated by applying a known signal through a test resistor to the current-to-voltage converter, followed by verification of the coordinated operation between the I-to-V converter, ADC, and control module.

The system startup sequence proceeded with DAC initialization and verifying its command-based voltage generation. The next tests verified the current control circuit under load conditions and the correct operation of the memristor state control circuits in the switching module. The final integration stage involved simultaneous operation of all neurosynaptic core components, supported by firmware developed in STM32CubeIDE (version 1.14.1) for both microcontrollers. Figure 5 displays the fully assembled core prototype alongside its system architecture schematic, with final physical dimensions indicated, while the test configuration used for prototype verification and debugging is shown in Supplementary Figures S3–S5. During this phase, the control software was upgraded to implement core diagnostic functions for 64 × 64 1T1R memristor arrays. Acquired measurement data was transmitted via a USB-UART bridge to a Python (version 3.13) script that formatted .csv files for results visualization, as presented in the following section.

3. Results

The developed neurosynaptic core prototype incorporates three functional blocks for memristor array diagnostics.

The first block enables I-V characteristic measurements. Figure 6 presents test results for a 508 Ω resistor, obtained to validate correct system operation. This primarily validates the components responsible for current control and conversion, which directly impact the accuracy of memristor resistance readings. Furthermore, similar measurements were performed for resistors with nominal values ranging from 100 Ω to 100 kΩ. The data showed that the measurement error did not exceed 3%, attributable mainly to a 20 Ω series resistance introduced by the PCB traces and analog switches.

Figure 7 presents the cyclic current-voltage characteristics of two memristors based on a two-layer nanocomposite (CoFeB–LiNbO₃/LiNbO₃) structure. The devices, with laboratory identifiers #2536 and #2592, exhibit stable resistive switching without breakdown, achieved by implementing a current compliance mechanism during measurement.

The voltage scan rate was 0.2 V/s. The resistive switching thresholds remained within a 2.5 V range, which is compatible with the 3.3 V operating voltage of 350 nm CMOS technology. As noted in Section 2, this compatibility is crucial for integration into transistor-accessed crossbar arrays, since the control methodology was designed to account for the voltage limitations of the access transistors. Detailed descriptions of the sample properties and switching mechanisms are provided in [34,35].

The second functional block measures retention time when the memristor is in an intermediate resistive state, utilizing a synaptic weight programming algorithm [36]. Although our memristor structures typically demonstrate an endurance of 10⁵ cycles, a retention of 10⁶ seconds, and a resistance window ranging from 1 to 100 kΩ, the test experiments specifically employed devices with suboptimal stability. This deliberate choice enabled the observation of temporal processes, such as resistance relaxation, with a resolution of approximately 0.1 s.

As shown in Figure 8, both structures exhibited only one intermediate state, which was reached rapidly (<1 s) after switching from either a high- or low-resistance state. The third functional block is designed for switching stability analysis, also known as an endurance test. The procedure began with a current-voltage characteristic measurement to identify the highest and lowest resistance states at a read voltage of 0.1 V. Subsequently, an algorithm for programming a preset resistive state was executed. This algorithm utilized the functionality of the previous block with minor modifications.

This approach involved a finite number of attempts to program the memristor into the target state. This limitation was implemented to prevent potential structure degradation and avoid an endless cycle of attempts to reach a state that might have become inaccessible. Upon completion of the finite programming sequence, the system stored the final resistance value—regardless of whether the precise target state was achieved—and then switched the structure to the opposite resistive state. The results of the software algorithm test, conducted over fifteen resistive switching cycles and presented in Figure 9, confirm its correct operation.

The completed tests identified key directions for further system development. Although the current version supports 64 × 64 1T1R arrays, several improvements were implemented to enhance component reliability and expand functionality—specifically, by adding support for 2T1R array testing. Figure 10 presents the modified switching module and interface board for 64 × 64 crossbar arrays.

The primary modification involves upgraded connectors with enhanced mechanical robustness to withstand repeated mating cycles, substantially reducing the risk of physical damage such as pad lifting or trace detachment. Additional improvements include component unification, where parts with identical functionality but different footprints (e.g., 0603 and 0805 resistors, SOIC-20 and SOIC-16 buffer ICs) were standardized to 0603 resistors and SOT-23 packages for buffer ICs, respectively. Furthermore, redundant features identified during prototype testing, such as the FT232-based USB-UART interface and several PLS-2 and PLS-6 diagnostic connectors, were eliminated for design optimization.

4. Discussion

The experimental results validate the functionality of our prototype as a diagnostic platform for memristor arrays, leading to a discussion of three critical aspects: a comparison with state-of-the-art neurosynaptic cores, an analysis of its vector-matrix multiplication capability, and the pathway toward its miniaturization.

4.1. Comparison with State-of-the-Art Neurosynaptic Core Prototypes

When positioned among existing hardware platforms for memristor-based computing, our prototype occupies a specific niche focused on characterization and subsystem validation. A directly comparable system is the software-hardware complex presented in [27], which supports simultaneous operation with eight active 1T1R arrays (128 × 16) and implements convolutional and feed-forward neural networks in hardware. In contrast, our device prioritizes the detailed characterization of a single, larger array (up to 64 × 64 elements, supporting both passive and active 1T1R/2T1R architectures) and leverages a modular design to facilitate the independent testing and validation of core subsystems, such as the switching and current control modules.

Other state-of-the-art works have progressed towards more integrated solutions. Some demonstrate a System-on-Module (SoM) approach, where a highly integrated memristor array is co-located with control logic on multiple PCBs [18,30], while others achieve full integration of memristors and CMOS control circuits on a single chip [28,31]. In this landscape, our prototype serves as a foundational engineering step. It is not yet a fully fledged neuromorphic accelerator but a versatile and necessary platform for the diagnostic characterization of memristor structures and the validation of control architectures—a critical phase that often precedes successful monolithic integration.

4.2. Vector-Matrix Multiplication Capability

A key feature of the proposed architecture is its inherent support for the fundamental operation of neuromorphic computing: vector-matrix multiplication (VMM). As outlined in Section 2, the use of 2:16 analog multiplexers MAX14661ETI+ from Analog Devices Inc. (Wilmington, MA, USA) in the switching module allows for the generation of arbitrary 64-element voltage vectors at the input of the memristor crossbar. When such a vector is applied to the rows of the array, the resulting currents accumulated on the columns represent the dot products between the input vector and the conductance values of the memristors in each column. This physical implementation of VMM is the cornerstone of hardware-based neural network inference.

While the primary focus of the current work is on diagnostic procedures (measuring I-V curves, retention, and endurance), the architecture is fundamentally designed to perform multiply-accumulate operations. The implementation and benchmarking of neural network inference algorithms using this VMM capability are the planned next step, leveraging the programmability and scalability of the developed prototype.

4.3. Challenges and Strategies for Miniaturization and Large-Scale Integration

The transition from a PCB-based prototype to a large-scale, integrated memristor-CMOS neurosynaptic core presents significant challenges, which can be divided into two main domains.

The first challenge lies in the co-integration of a high-yield, high-performance memristor array with a CMOS backend. This requires achieving uniform memristor characteristics (endurance > 10⁶ cycles, retention > 10⁴ s) across an entire wafer. The memristor’s operational parameters must be carefully co-designed with the transistor technology. For instance, in a 350 nm CMOS process with a 3.3 V supply, the memristor’s threshold voltages must not exceed ~2.5 V to ensure reliable switching without compromising the access transistors. Furthermore, the resistance window (R_off/R_on) must be sufficiently large to overcome the parasitic series resistance of transistors and interconnects, ensuring accurate conductance readout [26] across a large array (e.g., 256 × 256). This is crucial for maintaining computational accuracy during VMM operations from the first to the last column of the array.

The second component involves the integrated circuit-level design of the peripheral electronics. While blocks such as DACs, ADCs, and analog multiplexers are available as standard library elements, they must be carefully matched to the specific current and voltage ranges of the integrated memristor array. Furthermore, the digital control logic for the neurosynaptic core, a CPU interface for system management and external communication, and a network-on-chip for interconnecting multiple cores into a scalable system (as conceptualized in Figure 1) must be developed. A corresponding software stack is equally important to provide system control, algorithm mapping, and data management for the hardware.

Our prototype directly addresses these challenges by providing a platform for empirical validation of these requirements. The modular design allows for testing interface circuits, while the diagnostic suites enable the screening of memristor technologies for large-scale integration. The overall compute-in-memory architecture, combined with a minimalist analog design, provides a foundation for a compact, area-efficient integrated circuit. This approach is expected to achieve energy efficiency levels competitive with current state-of-the-art solutions in a future ASIC implementation.

5. Conclusions

This paper presented the development and validation of a modular neurosynaptic core prototype designed for comprehensive diagnostics of memristor crossbar arrays. The prototype successfully implements three core principles: a unipolar pulse switching scheme for reliable control of bipolar memristors in transistor-integrated arrays, a modular architecture for independent subsystem validation, and a minimalist yet scalable analog design for memristor crossbar array control.

The platform demonstrated its functionality by automating the measurement of key memristor characteristics, including current-voltage curves, retention time, and endurance, with an error not exceeding 3% for resistance readings. The primary advantage of the proposed architecture is its inherent support for vector-matrix multiplication, the fundamental operation for neuromorphic computing, paving the way for future implementation of neural network inference.

While the current prototype is a PCB-level implementation not optimized for ultra-low power consumption, the chosen compute-in-memory architecture and the minimal number of power-intensive analog components establish a foundation for high energy efficiency. The design principles and diagnostic capabilities demonstrated here are critical for the subsequent development of an integrated circuit version, which is expected to achieve energy efficiency competitive with other advanced memristor-based systems.