Search Results (125)

This paper proposes a dual-mode CMOS analog front-end (AFE) circuit for short-wave infrared (SWIR) image sensors, which integrates a hybrid readout circuit (ROIC) and a 12-bit two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC dynamically switches between buffered-direct-injection (BDI) and direct-injection (DI) modes, thus balancing injection efficiency against power consumption. While the DI structure offers simplicity and low power, it suffers from unstable biasing and reduced injection efficiency under high background currents. Conversely, the BDI structure enhances injection efficiency and bias stability via an input buffer but incurs higher power consumption. To address this trade-off, a dual-mode injection architecture with mode-switching transistors is implemented. Mode selection is executed in-pixel via a low-leakage transmission gate and coordinated by the column timing controller, enabling low-current pixels to operate in low-noise BDI mode, whereas high-current pixels revert to the low-power DI mode. The TS-SS ADC employs a four-terminal comparator and dynamic reference voltage compensation to mitigate charge leakage and offset, which improves signal-to-noise ratio (SNR) and linearity. The prototype occupies 2.1 mm × 2.88 mm in a 0.18 µm CMOS process and serves a 64 × 64 array. The AFE achieves a dynamic range of 75.58 dB, noise of 249.42 μV, and 81.04 mW power consumption. Full article

This paper presents a highly efficient, low-power, fully integrated neural stimulation circuit implemented using solely low-voltage devices. The circuit primarily consists of a high-voltage-generation circuit, an output driver circuit, and a constant-current source, designed and simulated using a 180 nm low-voltage CMOS process. The high-voltage-generation circuit utilizes a negative-voltage-generation module together with a series–parallel capacitor charge pump circuit, which effectively reduces the number of charge pump stages by three, and saves 29% of the area compared to a conventional charge pump circuit. A bootstrap clock generation circuit was utilized to generate the control signal to ensure that all transistors work within their voltage limit. To realize the high-voltage output driver circuit using low-voltage devices, a stacked transistor structure with deep N-well (DNW) devices was utilized. The four different output voltage levels from the high-voltage-generation circuit were utilized to generate a different voltage domain of control signals and bias voltage for the stacked transistors, making sure that all transistors work within their voltage limit. Simulation results show that the high-voltage-generation circuit can generate an output of up to 12.69 V from a 1.65 V low input voltage, with a maximum output current of 1 mA, achieving 74.9% efficiency. The overall efficiency of the neural stimulation circuit, including the high-voltage-generation circuit, output driver circuit and constant-current source, reaches 74% under the voltage-controlled stimulation (VCS) mode and 59.5% under the current-controlled stimulation (CCS) mode, whereas the standby static power consumption is as low as 66 pW. Full article

This paper presents a fully integrated bandpass filter (BPF) with high tunability based on a novel differential active inductor (DAI), designed for sensor interface circuits operating in the ultra-high frequency (UHF) band. The design of the proposed DAI is based on a symmetrical configuration, utilizing a differential amplifier for the feedforward transconductance and a common-source (CS) transistor for the feedback transconductance. By integrating a cascode scheme with a feedback resistor, the quality factor of the active inductor is significantly improved, leading to enhanced mid-band gain for the bandpass filter. To facilitate independent tuning of the BPF‘s center frequency and mid-band gain, an active resistor adjustment and bias voltage control are employed, providing precise control over the filter’s operational parameters. Post-layout simulations and process corner results are conducted with 0.13 µm CMOS technology at 1.2 V supply voltage. The proposed second order BPF achieves a broad tuning range of 280 MHz to 2.426 GHz, with a passband gain between 8.9 dB and 16.54 dB. The design demonstrates a maximum noise figure of 16.54 dB at 280 MHz, an input-referred 1 dB compression point of −3.78 dBm, and a third-order input intercept point (IIP3) of −0.897 dBm. Additionally, the BPF occupies an active area of only 68.2×30 µm², including impedance-matching part, and consumes a DC power of 14–20 mW. The compact size and low power consumption of the design make it highly suitable for integration into modern wireless sensor interfaces where performance and area efficiency are critical. Full article

This paper presents a wide-tuning-range, low-power tunable active inductor (AI) designed and fabricated using 130 nm CMOS technology with six metal layers. To achieve high performance with a relatively small silicon area and low power consumption, the AI structure is carefully designed and optimized using a cascode stage, a feedback resistor, and multi-gate finger transistors. In the proposed circuit topology, inductance tuning is realized by adjusting both the bias current and the feedback resistor. The performance of the circuit is evaluated in terms of tuning range, quality factor, power consumption, and chip area. The functionality of the fabricated device is experimentally validated, and the fundamental characteristics of the active inductor are measured over a wide frequency range using a Cascade GSG probe, with results compared to simulations. Experimental measurements show that, under a 1 V supply, the AI achieves a self-resonant frequency (SRF) of 3.961 GHz and a quality factor (Q) exceeding 1586 at 2.383 GHz. The inductance is tunable between 6.7 nH and 84.4 nH, with a total power consumption of approximately 2 mW. The total active area, including pads, is 345 × 400 µm². Full article

Solution-processed metal oxide dielectrics often result in unstable thin-film transistor (TFT) performance, hindering the development of next-generation metal oxide electronics. In this study, we prepared fluorine (F)-doped zirconium oxide (ZrO₂) dielectric layers using a chemical solution method to construct TFTs. The characterization by X-ray photoelectron spectroscopy (XPS) revealed that appropriate fluoride doping significantly reduces oxygen vacancies and the concentration of hydroxyl groups, thereby suppressing polarization processes. Subsequently, the electrical properties of Al/F:ZrO₂/n⁺⁺Si capacitors were evaluated, demonstrating that the optimized 10% F:ZrO₂ dielectric exhibits a low leakage current density and stable capacitance across a wide frequency range. Indium zinc oxide (IZO) TFTs incorporating 10% F:ZrO₂ dielectric layers were then fabricated. These devices displayed reliable electrical characteristics, including high mobility over a broad frequency range, reduced dual-sweep hysteresis, and excellent stability under positive-bias stress (PBS) after three months of aging. These findings indicate that the use of the fluorine-doped ZrO₂ dielectric is a versatile strategy for achieving high-performance metal oxide thin-film electronics. Full article

Schottky barrier thin-film transistors (SBTFTs) are promising for low-power electronics due to advantages such as low saturation voltage and high stability. In this study, we developed a high-performance bilayer IGZO SBTFT by combining a 4.7 nm atomic layer deposition (ALD) IGZO layer with an 11.8 nm sputtering IGZO layer, using platinum (Pt) and molybdenum (Mo) electrodes. The device exhibits dual-mode operation. In Schottky barrier TFT (SB-TFT) mode (Pt as source), the bilayer structure reduces defect density, achieving a very low saturation voltage (~0.4 V), high field-effect mobility (up to 20 cm²/V·s), and enhanced stability under stress conditions, including positive/negative bias and negative illumination. In quasi-Ohmic TFT (QO-TFT) mode (Pt as drain), the device retains conventional saturation behavior in output characteristics while delivering similar mobility and robust stability. This work provides a novel bilayer SBTFT design with dual functionality, enabling a higher current drive, improved stability, and flexibility for energy-efficient applications. Full article

This paper presents a low-voltage, low-power current differencing transconductance amplifier (CDTA) utilizing the bulk-driven MOS transistor technique in the subthreshold region for reduced voltage and power consumption. The proposed CDTA includes a z-copy terminal, which enhances its functionality in current-mode circuit applications. Designed in the Cadence Virtuoso environment using 0.18 µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC), the amplifier operates with a supply voltage of 0.45 V and consumes 328 nW of power, with a bias current set to 10 nA. The current bandwidth and offset of the CDTA are 35 kHz and 0.3 nA, respectively. To demonstrate its performance, the CDTA is applied in a current-mode universal filter, which can realize low-pass, band-pass, high-pass, band-stop, and all-pass responses within a single topology. This design eliminates issues related to inverting input signals, input signal matching, or the need for multiple input signals. Additionally, the natural frequency of these filtering functions can be electronically controlled. The low-pass filter achieves a dynamic range of 61 dB, with a total harmonic distortion of 0.8%. Full article

Semiconductor radiation detectors usually use a specific signal conditioning circuit, ensuring the required detection system parameters. This paper details the noise properties of specific input stages in photoreceivers that detect various types of radiation. For this purpose, the popular silicon PIN photodiode (BPW34) and two different types of low-noise operational amplifiers (AD797A and ADA4625-1) were used. In the presented experiments, noise measurements were provided for voltage and transimpedance amplifiers operating in input stages, comparing their noise and bandwidths. This made it possible to obtain results for bipolar junction transistor (BJT)- and field-effect transistor (FET)-based input stages of circuity, cooperating directly with a photodiode. Analyzing the obtained characteristics and considering the photodiode operation mode, it is evident that the transimpedance amplifier and photoconductive mode should be considered a typical first-choice solution. In some cases, the performances, such as bandwidth and noise, may be similar to those of voltage. Nevertheless, the bias method used in TIA and feedback compensation can also affect the resulting output noise spectral characteristics due to the photodiode and other capacitances existing in the circuit. In the case of a high transimpedance, the FET-based op-amps ensure lower output noise than the BJT-based ones due to the significantly lower current noise. The simple radiation detector with two-channel differential TIA was also proposed and tested based on the results obtained. Full article

Biologically sensitive field-effect transistors (BioFETs) have advanced the biosensing capabilities in various fields such as healthcare, security and environmental monitoring. Here, we propose a junctionless BioFET (JL-BioFET) for the high-sensitivity and low-cost detection of biomolecules and analyze it using detailed device simulations. In contrast to the conventional FET with junctions, the JL-BioFET simplifies fabrication by doping the source, channel and drain simultaneously with the same types of impurities, thereby reducing the fabrication effort and cost. Additionally, if the device is designed with optimal bias, it can operate with only the source and drain terminals, which reduces power consumption. Thus, cost reduction and reduced power consumption are strong motivations to pursue a new design. Therefore, we simulated two JL-BioFET structures (SOI JL, bulk JL) that operate without a gate electrode and compared their biosensing performances. The bulk JL-BioFET showed an average sensitivity three times higher than that of the SOI JL-BioFET across varying charge levels. Then, we optimized the sensing performance of the bulk JL-BioFET by adjusting three key parameters: the active layer thickness and the doping concentrations of the active layer and substrate. These encouraging results are expected to lead to future fabrication efforts to realize bulk JL-BioFETs for high-performance biosensing. Full article

In this paper, a silicon carbide (SiC) phototransistor based on an open-base structure was fabricated and used as a radiation detector. In contrast to the exposed and thin sensitive region of traditional photo detectors, the sensitive region of the radiation detector was much thicker (30 μm), ensuring the high energy deposition of radiation particles. The response properties of the fabricated SiC npn radiation detector were characterized by high-energy X-ray illumination with a maximum X-ray photon energy of 30 keV. The SiC npn detector featured stable and clear response to the X-ray within 0.0766 Gy∙s⁻¹ to 0.766 Gy∙s⁻¹ below 300 V. Due to to the low leakage current of less than 1 nA and the fully depleted sensitive region, the bipolar-transistor-modeled SiC npn detector exhibited a clear common-emitter current gain of 5.85 at 200 V (under 0.383 Gy∙s⁻¹), where the gain increased with bias voltage due to the Early effect and reached 7.55 at 300 V. In addition, the transient response of the SiC npn detector revealed a longer delay time than the SiC diode of the same size, which was associated with the larger effective capacitance of the npn structure. The npn detector with internal gain showed great potential in radiation detection. Full article

Inductively coupled plasma–reactive etching (ICP-RIE) of InGaZnO (IGZO) thin films was studied with variations in gas mixtures of hydrochloride (HCl) and argon (Ar). The dry etching characteristics of the IGZO films were investigated according to radiofrequency bias power, gas mixing ratio, and chamber pressure. The IGZO film showed an excellent etch rate of 83.2 nm/min from an optimized etching condition such as a plasma power of 100 W, process pressure of 3 mTorr, and HCl ratio of 75% (HCl:Ar at 30 sccm:10 sccm). In addition, this ICP-RIE etching condition with a high HCl composition ratio at a moderate RIE power of 100 W showed a low etched pattern skew and low photoresist damage on the IGZO patterns. It also provided excellent surface morphology of the SiO₂ film underneath after the entire dry etching of the IGZO layer. The IGZO thin film as an active layer was successfully patterned under the ICP-RIE dry etching under the HCl-Ar gas mixture, affording an excellent electrical characteristic in the resultant top-gate IGZO thin-film transistor. Full article

In active-matrix organic light-emitting diode (AMOLED) displays, conventional pixel circuits that compensate for the non-uniformity of the threshold voltage (V_T) of low-temperature polycrystalline silicon thin-film transistors (TFTs) can hardly compensate for variations in other TFT parameters, such as carrier mobility (μ₀), subthreshold swing (SS) and the various effects of parasitic capacitance. In recent high-resolution AMOLED displays, as the current required for OLED pixel driving decreases, the current error rate (CER) caused by the non-uniform TFT parameters increases. In this study, we analyzed the influence of each TFT parameter on the CER using SPICE simulation. Based on our analysis, the origin of the increased CER can be classified into two categories: the charging capability of driving TFT and the capacitive coupling effect of the switching TFT. The SS of the driving TFT and the parasitic capacitance of the switching TFT are major factors that affect the CER in terms of the charging capability and capacitive coupling effect, respectively. Our analysis results can be summarized as follows: The SS value of the driving TFT should be high, and its variation should be small to minimize the CER. The variation in the parasitic capacitance of the switching TFT possibly occurs due to long-term bias conditions, as well as process non-uniformity. Therefore, the stability of TFT should also be confirmed for the prevention of anomalous CER caused by long-term bias stress. Full article

This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of −7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm. Full article

This paper proposes a highly linear low-noise amplifier (LNA) using a cascode configuration. In the proposed topology, the linearity of the circuit is enhanced through the application of derivative superposition technology. The technology combines an auxiliary transistor operating in the moderate inversion region with a main transistor operating in the strong inversion region, and two degenerative inductors are connected in series at the source nodes of both transistors. The primary objective of this design is to mitigate the negative impacts of second-order and third-order nonlinearities on the third-order input intercept point (IIP3) through their interactions, thereby enhancing the linear performance of the circuit. An on-chip active bias circuit is designed to effectively address fluctuations in the IIP3 during process and temperature variations by stabilizing the transconductance of the common-source transistor, enabling the LNA to operate reliably in complex environments. During post-layout simulation in DongBu High-Tech’s 0.13 μm CMOS process, the circuit’s output third-order intercept point (OIP3) exhibits minimal fluctuations across different process corners and temperature variations. At the typical nmos and typical pmos (TT) process corner and a temperature of 30 °C, it achieves an OIP3 of 33.9 dBm with a power consumption of 42 mW sourced from a 2.8 V power supply. Furthermore, it realizes a relatively flat gain of 16 dB, a noise figure (NF) of 0.91 dB, input return loss less than −8 dB, and output return loss less than −10 dB. Full article

We investigate the inorganic/organic hybrid vertical phototransistor (VPT) by integrating an atomic layer deposition-processed ZnO (ALD-ZnO) transistor with a prototype poly(3-hexylthiophene):[6,6]-phenyl-C₆₁-butyric acid methyl ester (P3HT:PC₆₁BM) blend organic photodiode (OPD) based on an encapsulated source electrode geometry, and discuss the device mechanism. Our preliminary studies on reference P3HT:PC₆₁BM OPDs show non-ohmic electron injection between the ALD-ZnO and P3HT:PC₆₁BM layers. However, the ALD-ZnO layer enables the accumulation of photogenerated holes under negative bias, which facilitates electron injection upon illumination and thereby enhances the external quantum efficiency (EQE). This mechanism underpins the photoresponse in the VPT. Furthermore, we demonstrate that the gate field in the VPT effectively modulates electron injection from the ALD-ZnO layer to the top OPD, resulting in the VPT operating as a non-ohmic OPD in the OFF state and as an ohmic OPD in the ON state. Benefiting from the unique transistor geometry and gate modulation capability, this hybrid VPT can achieve an EQE of 45,917%, a responsivity of 197 A/W, and a specific detectivity of 3.4 × 10¹² Jones under 532 nm illumination and low drain-source voltage (V_ds = 3 V) conditions. This transistor geometry also facilitates integration with various OPDs and the miniaturization of the ZnO channel area, offering an ideal basis for the development of highly efficient VPTs and high-resolution image sensors. Full article