A 328 nW, 0.45 V Current Differencing Transconductance Amplifier and Its Application in a Current-Mode Universal Filter

Abstract

This paper presents a low-voltage, low-power current differencing transconductance amplifier (CDTA) utilizing the bulk-driven MOS transistor technique in the subthreshold region for reduced voltage and power consumption. The proposed CDTA includes a z-copy terminal, which enhances its functionality in current-mode circuit applications. Designed in the Cadence Virtuoso environment using 0.18 µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC), the amplifier operates with a supply voltage of 0.45 V and consumes 328 nW of power, with a bias current set to 10 nA. The current bandwidth and offset of the CDTA are 35 kHz and 0.3 nA, respectively. To demonstrate its performance, the CDTA is applied in a current-mode universal filter, which can realize low-pass, band-pass, high-pass, band-stop, and all-pass responses within a single topology. This design eliminates issues related to inverting input signals, input signal matching, or the need for multiple input signals. Additionally, the natural frequency of these filtering functions can be electronically controlled. The low-pass filter achieves a dynamic range of 61 dB, with a total harmonic distortion of 0.8%.

1. Introduction

The current differencing transconductance amplifier (CDTA) is an active building block for current-mode signal processing applications [1,2]. It is widely used in various applications, including universal filters [2,3,4,5,6], sinusoidal oscillators [7,8,9], capacitance multipliers [10,11], precision rectifiers [12,13], memristor emulators [14,15,16], and chaotic oscillators [17]. However, traditional CDTA circuits are not suitable for low-voltage, low-power applications because their design does not inherently support efficient operation under these conditions. In modern electronic systems, both analog and digital circuits increasingly require low-voltage, low-power operation [18,19,20].

Several low-voltage, low-power CDTAs have been reported in the literature [21,22,23,24,25]. The circuit in [21] operates with a ±0.6 V supply voltage and consumes 143 μW of power using 0.18 µm TSMC technology. In [22], a ±1.4 V supply voltage is used, with a power consumption of 2.6 mW using 130 nm TSMC technology. The circuit in [23] operates with a ±0.8 V supply voltage and demonstrates low power consumption using 0.18 µm CMOS technology. Another design in [24] uses a ±1 V supply voltage and consumes 0.1 mW of power using 0.18 µm CMOS technology, while [25] operates with a 0.5 V supply voltage and consumes 1.05 μW using 0.18 µm CMOS technology.

Universal filters provide five fundamental filtering functions, low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), band-stop filter (BSF), and all-pass filter (APF), within a single topology. These filters are extensively used in communication, control, electronics, and instrumentation systems. For example, they are employed in crossover networks for high-fidelity loudspeakers and for tone decoding in touch-tone telephones [26,27]. Low-voltage, low-power universal filters are becoming increasingly important in biomedical systems [28]. In current-mode signal processing circuits, they offer several advantages, such as wide signal bandwidth and ease in adding and subtracting current signals. The ideal characteristics of current-mode filters include low input and high output impedance, no requirement for input signal matching, and no need for inverted input signals, thereby eliminating the need for additional circuitry. Several low-voltage, low-power current-mode universal filters have been proposed using various active devices, such as transconductance amplifiers [29,30,31] and voltage second-generation current conveyors (VCII) [32,33]. In recent years, reducing the supply voltage and power consumption of active elements has become essential, particularly for wearable and biomedical applications [34,35,36,37].

This paper presents a low-voltage, low-power CDTA that utilizes the bulk-driven MOS transistor technique, operating in the weak inversion region, to achieve its low-voltage and low-power characteristics. To demonstrate the advantages of the proposed CDTA, it is applied in current-mode universal filters. The proposed filter provides both non-inverting and inverting transfer functions for LPF, HPF, BPF, BSF, and APF, with low input and high output impedances, electronic tuning capability, no component-matching requirements, and no inverted input signals. Additionally, the natural frequency of the filter can be electronically controlled.

2. Circuit Description

2.1. Proposed 0.45 V CDTA

The electrical symbol of the CDTA is shown in Figure 1, and its equivalent circuit is illustrated in Figure 2. The ideal characteristics of the CDTA can be described as follows:

$$\begin{array}{c}{V}_p=V_n=0\\ I_z=I_{zc}=I_p-I_n\\ I_{x\pm }=g_m{V}_z\end{array}$$

(1)

where $g_m$ is the transconductance gain, $I_p$ and $I_n$ are the input currents, and $I_z$, $I_{zc}$, and $I_x$ are the output currents of the CDTA. The z_c-terminal of the CDTA is introduced to enhance its functionality in current-mode circuit applications. Therefore, in the design of the CDTA, the p- and n-terminals should ideally exhibit low impedance (ideally zero), while the z-, z_c-, and x-terminals should have high impedance (ideally infinite).

Figure 3 shows the CMOS implementation of the proposed CDTA. The circuit consists of a minus-type current conveyor (CCII−), a plus-type (CCII+), and a transconductance amplifier (TA). Both the CCII− and CCII+ form a current differencing unit (CDU) [21], with their output z connected to the TA. Even though the proposed CDTA is composed of known blocks, it includes a z-copy terminal, which enhances its functionality in current-mode circuits, and this feature is demonstrated in the proposed filter design.

The CCII+ functions as a current follower ($I_n$ = $I_{z+}$), while the CCII− functions as an inverted current follower ($I_p$ = $I_{z-}$). Since the outputs of the CCII+ and CCII− are connected at the z- terminal, the function of the CDU is realized, such that ($I_z=I_p-I_n)$. The z_c-terminal of the CDTA is implemented using complementary current mirrors.

The z-terminal of the CDU is connected to the non-inverting terminal of the TA, while the inverting terminal is grounded. When the z-terminal is loaded with an impedance, the current $I_z$ is converted into a voltage $V_z$. This voltage is then converted into a current $I_x$ at the x-terminal of the TA. Consequently, the ideal characteristic $I_x=g_m{V}_z$ of the CDTA is achieved.

The MOS differential pairs of the CCIIs are implemented using bulk-driven MOS transistors (M₁ and M₂). These differential pairs are loaded by transistors M₄ and M₅ and supplied by transistor M₃. This configuration is based on the flipped voltage follower (M₁–M₅), which enables operation with a minimal supply voltage. Consequently, the proposed CCII achieves a reduced minimum supply voltage, given by the sum of the source-gate voltage of M₃ and the drain-source voltage of M₄, as follows:

$$V_{DD\left(\mathrm{m}\mathrm{i}\mathrm{n}\right)}=\left(V_{SG-M3}+V_{DS\left(sat\right)-M4}\right)$$

(2)

where $V_{SG-M3}$ is equal to at least $V_{DS\left(sat\right)-M3}+V_{DS\left(sat\right)-M1}$. For circuit stability, Miller frequency compensation is applied using the capacitance C_C.

Assuming unity-gain current mirrors in the current conveyors, with identical transistors (M₆ = M₈ = M₉–M₁₁ and M₇ = M₁₂–M₁₅), the input resistance at the p-terminal ($r_p$), the input resistance at the n-terminal ($r_n$), and the output resistance at the x-terminal of the CDTA can be expressed, respectively, by

$$r_p=r_n={\displaystyle \frac{1}{g_{m6}\left(g_{mb1,2}\left(r_{ds2}‖r_{ds5}\right)\right)}}$$

(3)

$$r_z\cong {\displaystyle \frac{1}{2\left(g_{ds8,10}+{ g}_{ds12,14}\right)}}$$

(4)

$$r_{zc}\cong {\displaystyle \frac{1}{2\left(g_{ds9,11}+g_{ds13,15}\right)}}$$

(5)

$$r_x=\left(r_{ds8}\left(1+g_{m8}{r}_{ds8c}\right)\right)\left|\right| \left(r_{ds14}\left(1+g_{m14}{r}_{ds14c}\right)\right)$$

(6)

where $g_{mj}$, $g_{mbj}$, and $r_{dsj}$ are, respectively, the gate transconductance, bulk transconductance, and output resistance of the $j$th MOS transistors. It should be noted that the input resistances $r_p$ and $r_n$ of this CDTA structure are equal, since CCII− and CCII+ are identical.

The input-referred thermal noise of the differential amplifier is used to determine the input noise of the proposed CDTA, which can be expressed by

$${\overline{v}}_n^2\cong 2{\displaystyle \frac{8kT}{{3g}_{mb1}^2}}\left(g_{m1,2}+g_{m4,5}\right)$$

(7)

$k$ is the Boltzmann constant ($~$1.38 × 10⁻²³ J/K), and $T$ is the absolute temperature.

The TA of the CDTA is composed of a bulk-driven (BD) linearized differential pair and current mirrors. To achieve high output resistance and, consequently, improve the DC voltage gain, self-cascode current mirrors are utilized. The linearity of the input pair is enhanced through the use of BD transistors M₃ and M₄, which operate in the triode region [38]. The biasing current, $I_{set}$, is employed to adjust the transconductance $g_m$. Assuming unity-gain current mirrors, the DC transfer characteristic of the TA in the subthreshold region is given by

$$I_x=2I_{set}tanh\left(\eta {\displaystyle \frac{V_z}{2n_p{U}_T}}-{tanh}^{-1}\left[{\displaystyle \frac{1}{4m+1}}tanh\left(\eta {\displaystyle \frac{V_z}{2n_p{U}_T}}\right)\right]\right)$$

(8)

where $\eta$ = $g_{mb}/g_m$ is the bulk-to-gate transconductance ratio, $n_p$ is the subthreshold slope factor, $U_T$ is the thermal potential, and $m$ = (W/L_3,4)/(W/L_1,2) should be equal to 0.5 for optimal linearity in the weak inversion region [38]. The small-signal transconductance of the OTA is expressed as follows:

$$g_m=\eta ·{\displaystyle \frac{4m}{4m+1}}·{\displaystyle \frac{I_{set}}{n_p{U}_T}}$$

(9)

The DC voltage gain is

$$A_{vTA} ≌{ g}_m\left(g_{m8}{r}_{ds8}{r}_{ds8c}\right)\left|\right|\left(g_{m14}{r}_{ds14}{r}_{ds14c}\right)$$

(10)

Thus, the voltage gain is increased by employing self-cascode connections, which enhance the output resistance of the TA stage.

The circuit was designed as follows. The bias currents in the whole structure determine its power dissipation and should be chosen as low as possible. However, their minimum values in the input stage of the CCII are limited by thermal noise, which is a dominant source of noise in the proposed design. Taking into account (7), I_B was set to 50 nA, which provides the required level of noise. The biasing currents in all other branches were also set to I_B, which entailed $g_{m6}/g_{m1}$= 1 and unity-gain current mirrors in the structure. This resulted in $g_{m6}/g_{mb1}$ equal to about 3 at the operating point, which resulted in a moderate Miller compensation capacitor Cc. The W/L ratios of the transistors in the input stage were chosen to obtain V_DS = (V_DD − V_SS)/3 for each transistor in this stage at the operating point for the assumed biasing currents. For V_DD = 0.45 V, this means that V_SG3 = 0.3 V and V_GS1,2 = 0.3 V if the gate terminals of M₁ and M₂ are connected to the lowest potential, which is advantageous to decrease the bulk currents and W/L ratios of the input transistors. For the diode-connected p- and n-channel transistors in the current mirrors, |V_GS| were chosen to be equal to about mid supply. Such a choice gives a maximum voltage headroom for possible PVT variations and signal swing.

The biasing currents for the transconductance amplifier were chosen to obtain the required value of its transconductance (see (9)). The coefficient $m$ = (W/L_3,4)/(W/L_1,2) was chosen to be equal to 0.5 for optimal linearity. As previously, in the input stage the voltage drops across the main elements (biasing sources M_12,12c and M_13,13c and cascode current mirrors M_6,6c and M_7,7c), and the V_DS of the input transistors M₁ and M₂ were equal to around (V_DD − V_SS)/3 for nominal biasing currents to maximize voltage headroom for possible PVT variation, transconductance tuning, and signal swing. Regarding the self-cascode connections, the V_DS of the most bottom transistors (most upper transistors) operating in the triode region were chosen to be around 30 mV for nominal biasing currents. The biasing voltage V_B allowed obtaining proper values of the quiescent voltages at the sources of M₁ and M₂ for nominal biasing currents and moderate W/L ratios of the input transistors.

2.2. Proposed Current-Mode Analog Filter

The proposed current-mode analog filter, implemented using CDTAs, is shown in Figure 4. The circuit comprises two CDTAs and two grounded capacitors. The inclusion of grounded capacitors simplifies the compensation of parasitic passive components in the circuit.

When $I_1$ to $I_4$ serve as the input terminals and $I_{o1}$ to $I_{o6}$ as the output terminals, the current outputs of Figure 4 can be derived using the CDTA characteristics given in Equation (1) and nodal analysis as follows:

$$I_{o1}={\displaystyle \frac{s^2{C}_1{C}_2{I}_1-\left(s{C}_2{g}_{m1}+g_{m1}{g}_{m2}\right)I_2-s{C}_1{g}_{m2}{I}_3-s{C}_1{g}_{m2}{I}_4}{s^2{C}_1{C}_2+s{C}_2{g}_{m1}+g_{m1}{g}_{m2}}}$$

(11)

$$I_{o2}={\displaystyle \frac{s{C}_2{g}_{m1}{I}_1+s{C}_2{g}_{m1}{I}_2-g_{m1}{g}_{m2}{I}_3-g_{m1}{g}_{m2}{I}_4}{s^2{C}_1{C}_2+s{C}_2{g}_{m1}+g_{m1}{g}_{m2}}}$$

(12)

$$I_{o3}={\displaystyle \frac{s{C}_2{g}_{m1}{I}_1+s{C}_2{g}_{m1}{I}_2+\left(s^2{C}_1{C}_2{I}_1+s{C}_2{g}_{m2}\right)I_3-g_{m1}{g}_{m2}{I}_4}{s^2{C}_1{C}_2+s{C}_2{g}_{m1}+g_{m1}{g}_{m2}}}$$

(13)

$$I_{o4}={\displaystyle \frac{\left\{\begin{array}{c}{-g}_{m1}{g}_{m2}{I}_1-g_{m1}{g}_{m2}{I}_2-\left(s{C}_1{g}_{m2}+g_{m1}{g}_{m2}\right)I_3\\ -\left(s{C}_1{g}_{m2}+g_{m1}{g}_{m2}\right)I_4\end{array}\right\}}{s^2{C}_1{C}_2+s{C}_2{g}_{m1}+g_{m1}{g}_{m2}}}$$

(14)

$$I_{o5}={\displaystyle \frac{-s{C}_2{g}_{m1}{I}_1-s{C}_2{g}_{m1}{I}_2+g_{m1}{g}_{m2}{I}_3+g_{m1}{g}_{m2}{I}_4}{s^2{C}_1{C}_2+s{C}_2{g}_{m1}+g_{m1}{g}_{m2}}}$$

(15)

$$I_{o6}={\displaystyle \frac{\left\{\begin{array}{c}{g}_{m1}{g}_{m2}{I}_1+g_{m1}{g}_{m2}{I}_2+\left(s{C}_1{g}_{m2}+g_{m1}{g}_{m2}\right)I_3\\ +\left(s{C}_1{g}_{m2}+g_{m1}{g}_{m2}\right)I_4\end{array}\right\}}{s^2{C}_1{C}_2+s{C}_2{g}_{m1}+g_{m1}{g}_{m2}}}$$

(16)

Here, $g_{m1}$ and $g_{m2}$ refer to the transconductance of the first and second CDTA blocks employed in the proposed filter architecture.

Table 1. Obtaining variant filtering function of current-mode analog filter.

Filtering Function		Output	Input	Transfer Functions
LPF	Non-inverting	$I_{o5}$	$I_4$	$g_{m1}{g}_{m2}/D\left(s\right)$
		$I_{o6}$	$I_1$$\mathrm{or} I_2$	$g_{m1}{g}_{m2}/D\left(s\right)$
		${I_{o1}+I}_{o6}$	$I_3$	$g_{m1}{g}_{m2}/D\left(s\right)$
	Inverting	$I_{o2}$	$I_3$$\mathrm{or} I_4$	$-g_{m1}{g}_{m2}/D\left(s\right)$
		$I_{o3}$	$I_4$	$-g_{m1}{g}_{m2}/D\left(s\right)$
		$I_{o4}$	$I_1$$\mathrm{or} I_2$	$-g_{m1}{g}_{m2}/D\left(s\right)$
		${I_{o1}+I}_{o2}$	$I_2$	$-g_{m1}{g}_{m2}/D\left(s\right)$
HPF	Non-inverting	$I_{o1}$	$I_1$	$s^2{C}_1{C}_2/D\left(s\right)$
		${I_{o1}+I}_{o3}$	$I_3$	$s^2{C}_1{C}_2/D\left(s\right)$
BPF	Non-inverting	$I_{o2}$	$I_1$$\mathrm{or} I_2$	$s{C}_2{g}_{m1}/D\left(s\right)$
		$I_{o3}$	$I_1$$\mathrm{or} I_2$	$s{C}_2{g}_{m1}/D\left(s\right)$
		${I_{o2}+I}_{o6}$	$I_3$	$s{C}_1{g}_{m2}/D\left(s\right)$
	Inverting	$I_{o1}$	$I_3$$\mathrm{or} I_4$	$s{C}_1{g}_{m2}/D\left(s\right)$
		$I_{o5}$	$I_1$$\mathrm{or} I_2$	$s{C}_1{g}_{m2}/D\left(s\right)$
		${I_{o1}+I}_{o6}$	$I_2$	$s{C}_2{g}_{m1}/D\left(s\right)$
		${I_{o4}+I}_{o5}$	$I_3$	$s{C}_1{g}_{m2}/D\left(s\right)$
BSF	Non-inverting	${I_{o1}+I}_{o6}$	$I_1$	$\left(s^2{C}_1{C}_2+g_{m1}{g}_{m2}\right)/D\left(s\right)$
		${I_{o1}+I}_{o3}+I_{o5}$	$I_3$	$\left(s^2{C}_1{C}_2+g_{m1}{g}_{m2}\right)/D\left(s\right)$
APF	Non-inverting	${I_{o1}+I}_{o5}+I_{o6}$	$I_1$	$\left(s^2{C}_1{C}_2-s{C}_2{g}_{m1}+g_{m1}{g}_{m2}\right)/D\left(s\right)$

Note: $D\left(s\right)=s^2{C}_1{C}_2+s{C}_2{g}_{m1}+g_{m1}{g}_{m2}.$

demonstrates that five standard filtering functions, LPF, HPF, BPF, BSF, and APF, can be realized using a single topology, providing a total of 19 transfer functions. These filtering functions are achieved with a single input signal, eliminating the need for multiple input signals that would require additional components, such as a multiple-input current mirror. Furthermore, the output signals can be directly connected without the need for buffer circuits. As a result, the proposed current-mode analog filter can efficiently realize all five standard filtering functions without requiring any extra circuitry. To implement these filtering functions, inverting-type input signals are not required, thereby eliminating the need for additional inverting current amplifiers. The output terminals $I_{o1}$, $I_{o2}$, $I_{o3}$, $I_{o4}$, $I_{o5}$, and $I_{o6}$ exhibit high impedance, allowing them to be directly connected to the next stage without the need for buffer circuits.

The parameters ${\omega }_o$ and $Q$ can be expressed, respectively, as follows:

$${\omega }_o=\sqrt{{\displaystyle \frac{g_{m1}{g}_{m2}}{C_1{C}_2}}}$$

(17)

$$Q=\sqrt{{\displaystyle \frac{g_{m2}{C}_1}{g_{m1}{C}_2}}}$$

(18)

It is evident from Equations (17) and (18) that the parameter ${\omega }_o$ can be controlled by adjusting the transconductance $g_m$ (where $g_m$ = $g_{m1}$ = $g_{m2}$), while the parameter $Q$ can be adjusted by the ratio $C_1$/$C_2$.

2.3. Non-Ideal Analysis

The non-ideal characteristics of the CDTA are taken into account in the analysis of the proposed universal filter. The parasitic current gains between the p- and z-terminals and the n- and z-terminals, along with the non-ideal transconductance, are taken into account. Parasitic impedances are neglected, as the circuit operates at low frequencies typical for biomedical signals. In the non-ideal case, the behavior of the CDTA can be represented, as shown in [2], by the following equation:

$$\left.\begin{array}{c}{V}_p=V_n=0\\ I_z={\alpha }_p{I}_p-{\alpha }_n{I}_n\\ I_x=g_{mn}{V}_z\end{array}\right\}$$

(19)

Here, ${\alpha }_p=1-{\epsilon }_p$, where ${\epsilon }_p\left(\left|{\epsilon }_p\right|\ll 1\right)$ represents the parasitic current gain between the p- and z-terminals of the CDTA. Similarly, ${\alpha }_n=1-{\epsilon }_n$, where ${\epsilon }_n\left(\left|{\epsilon }_n\right|\ll 1\right)$ denotes the parasitic current gain between the n- and z-terminals of the CDTA. Ideally, ${\alpha }_p$, and ${\alpha }_n$ are all equal to unity. The parameter $g_{mn}$ represents the non-ideal transconductance.

The non-ideal transconductance $g_{mn}$ of the TA at a frequency near its cut-off can be expressed [39] as follows:

$$g_{mn}\left(s\right)\cong g_m\left(1-{sT}_o\right)$$

(20)

where $T_o=1/{\omega }_{gm}$ and ${\omega }_{gm}$ represents the first pole frequency of $g_m$.

Using (19) and nodal analysis, the denominator of the transfer functions can be rewritten as follows:

$$D\left(s\right)=s^2{C}_1{C}_2+s{C}_2{g}_{m1}{\alpha }_{p1}+g_{m1}{g}_{m2}{\alpha }_{p1}{\alpha }_{n2}$$

(21)

where ${\alpha }_{pj}$, and ${\alpha }_{nj}$ are the parasitic current gains of the $j$th CDTA.

Considering the non-idealities in (20) for $g_{m1}$ and $g_{m2}$, the non-idealities can be approximated as $g_{mn1}\left(s\right)\cong g_{m1}\left(1-s{T}_{o1}\right)$ and $g_{mn2}\left(s\right)\cong g_{m2}\left(1-s{T}_{o2}\right)$. The denominator $D\left(s\right)$ of the transfer functions of the filters can be then written as follows:

$$\begin{gathered} D\left(s\right)=s^2{C}_1{C}_2\left(1-{\displaystyle \frac{C_2{g}_{m1}{\alpha }_{p1}{T}_{o1}-g_{m1}{g}_{m2}{\alpha }_{p1}{\alpha }_{n2}{T}_{o1}{T}_{o2}}{C_1{C}_2}}\right) \\ +s{C}_2{g}_{m1}{\alpha }_{p1}\left(1-{\displaystyle \frac{g_{m1}{g}_{m2}{\alpha }_{n2}\left(T_{o1}+T_{o2}\right)}{C_2{g}_{m1}}}\right)+g_{m1}{g}_{m2}{\alpha }_{p1}{\alpha }_{n2} \end{gathered}$$

(22)

From (22), the non-ideal effects of the transconductances $g_{m1}$ and $g_{m2}$ can be mitigated by satisfying the following conditions:

$${\displaystyle \frac{C_2{g}_{m1}{\alpha }_{p1}{T}_{o1}-g_{m1}{g}_{m2}{\alpha }_{p1}{\alpha }_{n2}{T}_{o1}{T}_{o2}}{C_1{C}_2}}\ll 1$$

(23)

$${\displaystyle \frac{g_{m1}{g}_{m2}{\alpha }_{n2}\left(T_{o1}+T_{o2}\right)}{C_2{g}_{m1}}}\ll 1$$

(24)

These conditions can be achieved by appropriately selecting the values of $g_{m1}$ and $g_{m2}$ and capacitances $C_1$ and $C_2$.

In the non-ideal case, the natural frequency and quality factor of the proposed filter become

$${\omega }_o=\sqrt{{\displaystyle \frac{g_{m1}{g}_{m2}{\alpha }_{p1}{\alpha }_{n2}}{C_1{C}_2}}}$$

(25)

$$Q=\sqrt{{\displaystyle \frac{g_{m2}{C}_1{\alpha }_{n2}}{g_{m1}{C}_2{\alpha }_{p1}}}}$$

(26)

3. Results

The simulation results were generated using the Cadence Virtuoso program using 0.18 µm CMOS technology from TSMC. The transistor aspect ratio of the CMOS structure of the CDTA is shown in

Table 2. Transistor aspect ratios of the CDTA.

CCII	W/L (µm/µm)	TA	W/L (µm/µm)
M1, M2	40/3	M1, M2	2 × 15/1
M3, M6, M8, M9–M11	50/3	M5–M11	2 × 10/1
MB, M4, M5, M7, M12–M15	30/3	M3, M4	15/1
		M5c–M11c	10/1
		M12–M19	2 × 15/1
		M12c–M19c	15/1
Capacitor: CC = 5 pF

. The bias current for the CCII ($I_B$) was 50 nA, and the bias voltage for the TA ($V_B$) was −50 mV. The voltage supply was 450 mV (±225 mV), and the power consumption of the CDTA shown in Figure 3, with $I_{set}$ = 10 nA, was 328 nW.

Figure 5 shows the CDU DC characteristics of the $I_z$ versus $I_p$ and $I_z$ versus $I_n$ of the CDTA for $V_{z }$= 0. It is evident that the circuit can process signals up to 50 nA, which is equal to the bias current of the CCII. Figure 6 demonstrates the TA DC characteristics of the $I_{x+}$ versus $V_z$ with various $I_{set}$ of the TA. The circuit is capable of processing input voltages in the range of ±200 mV while the voltage supply is ±225 mV, confirming the circuit’s ability to operate under low supply voltages. The overall performance of the proposed CDTA is summarized in

Table 3. Performance data of the proposed CDTA.

Parameters	Value
Supply voltage	0.45 V
Bias current IB	50 nA
Technology	0.18 μm
DC current swings: $I_p$$, I_n$	±50 nA
Current gains: $I_z$$/I_p$$, I_z$$/I_n$	0.988, 0.999
Offset current $I_z$ $(I_p$ $=I_n$ = 0)	0.3 nA
−3 dB bandwidth: $I_z$$/I_p$$, I_z$$/I_n$	[135, 124] kHz
−3 dB bandwidth of $g_m$ $(I_{set}$ = 10 nA)	76 kHz
$z_p$$, z_n$	19 kΩ
$z_z$	62.27 MΩ
$z_{x+}$$, z_{x-}$	[861, 792] MΩ
$g_m$$(I_{set}$ = [5, 10, 15, 20] nA)	[34.5, 67.5, 99.5, 130.6] nS
Power dissipation$(I_{set}$ = 10 nA)	328 nW

. Compared with the previous CDTAs in [21,22,23,24,25], the proposed structure provides a low supply voltage and low power consumption.

For the filter application in Figure 4, the capacitance values were chosen as $C_1$ = $C_2$ = 20 pF. With $I_{set}$ = 60 nA, the frequency response of the filter is shown in Figure 7, where the simulated cut-off frequency was 2.66 kHz, the quality factor was $\cong$1, and the power consumption of the filter was 1.098 µW.

Figure 8 demonstrates the electronic tuning capability of the filter using different values of $I_{set}$ = (30, 60, and 90) nA. The corresponding cut-off frequencies were (1.47, 2.66, and 3.58) kHz, respectively.

To confirm the stability and robustness of the filter design, both Monte Carlo (MC) analysis and process, voltage, temperature (PVT) corner analysis were performed. The MC analysis was run with 200 cycles, including process and mismatch variations. Regarding the PVT analysis, the process corners were fast–fast (FF), slow–fast (SF), fast–slow (FS), and slow–slow (SS). The voltage supply corners were selected at 400 mV and 500 mV, and the temperature corners were −10 °C and 60 °C. As shown in Figure 9, the curves overlap in the case of MC and process corners, confirming the proper design of the MOS structure. The variation in the voltage corner at 400 mV results in a reduced bias current and cut-off frequency. In the case of temperature variations, the slight deviation in the cut-off frequency at −10 °C is expected due to the sensitivity of the MOS transistor operating in the subthreshold region to temperature. The circuit offers advantages in electronic tunability. As a result, deviations caused by temperature, process variations, and voltage supply corners can be easily compensated by adjusting the filter’s setting current, allowing for the readjustment of the required cut-off frequency.

Figure 10a shows the transient response of the LPF when a sine wave input signal with an amplitude of 20 pA at 10 Hz is applied to the filter input, with $I_{set}$ = 60 nA. The output signal spectrum with total harmonic distortion (THD) shown in Figure 10b confirms a low distortion of 0.16% in the output signal.

Figure 11 shows the THD with various corners versus the amplitude of the input signal at 10 Hz. The nominal THD is less than 0.8% for a 40 nA amplitude of the input signal, confirming the low THD of the proposed filter. The equivalent output current noise of the LPF with various corners is shown in Figure 12. The integrated noise in the filter band from 1 to 2.66 kHz was 42.35 pA, resulting in dynamic range (DR) of 61 dB for 0.8% THD.

The proposed current-mode universal filter was compared with previously developed low-voltage universal filters in [25,29,31,32], as shown in

Table 4. Comparison of the proposed current-mode universal filter with those of some previous filters.

Factor	Proposed 2025	[25] 2024	[29] 2019	[31] 2022	[32] 2019
Number of active devices	2-CDTA	4-CDTA	8-INV	8-OTA	3-VCII, 1-ICB
Realization	0.18 µm CMOS	0.18 µm CMOS	32 nm CNTFET	0.18 µm CMOS	0.18 µm CMOS
Number of passive devices	2-C	2-C, 2-R	2-C	2-C	2-C, 3-R
Filter mode	CM (MIMO)	CM (MISO)	CM (MISO)	MM (MIMO)	TIM (SIMO)
Total number of filter responses	19	12	5 (CM)	5 (CM)	5
$\mathrm{Electronic} \mathrm{control} \mathrm{of} {\omega }_o$	Yes	Yes	Yes	Yes	No
All passive devices grounded	Yes	Yes	Yes	Yes	No
Without inverted/double input conditions/input-matching condition	Yes	No	No	No	Yes
High-output impedance	Yes	Yes	Yes	Yes	-
Power supply (V)	0.45	0.5	±0.2	±0.3	±0.9
Power dissipation (μW)	1.098	3.39	447 × 10−3	5.77	1.47 × 103
Natural frequency (Hz)	2.66 × 103	104.7	1.1 × 106	5 × 103	1.5 × 106
Integrated noise (pA)	42.35	38.32	-	-	-
THD (%)	0.8@40 nA	0.936@150 nA	>1.16	0.8@100 nA	3.6@5 μA
Dynamic range (dB)	61	68.86	-	53.2	-
Verification of result	Sim.	Sim.	Sim.	Sim.	Sim.

Note: ICB = Inverting Current Buffer, INV = Inverter, CNTFET = Carbon Nanotube Field-Effect Transistor, MM = Multi-Mode, TIM = Transimpedance Mode, MIMO = Multiple-Input Multiple-Output, MISO = Multiple-Input Single-Output, SIMO = Single-Input Multiple-Output.

. Compared to these earlier works, the proposed filter provides the most transfer functions among the five standard filtering functions. Unlike the MISO filters in [25,29,31], the proposed filter does not require an input-matching condition (i.e., $I_{in}$ = $I_{in1}$ = $I_{in2}$ = $I_{in3}$ [29]) or a double-input condition (i.e., $I_{in}$ = ${2I}_{in1}$ = $-I_{in2}$ [31]). The VCII-based filter in [32] lacks electronic tuning capability and suffers from the use of a floating resistor compared to the proposed topology. However, the universal filter in [29] achieves the lowest supply voltage and power consumption, made possible by a specialized technology (32 nm CNTFET). In addition, the filters in [25,31] exhibit better THD and the filter in [25] demonstrates better DR compared to the proposed filter; however, they consume more power.

4. Conclusions

This research presents a low-voltage, low-power CDTA, implemented using the bulk-driven MOS transistor technique to achieve a low supply voltage. The proposed CDTA is applied in a current-mode universal filter to demonstrate its performance. This universal filter can realize transfer functions for low-pass, band-pass, high-pass, band-stop, and all-pass responses within a single topology. All transfer functions are implemented with high output impedance, which is essential for current-mode circuits. The circuit addresses challenges related to inverting input signals, input signal matching, and the need for multiple input signals. Additionally, the natural frequency of the filters can be electronically controlled, providing an easy method to compensate for temperature variations. The CDTA and its application were designed using 0.18 µm CMOS technology.