Search Results (42)

This article presents an efficient non-isolated DC-DC hybrid converter for direct large-ratio step-down applications such as data centers. The converter topology employs a three-level-assisted Dickson switched capacitor network and interleaved dual inductors, significantly mitigating voltage swings at the switching nodes. As a result, the conduction duration of rectifying switches is substantially extended. This configuration is suitable for both odd- and even-order converters, achieving self-balancing of the flying capacitor voltages and inductor currents. To address uneven interleaved inductor currents, a duty-cycle-matching-based current distribution method is proposed to ensure equal current sharing and facilitate loss transfer between inductors. Additionally, an intrinsic charge-ratio-based method for capacitance optimization is introduced to achieve quasi-complete soft charging of the flying capacitors. This method eliminates surge currents during reconfiguration of the capacitor network, reduces losses, and enhances the capacitor utilization. Operating at 300 kHz, the prototype achieves high-ratio voltage conversion from 48 V to 0.5–2.0 V, with a maximum output current of 30 A. It attains a peak efficiency of 91.96% and a power density of 944.88 W/in³. Quasi-complete soft charging of the flying capacitors results in an approximate 2.94% improvement in the conversion efficiency. Full article

In this article, a new high step-up interleaved DC–DC converter is presented for renewable energy systems. The converter circuit is based on the interleaved two-phase boost converter and integrates a voltage-lift capacitor and a voltage multiplier cell. A high voltage gain of the converter can be achieved with a reasonable duty ratio and the voltage stresses of semiconductor devices are reduced. Because of low voltage stress, the switches with low on-resistance and the diodes with low forward voltage drops can be adopted to minimize the conduction losses. Additionally, the switching losses are reduced because the switches are turned on under zero-current switching (ZCS) conditions. Due to the existence of leakage inductances of the coupled inductors, the diode reverse-recovery problem is alleviated. Moreover, the leakage energy is recycled and the voltage spikes during switch turn-off are avoided. The parallel input architecture and interleaved operation reduce the input current ripple. The operating principles, steady-state characteristics, and design considerations of the presented converter are proposed in detail. Furthermore, a closed-loop control is designed to maintain a well-regulated output voltage despite variations in input voltage and output load. A prototype converter with a rated 1000 W output power is realized for demonstration. Finally, experimental results show the converter effectiveness and verify the theoretical analysis. Full article

Power electronic converters are important elements of many modern devices. Therefore, there is a need for a thorough analysis of their behavior and the ability to properly control them. Typically, the converter’s dynamics are investigated using the small-signal averaging method, which does not provide detailed information about the converter. In particular, it does not account for the switching ripple effect. In this paper, a novel switched state–space model of the interleaved step-up DC–DC converter is introduced. That model incorporates high-frequency information, which allows for a more in-depth dynamics analysis. The results, i.e., step and frequency responses, obtained from both theoretical models are compared to the interleaved step-up DC–DC converter model implemented in PSpice ver. 16.6 from Cadence Design Systems. Full article

Hybrid electric vehicles (HEVs) and fuel cell electric vehicles (FCEVs) utilize boost converters to gain a higher voltage than the battery. Interleaved boost converters are suitable for low input voltage, large input current, miniaturization, and high-efficiency applications. This paper proposes a novel linear quadratic integral (LQI) control for the interleaved boost converters. First, the small-signal model of the interleaved-boost converter is derived. In the proposed method, an output voltage and a current signal error between two-phase input currents are selected to control not only the output voltage but also a balance between two-phase input currents. Furthermore, steady-state characteristics in terms of the output voltage and the input current are demonstrated by experiments and simulations using an experimental apparatus with a rated power of 700 W. The validity of the proposed method’s tracking performance and load response is demonstrated by comparing it with that of the conventional PI control. The tracking performance of the LQI control for the 40 V step response has a ten times faster response than that of the PI control. Also, the experimental results demonstrate that the proposed method maintains a constant output voltage for a 300 W load step while the PI control varies by 10 V during 70 ms. Additionally, the proposed method has an excellent disturbance rejection. Full article

In this article, a new non-isolated interleaved DC–DC converter is proposed to provide a high voltage conversion ratio in renewable energy systems. The converter configuration is composed of a two-phase interleaved boost converter integrating a voltage-lift capacitor and three-winding coupled inductor-based voltage multiplier modules to achieve high step-up voltage conversion and reduce voltage stresses on the semiconductors (switches and diodes). The converter can achieve a high voltage conversion ratio when working at a proper duty ratio. The voltage stresses on the switches are significantly lower than the output voltage, which enables engineers to adopt low-voltage-rating MOSFETs with low on-state resistance. The switches can turn on under zero-current switching (ZCS) conditions because of the leakage inductor series reducing switching losses. Some diodes can naturally turn off under ZCS conditions to alleviate the reverse–recovery issue and to reduce reverse–recovery losses. The input current has small ripples due to the interleaved operation. The leakage inductor energy is recycled and voltage spikes on the switches are avoided. The proposed converter is suitable for applications in which high voltage gain, high efficiency and high power are required. The principle of operation, steady-state analysis and design considerations of the proposed converter are described in detail. In addition, a closed-loop controller is designed to reduce the effect of input voltage fluctuation and load change on the output voltage. Finally, a 1000 W laboratory prototype is built and tested. The theoretical analysis and the performance of the proposed converter were validated by the experimental results. Full article

In this paper, a thermoelectric conversion system for multiple heat sources is proposed. For design convenience, the overall system employs only a single-stage converter. Such a converter uses coupling inductors and switched capacitors to increase the voltage gain. In order to reduce the high-frequency voltage oscillation of the turn-off of the main switches created from leakage inductors, two active clamp circuits with zero voltage switching (ZVS) turn-on are employed. By doing so, although the current-sharing device with interleave control is embedded in the proposed converter, the input currents can be unequal. Therefore, the inputs of the converter can operate under individual maximum power points and transfer the energy from different thermoelectric generators (TGs) to a single load. Furthermore, the main switches have low voltage stress during the turn-off period. As for the maximum power point tracking (MPPT) method, it utilizes a three-point-weighting method to improve the tracking stability. In addition, the number of inputs of this converter can be extended. The MPPT simulation is presented to verify the feasibility as well as several experimental waveforms to demonstrate the effectiveness. The field programmable gate array (FPGA) is used as a digital control kernel to control the thermoelectric conversion system. Full article

This paper presents the converter design of a single-phase non-isolated step-down controlled rectifier for power factor improvement and output voltage regulation. The converter consists of a full-bridge diode rectifier and a DC–DC interleaved buck converter of two or more switching cells that has an LC filter in its input. It is proposed that the interleaved switching cells operate in discontinuous conduction mode and the current through the input LC filter be continuous, avoiding switching frequency components to be injected into the grid. The controller, which has a simple structure and a small number of sensors, allows the system to achieve a high power factor. It also regulates the output voltage to a constant reference. An experimental prototype is built and tested to validate the analysis and proposed design. The closed-loop converter is evaluated both in a steady state and in transient conditions. At steady state, the converter achieves a power factor above 0.9 with a maximum of 45.4% THD at 110.1W. The main contributions of this paper are guidelines for the design of the converter, open-loop analysis, and converter control. Full article

Traffic sign detection is a research hotspot in advanced assisted driving systems, given the complex background, light transformation, and scale changes of traffic sign targets, as well as the problems of slow result acquisition and low accuracy of existing detection methods. To solve the above problems, this paper proposes a traffic sign detection method based on a lightweight multiscale feature fusion network. Since a lightweight network model is simple and has fewer parameters, it can greatly improve the detection speed of a target. To learn more target features and improve the generalization ability of the model, a multiscale feature fusion method can be used to improve recognition accuracy during training. Firstly, MobileNetV3 was selected as the backbone network, a new spatial attention mechanism was introduced, and a spatial attention branch and a channel attention branch were constructed to obtain a mixed attention weight map. Secondly, a feature-interleaving module was constructed to convert the single-scale feature map of the specified layer into a multiscale feature fusion map to realize the combined encoding of high-level semantic information and low-level semantic information. Then, a feature extraction base network for lightweight multiscale feature fusion with an attention mechanism based on the above steps was constructed. Finally, a key-point detection network was constructed to output the location information, bias information, and category probability of the center points of traffic signs to achieve the detection and recognition of traffic signs. The model was trained, validated, and tested using TT100K datasets, and the detection accuracy of 36 common categories of traffic signs reached more than 85%, among which the detection accuracy of five categories exceeded 95%. The results showed that, compared with the traditional methods of Faster R-CNN, CornerNet, and CenterNet, traffic sign detection based on a lightweight multiscale feature fusion network had obvious advantages in the speed and accuracy of recognition, significantly improved the detection performance for small targets, and achieved a better real-time performance. Full article

With the great improvement in data transmission rate requirements, the analog-to-digital converter (ADC)-based wireline receiver has received more attention due to its flexible and powerful equalization capability. Time-interleaved ADC (TI-ADC) is the most commonly used architecture in high-speed ADC-based receivers. One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The traditional skew detection and calibration circuits consume substantial power and area of the receiver system. In this article, we propose a novel calibration method using the autocorrelation principle combined with an existing Mueller–Müller clock and data recovery circuit (MM-CDR). This new method reuses the existing error-direction information of the MM-CDR in the ADC-based wireline receiver and combines the autocorrelation principle to obtain the timing mismatch information in the TI-ADC without adding an additional skew deviation extraction circuit, which greatly reduces the area and power consumption. In order to demonstrate the effectiveness and superiority of our skew calibration method, we designed a complete ADC-based wireline receiver circuit using the 28 nm CMOS technology. The simulation results show that our proposed calibration method could obtain 0.193 sensitivity per 1% skew, which was superior to traditional calibration methods. To verify the speed and accuracy of the convergence of our calibration method, the initial skews were set to +0.4 ps, +0.2 ps, −0.59 ps, and 0 ps for our 4 × 8 TI-ADC; the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) of the ADC were increased from 37.24 dB and 31.28 dB to 48.07 dB and 34.56 dB, respectively, after timing calibration with a 50 fs step. In order to compare the area and power consumption required by different skew calibration methods, we synthesized the expressions of various methods using the 28 nm CMOS technology, and the area and power consumption of our proposed skew calibration loop were 695 μm² and 0.126 mW, respectively, which were the smallest among these methods. Full article

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm² active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s. Full article

In this paper, a Power Factor Correction (PFC) application, based on the novel power stage topology named Independent Double-Boost Interleaved Converter (IDBIC), has been analyzed. The novelty of the proposed PFC rectifier is based on the sum of capabilities, such as supplying three independent output voltage levels with interleaved operation at the input and high voltage gain. The hardware used within this application consists of an AC input L-C-L filter, a single-phase bridge rectifier, the IDBIC power stage, output capacitors group and a group of variable high-power rheostats (resistors) group as DC load. The main purpose of the carried study was to highlight the advantages and disadvantages of the novel power stage topology in the context of a green and modern AC to DC conversion solution. Nowadays, a high level of the efficiency and power factor have become a mandatory feature for the AC to DC conversion solutions to satisfy the international electrical standards. Thus, considering the modern electrical standards and recommendations, the current study tries to better depict the working steps and principles of the modern power stage topology within an AC to DC conversion application. The behavior of the considered power stage described in different detailed working steps (such as the Discontinuous Conduction Mode and Continuous Conduction Mode) may help understand how the energy conversions process of AC to DC becomes more efficient. The high output voltage gain of the considered power stage is the key feature in the Power Factor Correction process. With such a feature, the AC to DC conversion solution/application can also operate at lower input AC voltages (such as 90 [V] and 110 [V]). The proposed solution can be successfully used in the electric vehicle (automotive field) and high-power electrical traction (e.g., trains, high power electrical machines and drives). The same solution can also be used successfully in fast battery charging applications and chemical electrolysis processes. Full article

This paper examines the design and analysis of DC–DC converters for high-power and low-voltage applications such as renewable energy sources (RESs) and comparisons between converters based on switch stresses and efficiency. The RESs including photovoltaic arrays and fuel cell stacks must have enhanced output voltages, such as 380 V DC in the case of a full bridge inverter or 760 V DC in the case of a half bridge inverter, in order to interface with the 220 V AC grid-connected power system. One of the primary difficulties in developing renewable energy systems is enhancing DC–DC converters’ efficiency to enable high step-up voltage conversion with high efficiency and low voltage stress. In the present work, the efficiency, current, and voltage stress of switches of an isolated Flyback boost converter, simple DC–DC Boost converter, and an Interleaved boost converter, are explored and studied relatively. The most suitable and optimized options with a high efficiency and low switching stress are investigated. The more suitable topology is designed and analyzed for the switch technology based on the Silicon-Metal Oxide Semiconductor Field Effect Transistor (Si-MOSFET) and the Gallium Nitride-High Electron Mobility Transistor (GaN-HEMT). The Analytical approach is analyzed in this paper based on efficiency and switching stress. It is explored that GaN HEMT based Flyback boost converter is the best. Finally, the future direction for further improving the efficiency of the proposed boost converter is investigated. Full article

The recent growth of battery-powered applications has increased the need for high-efficiency step-up dc-dc converters. The step-up conversion is commonly used in several applications, such as electric vehicle (EV); plug-in hybrid electric vehicles (PHEV); photovoltaic (PV) systems; uninterruptible power supplies (UPS); and fuel cell systems. The input current is shared among inductors by paralleling the converters; resulting in high reliability and efficiency. In this paper; a detailed analysis for reducing power loss and improving efficiency is discussed. In continuous conduction mode; the converters are tested with a constant duty cycle of 50%. The multi phase interleaved boost converter (MPIBC) is controlled by interleaved switching techniques; which have the same switching frequency but phases are shifted. The efficiency of the six phase IBC model is 93.82% and 95.74% for an input voltage of 20 V and 200 V, respectively. The presented six phase MPIBC is validated by comparing it with the existing six phase IBC. The result shows that the presented converter is better than the existing converter. The prototype of the two phase and six phase IBC is fabricated to test the performance. It is found that the output power at the load end is highest for the 5 kHz switching frequency. Full article

This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 mm² and consumes 432 mW power consumption. Full article

DC-DC boost converters are necessary to extract power from solar panels. The output voltage from these panels is far lower than the utility voltage levels. One of the main functions of the boost converter is to provide a considerable step-up gain to interface the panel to the utility lines. There are several techniques used to boost the low panel voltage. Some of the issues faced by these topologies are a high duty ratio operation, complex design with multiple active switches and discontinuous input current that affects the power drawn from the panel. This paper presents a boost converter topology that combines the advantages of an interleaved structure, a voltage lift capacitor and a passive voltage multiplier network. A mathematical analysis of the proposed converter during its various modes of operation is presented. A 100 W prototype of the proposed converter is designed and tested. The prototype is controlled by a PIC16F18455 microcontroller. The converter is capable of achieving a gain of 10 without operating at extremely high duty ratios. The voltage stress of the switch is far lower than the maximum output voltage. Full article