Analysis and Design of a New High Voltage Gain Interleaved DC–DC Converter with Three-Winding Coupled Inductors for Renewable Energy Systems

Abstract

In this article, a new non-isolated interleaved DC–DC converter is proposed to provide a high voltage conversion ratio in renewable energy systems. The converter configuration is composed of a two-phase interleaved boost converter integrating a voltage-lift capacitor and three-winding coupled inductor-based voltage multiplier modules to achieve high step-up voltage conversion and reduce voltage stresses on the semiconductors (switches and diodes). The converter can achieve a high voltage conversion ratio when working at a proper duty ratio. The voltage stresses on the switches are significantly lower than the output voltage, which enables engineers to adopt low-voltage-rating MOSFETs with low on-state resistance. The switches can turn on under zero-current switching (ZCS) conditions because of the leakage inductor series reducing switching losses. Some diodes can naturally turn off under ZCS conditions to alleviate the reverse–recovery issue and to reduce reverse–recovery losses. The input current has small ripples due to the interleaved operation. The leakage inductor energy is recycled and voltage spikes on the switches are avoided. The proposed converter is suitable for applications in which high voltage gain, high efficiency and high power are required. The principle of operation, steady-state analysis and design considerations of the proposed converter are described in detail. In addition, a closed-loop controller is designed to reduce the effect of input voltage fluctuation and load change on the output voltage. Finally, a 1000 W laboratory prototype is built and tested. The theoretical analysis and the performance of the proposed converter were validated by the experimental results.

1. Introduction

The demand for renewable energies, such as fuel cells and photovoltaic arrays, has dramatically increased for electricity generation because of the shortage of fossil fuels and the growing climate change impacts [1]. The renewable energy system is shown in Figure 1. A 380 or 400 V_dc dc-bus voltage is necessary for grid-connected applications if the line voltage of the utility grid is 220 V_ac. However, the output voltages of fuel cells and photovoltaic arrays are typically lower than 50 V. Therefore, DC–DC converters with high voltage conversion ratios are necessary to boost the low voltages of green energy resources to the high dc-bus voltage required in renewable energy system applications.

High voltage gain DC–DC converters can be mainly divided into two types: isolated and non-isolated. The traditional isolated type adjusts the transformer turns ratio to obtain high voltage gain, such as in push–pull, half-bridge, forward and flyback DC–DC converters. However, high leakage inductance derived from the high turns ratio may result in high voltage spikes and poor efficiency. A boost converter of the non-isolated type can, theoretically, achieve high voltage gain by operating at a very large duty ratio. However, the voltage conversion ratio is practically limited due to parasitic elements [2]. In general, high voltage rated MOSFETs have the characteristic of high on-state resistance R_DS(ON), and the high voltage-rated diodes have high forward voltage drop. Therefore, a high voltage gain DC–DC converter, having low voltage stresses on the switches and diodes, can contribute to reducing conduction losses. Consequently, low semiconductor voltage stress is important for efficiency considerations in the new high voltage gain converter topology.

In recent years, high voltage gain DC–DC converters have been researched in depth by means of different voltage-boosting techniques. The most widely used method is based on the coupled inductor technique. In [3], a coupled inductor-based soft switched high step-up converter with a voltage multiplier cell was proposed for DC microgrid applications. In [4], five categories of high step-up coupled-inductor boost converters were reviewed. Two configurations for two- and three-winding coupled inductor-based high step-up DC–DC converters were proposed for sustainable energy applications in [5]. In [6], a three-winding coupled inductor-based high voltage gain DC–DC converter was proposed for photovoltaic (PV) systems. The turns ratio of the coupled inductor can be utilized to increase design freedom for the voltage conversion ratio in addition to the duty ratio. The winding cross-coupled inductor contributes to the current sharing performance of the interleaved two-phase converter [7]. The voltage multiplier cell (VMC) is often composed of a coupled inductor and diode–capacitor to further extend the voltage gain and reduce the switch voltage stress [8,9,10,11]. A converter topology that integrates a built-in transformer, coupled inductor, diode and capacitor is proposed to extend the higher voltage gain [12,13]. To achieve high voltage gain with simple circuit structures a number of approaches have been proposed, such as the following: transformer-less and coupled inductor-less techniques of a hybrid switched-inductor in [14], modified active switched-inductor in [15], active switched-inductor and passive switched-capacitors in [16,17] and switched-capacitor in [18]. Three-level DC–DC converters have a simple configuration and decrease the switch voltage stress to half the output voltage [19,20]. To reduce switching losses, zero-voltage switching (ZVS) or zero-current switching (ZCS) in high voltage gain DC–DC converters were proposed in [21,22,23]. The review papers provide good references for research on high voltage gain DC–DC converters [24,25,26,27].

A new non-isolated high voltage gain, interleaved DC–DC converter, suitable for renewable energy applications, is proposed in this article. The techniques of voltage-lift, three-winding coupled inductors and voltage multiplier modules are used to increase the voltage conversion ratio and to reduce the voltage stresses on the power devices.

The characteristics and benefits of the presented converter are summarized as follows:

(1)

The high voltage gain of the proposed converter can be obtained with an appropriate duty ratio.

(2)

Low voltage-rated MOSFETs with low on-state resistance R_DS(ON) and low voltage-rated diodes with low forward voltage drop can be adopted to reduce conduction losses, due to their having low voltage stresses.

(3)

The switches turn ON under the ZCS condition to reduce switching losses.

(4)

The diode reverse–recovery issue is mitigated due to the leakage inductors of the coupled inductors, and voltage spikes on the switches are avoided because the leakage energy is recycled.

(5)

The interleaved parallel input structure of the presented configuration decreases current stresses on the power devices and reduces the input current ripple.

The rest of this article is organized as follows. The operational principle of the proposed converter is presented in detail in Section 2. The steady-state analysis is given in Section 3. The driving circuit and the closed-loop controller design is demonstrated in Section 4. Section 5 demonstrates the simulation and experimental results when using a 1000 W laboratory prototype to validate the theoretical analysis and to assess the effectiveness of the presented converter. This article is concluded in Section 6.

2. Proposed Converter and Principle of Operation

2.1. Proposed Converter

The circuit configuration of the proposed converter topology is shown in Figure 2a. The proposed converter has two coupled inductors with three windings. Their own coupling references are denoted “$•$“ and “$\circ$“.

The first winding of each coupled inductor acts as an input filter inductor. The second and third windings of the coupled inductors are inserted in series integrating capacitors and diodes to form two voltage multiplier modules (VMMs). It should be pointed out that the arrangement positions of the series windings are different in the two VMMs, so that the output capacitors, $C_2$ and $C_3$, can be charged and discharged alternately to reduce the output voltage ripple. The proposed converter primarily consists of two parts: one part is the interleaved boost converter integrating a voltage-lift capacitor, and the other part is the stacked structure of two voltage multiplier modules on the output side to further extend the voltage gain and reduce the voltage stresses on the power devices. Interleaved operation is adopted to help the current ripple cancellation on the input side.

Figure 2a, $S_1$ and $S_2$ present the following power switches: $C_f$ is the voltage-lift capacitor, $C_1$, $C_2$ and $C_3$ are the output capacitors, $C_{11}$ and $C_{21}$ are the regenerative capacitors, $C_{12}$ and $C_{22}$ are the voltage-doubler capacitors, $D_c$ is the clamp diode, $D_{o1}$, $D_{o2}$ and $D_{o3}$ are the output diodes, $D_{11}$ and $D_{21}$ are the regenerative diodes, $D_{12}$ and $D_{22}$ are the voltage-doubler diodes and $R_o$ is the output load. The equivalent circuits for the coupled inductors consist of the ideal transformers with a turns ratio $N_1$:$N_2$:$N_3$, the magnetizing inductors $L_{m1}$ and $L_{m2}$, and the leakage inductors $L_{k1}$ and $L_{k2}$. Figure 2b shows the equivalent circuit of the presented converter.

2.2. Operational Principle

The switches $S_1$ and $S_2$ operate in an interleaved manner with phase shift $180°$ to lower the input current ripple due to ripple cancellation. The duty ratio of the switches is greater than 0.5 for high step-up voltage gain purposes. The key steady-state waveforms of the presented converter, operating in continuous conduction mode (CCM), are shown in Figure 3. According to the ON/OFF state of the switches and diodes in one switching period, the converter has eight operational stages, as illustrated in Figure 4.

In order to simplify the circuit analysis, some assumptions are made, as follow:

• All semiconductors (switches and diodes) are considered to be ideal.
• All capacitors are sufficiently large, and the voltages on these capacitors are regarded as constant during one switching period.
• The parameters of the three-winding coupled inductors are regarded as being identical; that is, the turns ratio $n=N_2/N_1=N_3/N_1$, $L_{m1}=L_{m2}=L_m$ and $L_{k1}=L_{k2}=L_k$. The coupling coefficient of the coupled inductor is defined as $k=L_m/(L_m+L_k)$.

Stage 1 [$t_0~t_1$]: At the beginning of this stage, switch $S_1$ starts to conduct and $S_2$ keeps to the on-state. The diodes $D_{o1}$, $D_c$, $D_{12}$, $D_{21}$ and $D_{o3}$ are reverse-biased. Due to the existence of leakage inductor $L_{k1}$ and the initial current $i_{Lk1}(t_0)=0$, $S_1$ achieves ZCS turn-on because of the leakage inductor series. In this stage, the leakage current $i_{Lk1}$ increases rapidly from its initial value (zero). The magnetizing energy stored in $L_{m1}$ still transfers to the second and third windings of the coupled inductor when $i_{Lk1}<i_{Lm1}$. The currents $i_{D11}$, $i_{D22}$ and $i_{Do2}$ decrease and the descent rate is limited by the leakage inductors $L_{k1}$ and $L_{k2}$. Therefore, the reverse-recovery issue of these diodes is lessened.

When the leakage current $i_{Lk1}$ rises to reach $i_{Lk1}=i_{Lm1}$ at $t=t_1$, the currents $i_{D11}$, $i_{Do2}$ and $i_{D22}$ decrease to zero. The diodes $D_{11}$, $D_{o2}$ and $D_{22}$ turn OFF under the ZCS condition. During this stage, the leakage current $i_{Lk1}$ is given by

$$i_{Lk1}\left(t\right)=i_{Lm1}\left(t\right)-n\left(i_{D11}\left(t\right)+i_{Do2}\left(t\right)+i_{D22}\left(t\right)\right)$$

(1)

Stage 2 [$t_1~t_2$]: The switches $S_1$ and $S_2$ are turned ON, and all diodes are reverse-biased during this stage. The input voltage $V_{in}$ supplies energy to the magnetizing inductors $L_{m1}$ and $L_{m2}$ as well as the leakage inductors $L_{k1}$ and $L_{k2}$. The leakage currents $i_{Lk1}$ and $i_{Lk2}$ increase linearly. The output capacitors $C_1$, $C_2$ and $C_3$ provide energy to the output load. When the switch $S_2$ is turned OFF, the stage ends. During this stage, the leakage currents can be represented as

$$i_{Lk1}\left(t\right)=i_{Lk1}\left(t_1\right)+\frac{V_{in}}{L_{m1}+L_{k1}}\left(t-t_1\right)$$

(2)

$$i_{Lk2}\left(t\right)=i_{Lk2}\left(t_1\right)+\frac{V_{in}}{L_{m2}+L_{k2}}\left(t-t_1\right)$$

(3)

Stage 3 [$t_2~t_3$]: The switch $S_2$ is turned OFF at $t=t_2$. The clamp diode $D_c$ begins to conduct because the leakage current $i_{Lk2}$ is continuous. The diodes $D_{12}$, $D_{21}$, $D_{o3}$ and $D_c$ are forward-biased. The current $i_{Lk2}$ flows through $D_c$, $C_f$ and $S_1$ to charge the voltage-lift capacitor $C_f$. The voltage across $S_2$ is clamped by the capacitor voltage $V_{Cf}$. The leakage current $i_{Lk2}$ decreases and the energy stored in the magnetizing inductor $L_{m2}$ is transferred to charge the capacitors $C_{12}$ and $C_{21}$ via the second and third windings of the coupled inductor during this stage. In the meantime, capacitors $C_{11}$ and $C_{22}$ are discharged. This stage is terminated when $i_{Lk2}$ falls to zero at $t=t_3$.

Stage 4 [$t_3~t_4$]: At the beginning of this stage, the leakage energy stored in $L_{k2}$ is released completely. The clamp diode $D_c$ is turned OFF with ZCS naturally. The magnetizing current $i_{Lm2}$ is reflected from the first winding to the second and third windings completely. The operation of this stage is similar to stage 3. This stage ends when switch $S_2$ returns to conduct at $t=t_4$. The switch current $i_{S1}$ is equal to the sum of $i_{Lm1}$ and $i_{Lm2}$ during this stage, which can be written as

$$i_{S1}(t)=i_{Lm1}(t)+n\left(i_{D12}(t)+i_{D21}(t)+i_{Do3}(t)\right)=i_{Lm1}(t)+i_{Lm2}(t)$$

(4)

Stage 5 [$t_4~t_5$]: At the beginning of this stage, switch $S_2$ starts to conduct and $S_1$ keeps to the on-state. The diodes $D_{o1}$, $D_c$, $D_{11}$, $D_{o2}$ and $D_{22}$ are reverse-biased. Due to the existence of leakage inductor $L_{k2}$ and the initial current $i_{Lk2}(t_4)=0$, $S_2$ achieves ZCS turn-on because of the leakage inductor series. In this stage, the leakage current $i_{Lk2}$ increases rapidly from its initial value (zero). The magnetizing energy stored in $L_{m2}$ still transfers to the second and third windings of the coupled inductor when $i_{Lk2}<i_{Lm2}$. The currents $i_{D12}$, $i_{D21}$ and $i_{Do3}$ decrease and the descent rate is limited by the leakage inductors $L_{k1}$ and $L_{k2}$. Therefore, the reverse-recovery issue of these diodes is lessened.

When the leakage current $i_{Lk2}$ rises to reach $i_{Lk2}=i_{Lm2}$ at $t=t_5$, the currents $i_{D12}$, $i_{D21}$ and $i_{Do3}$ decrease to zero. The diodes $D_{12}$, $D_{21}$ and $D_{o3}$ are turned OFF with the ZCS condition. During this stage, the leakage current $i_{Lk2}$ is given by

$$i_{Lk2}(t)=i_{Lm2}(t)-n\left((i_{D21}(t)+i_{D12}(t))+i_{Do3}(t)\right)$$

(5)

Stage 6 [$t_5~t_6$]: The switches $S_1$ and $S_2$ conduct, and all diodes are reverse-biased during this stage. The magnetizing inductors $L_{m1}$ and $L_{m2}$ as well as the leakage inductors $L_{k1}$ and $L_{k2}$ are supplied with energy by the input voltage $V_{in}$. The leakage currents $i_{Lk1}$ and $i_{Lk2}$ increase linearly. The output capacitors $C_1$, $C_2$ and $C_3$ provide energy to the output load. The stage ends when switch $S_1$ is turned OFF. During this stage, the leakage currents can be represented as

$$i_{Lk1}\left(t\right)=i_{Lk1}\left(t_5\right)+\frac{V_{in}}{L_{m1}+L_{k1}}\left(t-t_5\right)$$

(6)

$$i_{Lk2}\left(t\right)=i_{Lk2}\left(t_5\right)+\frac{V_{in}}{L_{m2}+L_{k2}}\left(t-t_5\right)$$

(7)

Stage 7 [$t_6~t_7$]: Switch $S_1$ is turned OFF at $t=t_6$. The output diode $D_{o1}$ begins to conduct because the leakage current $i_{Lk1}$ is continuous. The diodes $D_{11}$, $D_{22}$, $D_{o1}$ and $D_{o2}$ are forward-biased. The leakage current $i_{Lk1}$ flows through $D_{o1}$, $C_f$ and $C_1$ to charge the output capacitor $C_1$ and to discharge the voltage-lift capacitor $C_f$. The voltage across $S_2$ is clamped by the voltages on the capacitors $C_f$ and $C_1$. The switch voltage stress is equal to $-V_{Cf}+V_{C1}$. During this stage, the leakage current $i_{Lk1}$ decreases and the energy stored in the magnetizing inductor $L_{m1}$ is transferred to charge the capacitors $C_{11}$ and $C_{22}$ via the second third windings of the coupled inductor. In the meantime, capacitors $C_{12}$ and $C_{21}$ are discharged. This stage is terminated when the leakage current $i_{Lk1}$ decreases to zero at $t=t_7$,

Stage 8 [$t_7~t_8$]: At the beginning of this stage, the leakage energy stored in $L_{k1}$ is released completely. The output diode $D_{o1}$ is naturally turned OFF with ZCS. The magnetizing current $i_{Lm1}$ is reflected from the first winding to the second and third windings completely. The operation of this stage is similar to that of stage 7. During this stage, the switch current $i_{S2}$ is equal to the sum of $i_{Lm1}$ and $i_{Lm2}$, which is derived from

$$i_{S2}(t)=i_{Lm2}(t)+n\left(i_{D11}(t)+i_{Do2}(t)+i_{D22}(t)\right)=i_{Lm1}(t)+i_{Lm2}(t)$$

(8)

When switch $S_1$ returns to conduct at $t=t_8$, this stage ends. Then, another new switching cycle begins.

3. Steady-State Analysis

In order to simplify the steady-state analysis of the suggested topology, the transient stages of stage 1 and stage 5 are disregarded, due to their significantly short times, and the leakage inductors are ignored with coupling coefficient k = 1.

3.1. Voltage Gain Analysis

By applying the volt-second balance principle to the magnetizing inductor $L_{m2}$, the voltage-lift capacitor voltage $V_{Cf}$ can be obtained by

$$V_{Cf}=\frac{1}{1-D}{V}_{in}$$

(9)

The result is identical to the output voltage of the traditional boost converter. In addition, the magnetizing inductor $L_{m1}$ also satisfies the volt-second balance principle. We obtain

$$-V_{Cf}+V_{C1}=\frac{1}{1-D}{V}_{in}$$

(10)

Therefore, the voltage of the output capacitor $C_1$ can be derived by

$$V_{C1}=\frac{2}{1-D}{V}_{in}$$

(11)

In stage 3, the magnetizing inductor voltages are given by

$$v_{Lm1}=k{V}_{in}$$

(12)

$$v_{Lm2}=k(V_{in}-V_{Cf})=\frac{kD}{1-D}{V}_{in}$$

(13)

where the coupling coefficient is defined as

$$k=L_m/(L_m+L_k)$$

(14)

The voltage of the capacitor $C_{21}$ can be calculated by the voltages of the third windings in series in the voltage multiplier module in stage 3. This is given by

$$V_{C21}=n{v}_{Lm1}-n{v}_{Lm2}=\frac{kn}{1-D}{V}_{in}$$

(15)

Moreover, by applying the Kirchhoff’s Voltage Low (KVL) to the circuit of stage 3, the following equations can be obtained

$$V_{C12}+n{v}_{Lm2}-n{v}_{Lm1}-V_{C11}=0$$

(16)

$$V_{C3}+n{v}_{Lm2}-n{v}_{Lm1}-V_{C22}=0$$

(17)

In stage 7, the magnetizing inductor voltages are given by

$$v_{Lm1}=V_{in}+V_{Cf}-V_{C1}=-\frac{kD}{1-D}{V}_{in}$$

(18)

$$v_{Lm2}=k{V}_{in}$$

(19)

The voltage of the capacitor $C_{11}$ can be calculated by the voltages of the series’ third windings in the voltage multiplier module in stage 7. This is given by

$$V_{C11}=n{v}_{Lm2}-n{v}_{Lm1}=\frac{kn}{1-D}{V}_{in}$$

(20)

Moreover, by applying the Kirchhoff’s Voltage Low (KVL) to the circuit of stage 7, the following equations can be obtained

$$V_{C2}+n{v}_{Lm1}-n{v}_{Lm2}-V_{C12}=0$$

(21)

$$V_{C22}+n{v}_{Lm1}-n{v}_{Lm2}-V_{C21}=0$$

(22)

Arranging the above equations, the voltages of the capacitors $C_{12}$, $C_{22}$, $C_2$ and $C_3$ can be obtained. The results are as follows.

$$V_{C12}=V_{C22}=\frac{2kn}{1-D}{V}_{in}$$

(23)

$$V_{C2}=V_{C3}=\frac{3kn}{1-D}{V}_{in}$$

(24)

From Equations (11) and (24), the output voltage of the proposed converter can be derived by

$$V_o=V_{C1}+V_{C2}+V_{C3}=\frac{6kn+2}{1-D}{V}_{in}$$

(25)

Consequently, the voltage gain $M_k$ of the presented converter can be written in the form

$$M_k=\frac{V_o}{V_{in}}=\frac{6kn+2}{1-D}$$

(26)

The different curves of voltage gain with turns ratio n = 1, and various coupling coefficients, k = 1, 0.95, 0.9, are shown in Figure 5. Clearly, the coupling coefficient k has little influence on the voltage gain. If the leakage inductor is ignored (the coupling coefficient k = 1), then the ideal voltage gain of the proposed converter is written in the form

$$M=\frac{V_o}{V_{in}}=\frac{6n+2}{1-D}$$

(27)

From Equation (27), it can be concluded that the voltage gain of the proposed converter has two degrees of design freedom, turns ratio $n$ and duty ratio D. The high voltage gain of the proposed converter can be accomplished without an extremely large duty ratio if the designer selects the appropriate turns ratio of the coupled inductor. The voltage gain curves related to the turns ratio and the duty ratio are plotted in Figure 6. In fact, one can see that the voltage gain was 20 times with duty ratio D = 0.6 and turns ratio n = 1. Thus, the presented topology is suitable for high step-up voltage conversion.

3.2. Voltage Stress Analysis

Based on the operational principle of the presented topology, the voltage stress on switches $S_2$ and $S_1$ can be determined by stage 3 and by stage 7, respectively. With the help of Equation (27), the switch voltage stress is given by

$$V_{S2}=V_{Cf}=\frac{1}{1-D}{V}_{in}=\frac{1}{6n+2}{V}_o$$

(28)

$$V_{S1}=V_{C1}-V_{Cf}=\frac{1}{1-D}{V}_{in}=\frac{1}{6n+2}{V}_o$$

(29)

The switch voltage stress is much smaller than the output voltage. Therefore, MOSFETs with low rated voltage and low on-resistance R_DS(ON) can be used to reduce the conduction losses. Moreover, the voltage stresses on the following diodes can be obtained from stage 3.

$$V_{Do1}=V_{C1}-V_{Cf}=\frac{1}{1-D}{V}_{in}=\frac{1}{6n+2}{V}_o$$

(30)

$$V_{Do2}=V_{C2}-V_{C11}=\frac{2n}{1-D}{V}_{in}=\frac{n}{3n+1}{V}_o$$

(31)

$$V_{D11}=V_{C12}=\frac{2n}{1-D}{V}_{in}=\frac{n}{3n+1}{V}_o$$

(32)

$$V_{D22}=V_{C22}=\frac{2n}{1-D}{V}_{in}=\frac{n}{3n+1}{V}_o$$

(33)

Similarly, the voltage stresses on the following diodes can be obtained from stage 7.

$$V_{Dc}=V_{C1}=\frac{2}{1-D}{V}_{in}=\frac{1}{3n+1}{V}_o$$

(34)

$$V_{D12}=V_{C12}=\frac{2n}{1-D}{V}_{in}=\frac{n}{3n+1}{V}_o$$

(35)

$$V_{D21}=V_{C22}=\frac{2n}{1-D}{V}_{in}=\frac{n}{3n+1}{V}_o$$

(36)

$$V_{Do3}=V_{C3}-V_{C21}=\frac{2n}{1-D}{V}_{in}=\frac{n}{3n+1}{V}_o$$

(37)

From the results in Equations (30)–(37), the voltage stresses on the diodes are much lower than the output voltage. Therefore, the designer can choose the low forward voltage drop diodes to reduce conduction losses. It is known that the voltage stress on the switch or diode in the interleaved boost converter is equal to the output voltage. Thus, the presented converter has the merit of low semiconductor voltage stress.

3.3. Design Consideration

3.3.1. Considerations of Coupled Inductor Design

If an appropriate duty ratio is selected, then the turns ratio of the coupled inductor can be calculated according to Equation (27) and is given by

$$n=\frac{V_o(1-D)}{6V_{in}}-\frac{1}{3}$$

(38)

In order to operate under CCM and current-ripple considerations, the magnetizing inductor of the coupled inductor is designed as follows. If the average current through the magnetizing inductor is denoted as $I_{Lm}$ and its ripple current is denoted as $\Delta i_{Lm}$, then, the condition for the presented converter operating in CCM can be represented as

$$I_L{}_m>\frac{1}{2}\Delta i_{Lm}$$

(39)

Based on the operational principle, the ripple current $\Delta i_L{}_m$ can be expressed as

$$\Delta i_{Lm}=\frac{V_{in}}{L_{\mathrm{m}}}D{T}_s$$

(40)

where $T_s$ is the switching period. The average current $I_{Lm}$ can be written in the form

$$I_L{}_m=\frac{P_o}{2V_{in}}$$

(41)

where $P_o$ denotes the output power. Therefore, the value of the magnetizing inductor $L_m$ must satisfy the following condition in CCM operation.

$$L_m>\frac{V_{in}^{2}D{T}_s}{P_o}$$

(42)

Substituting Equation (27) into Equation (42), we obtain

$$L_m>\frac{{\left(1-D\right)}^2{V}_o^{2}D{T}_s}{{\left(6n+2\right)}^2{P}_o}=\frac{D{\left(1-D\right)}^2{R}_o^{}}{{\left(6n+2\right)}^2{f}_s}$$

(43)

where $f_s$ is the switching frequency.

3.3.2. Considerations regarding Capacitor Design

The main consideration regarding each capacitor is suppression of the voltage ripple to an acceptable level. According to the operational principle of the presented converter, the output capacitor $C_1$ discharges to the load by the output current in a total time of about $D{T}_s$. Therefore, the ripple voltage on the output capacitor $C_1$ can be expressed as

$$\Delta V_{C1}\approx \frac{D{V}_o}{R_o{C}_1{f}_s}$$

(44)

Substituting Equations (11) and (27) into Equation (44), we obtain

$$\Delta V_{C1}=\frac{(3n+1)D{V}_{C1}}{R_o{C}_1{f}_s}$$

(45)

If the specification of the voltage ripple on the output capacitor $C_1$ is provided, then the design condition of the output capacitor $C_1$ can be given by

$$C_1=\frac{(3n+1)D}{R_o{f}_s(\Delta V_{C1}/V_{C1})}$$

(46)

Similarly, if the percentage of voltage ripple is specified, then the design conditions of the output capacitors $C_2$ and $C_3$ can be, respectively, expressed as

$$C_2=\frac{(6n+2)D}{3n{R}_o{f}_s(\Delta V_{C2}/V_{C2})}$$

(47)

$$C_3=\frac{(6n+2)D}{3n{R}_o{f}_s(\Delta V_{C3}/V_{C3})}$$

(48)

The average charging current ${\overline{i}}_{C11(\mathrm{charge})}$ of the regenerative capacitor $C_{11}$ in one switching period is equal to the average current ${\overline{i}}_{D11}$ of the regenerative diode $D_{11}$. By applying the amp-second balance principle, the design condition of capacitor $C_{11}$ can be expressed as

$$C_{11}=\frac{(6n+2)}{n{R}_o{f}_s\left(\Delta V_{C11}/V_{C11}\right)}$$

(49)

The average discharging current ${\overline{i}}_{C12\left(\mathrm{discharge}\right)}$ of the voltage-doubler capacitor $C_{12}$ in one switching period is equal to the average current ${\overline{i}}_{Do1}$ of the output diode $D_{o1}$. In a similar way to that of the design method of $C_{11}$, the design condition of the capacitance and the voltage ripple can be derived by

$$C_{12}=\frac{(6n+2)}{2n{R}_o{f}_s\left(\Delta V_{C12}/V_{C12}\right)}$$

(50)

Similarly, the values of the capacitors $C_{21}$ and $C_{22}$ can be, respectively, derived by

$$C_{21}=\frac{(6n+2)}{n{R}_o{f}_s\left(\Delta V_{C21}/V_{C21}\right)}$$

(51)

$$C_{22}=\frac{(6n+2)}{2n{R}_o{f}_s\left(\Delta V_{C22}/V_{C22}\right)}$$

(52)

3.4. Converter Performance Comparison

In order to illustrate the performance of the presented converter, a comparison to the similar interleaved high voltage gain DC-DC converters published in [28,29,30,31,32,33] is shown in

Table 1. Performance comparison.

Reference Converter	[28]	[29]	[30]	[31]	[32]	[33]	Proposed
Voltage gain	$\frac{3n+1}{1-D}$	$\frac{2n+2}{1-D}$	$\frac{2n+4}{1-D}$	$\frac{3n+D(2n-1)+2}{1-D}$	$\frac{5n+1}{1-D}$	$\frac{4n+4}{1-D}$	$\frac{6n+2}{1-D}$
Voltage stress on switches	$\frac{V_o}{3n+1}$	$\frac{V_o}{2n+2}$	$\frac{V_o}{2n+4}$	$\frac{V_o}{3n+D(2n-1)+2}$	$\frac{V_o}{5n+1}$	$\frac{V_o}{4n+4}$	$\frac{V_o}{6n+2}$
Maximum diode voltage stress	$\frac{2n{V}_o}{3n+1}$	$\frac{\left(2n+1\right)V_o}{2n+2}$	$\frac{n{V}_o}{n+2}$	$\frac{(n+1)V_o}{3n+D(2n-1)+2}$	$\frac{2n{V}_o}{5n+1}$	$\frac{\left(2n+1\right)V_o}{2n+2}$	$\frac{n{V}_o}{3n+1}$
Number of switches	2	2	2	2	2	2	2
Number of diodes	8	6	6	9	7	5	8
Number of capacitors	7	5	6	8	6	5	8
Number of coupled inductor	2	2	2	2	2	2	2
Voltage gain $n=1,D=0.6$	10	10	15	14	15	20	20

. If the turns ratio was $n\ge 1$ (the general case for high voltage gain purposes), it revealed the following results: (1) the voltage conversion ratio of the presented converter was the highest; (2) the switch voltage stress of the presented converter was the lowest, and was much lower than the output voltage; (3) the maximum diode voltage stress of the presented converter was the lowest, and was much lower than the output voltage; (4) the number of components was not the largest.

The voltage gain of the presented converter was higher than that of the converter in [33] if the turns ratio was n > 1. The switches turned on under the ZCS condition to reduce the switching losses in the proposed converter. The converter in [33] had the advantage of fewer components; however, the switches did not have the ZCS turn-on feature.

4. Driving Circuit and Controller Design

The converter operates in an interleaved mode. It was necessary to design a driving circuit to generate PWM signals with a phase shift of $180°$ to drive the power switches. The driving circuit implemented by the PWM IC KIA494 is shown in Figure 7.

In order to keep the output voltage at a specific value, regardless of input voltage fluctuations and load changes, the closed-loop control system, shown in Figure 8, was employed to obtain good output voltage regulation. In the block diagram, $C\left(s\right)$ is the controller transfer function and $1/V_P$ is the pulse-width modulator (PWM) gain, where $V_P$ is the amplitude of sawtooth waveform in the PWM. Function $P\left(s\right)$ is the small signal transfer function of the presented converter from the duty ratio to the output voltage and K is the sensor gain of the output voltage. The controller $C\left(s\right)$ required a design such that the open-loop transfer function $T_{OL}\left(s\right)$ met the following specifications:

• A gain crossover frequency of 1 kHz ($2\pi \times {10}^3\mathrm{rad}/\mathrm{s}$).
• A phase margin (P.M.) larger than ${50}^{\mathrm{o}}$.
• The low frequency gain of the open-loop transfer function $T_{OL}\left(s\right)$ to be very high to reduce the steady-state error for the constant reference input.

The frequency response analyzer NF FRA51602 was used to measure the frequency response from the control signal ${\tilde{v}}_{ctrl}$ to the output voltage sensing signal $K{\tilde{v}}_o$ at the operating point of the proposed converter. Then, the curve fitting method, using the MATLAB software, was employed to establish the transfer function of $G\left(s\right)$, where

$$G(s)=\frac{K{\tilde{v}}_o(s)}{{\tilde{v}}_{ctrl}(s)}=\frac{K}{V_p}P(s)$$

(53)

The transfer function by the curve-fitting method is obtained by

$$G\left(s\right)=\frac{k{\tilde{v}}_o(s)}{{\tilde{v}}_{ctrl}(s)}=\frac{1.54}{\left(1+\frac{2.2}{1400}s+\frac{1}{{1400}^2}{s}^2\right)}$$

(54)

The Bode plots of the measured method and the curve-fitting method are shown together in Figure 9. From the comparison, it can be seen that the curves were quite consistent for the frequency range concerned. Consequently, the transfer function given in Equation (54) was utilized to design the controller.

In this article, the K factor approach [34] was employed to design the well-known Type III controller. The electronic circuit with six passive components is illustrated in Figure 10, and the circuit transfer function is expressed by

$$\frac{{\tilde{v}}_{ctrl}\left(s\right)}{K{\tilde{v}}_o(s)}=-\frac{R_1+R_3}{R_1{R}_3{C}_2}\frac{\left(s+\frac{1}{R_2{C}_1}\right)\left(s+\frac{1}{(R_1+R_3)C_3}\right)}{s\left(s+\frac{1}{R_2{C}_1{C}_2/(C_1+C_2)}\right)\left(s+\frac{1}{R_3{C}_3}\right)}$$

(55)

The controller consists of an integrator and two sets of phase leaders. The integrator is helpful to ensure a steady-state error of zero. The phase leaders are helpful to provide enough phase margin to keep the control loop stable. The controller transfer function was designed and obtained as

$$C\left(s\right)=\frac{1.13\times {10}^6(s+2024)(s+1761)}{s(s+24380)(s+20903)}$$

(56)

with the parameters of the six components:

$$R_1=100\mathrm{k}\Omega ,R_2=426\mathrm{k}\Omega ,R_3=9.2\mathrm{k}\Omega ,C_1=1.16\mathrm{nF},C_2=0.105\mathrm{nF},C_3=5.2\mathrm{nF}$$

The frequency response of the controller $C\left(s\right)$ is shown in Figure 11.

The frequency response of the open-loop transfer function $T_{OL}\left(s)=C\right(s\left)G\right(s)$ was obtained as depicted in Figure 12. The control system provides a gain crossover frequency of $\omega =2\pi \times {10}^3$ rad/s, a phase margin of ${50}^{\mathrm{o}}$, and very high DC gain. Thus, the designed controller satisfies the specification requirements of the voltage control system.

5. Experimental Results

A 1000 W laboratory prototype, with voltage conversion from 24 V to 400 V, was implemented and tested to validate the performance of the presented converter. The detailed and complete circuit of the experiment with the closed-loop control is shown in Figure 13. The sensor gain K of the output voltage was equal to 1/100 in the closed-loop control system. Therefore, the reference signal V_ref was equal to 4 V. Figure 14 shows the prototype photograph. The components and parameters of the experimental converter are shown in

Table 2. Parameters of prototype converter.

Components	Parameters
Magnetizing inductors $L_{m1}$, $L_{m2}$	$73\mathsf{\mu }\mathrm{H}$
Leakage inductors $L_{k1}$, $L_{k2}$	$0.6\mathsf{\mu }\mathrm{H}$
Turns ratio of coupled inductor $n$	$1$
Voltage-lift capacitor $C_f$	$82\mathsf{\mu }\mathrm{F}$
Output capacitors $C_1$, $C_2$, $C_3$	$150\mathsf{\mu }\mathrm{F}$
Regenerative capacitors $C_{11}$, $C_{21}$	$82\mathsf{\mu }\mathrm{F}$
Voltage-doubler capacitors $C_{12}$, $C_{22}$	$82\mathsf{\mu }\mathrm{F}$
Switching frequency $f_s$	$50\mathrm{kHz}$
Switches $S_1$, $S_2$	FDP036N10A
Diodes $D_{11}$, $D_{21}$, $D_{12}$, $D_{22}$, $D_{o2}$, $D_{o3}$	V30120C
Diodes $D_c$, $D_{o1}$	30CPQ200

. The simulation of the proposed converter was performed by the circuit simulation software Is-Spice, with the circuit shown in Figure 15. The Under the full load (1000 W) condition, the simulated results and the experimental results are demonstrated in Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23 and Figure 24.

The waveforms of the gating signals $v_{gs1}$ and $v_{gs2}$ of the switches, output voltage and input voltage are illustrated in Figure 16. The voltage conversion ratio was over 16 times with $V_o=400\mathrm{V}$ and $V_{in}=24\mathrm{V}$. It was verified that the converter achieved high voltage gain without a very large duty ratio.

Figure 17 illustrates the waveforms of the gating signals and the switch voltages $v_{ds1}$ and $v_{ds2}$. The maximum switch voltage was slightly more than 50 V. The switch voltage stress was much lower than the output voltage 400 V. Clearly, the switches of the proposed converter had low voltage stress.

The waveforms of the input current $i_{in}$, the leakage currents $i_{Lk1}$ and $i_{Lk2}$ are shown in Figure 18. The input parallel structure of two-phase shares the input current to reduce the current stress of power devices. On the other hand, the ripple currents of $i_{Lk1}$ and $i_{Lk2}$ were almost the same, with an amplitude of 49 A. The current ripple cancellation was achieved, due to the interleaved operation, such that the ripple current of $i_{in}$ reduced to only 2 A. It was verified that the interleaved operation could reduce the input current ripple for the parallel input structure.

The current and voltage waveforms of the regenerative diodes $D_{11}$ and $D_{21}$, as well as those of the voltage-doubler diodes $D_{12}$ and $D_{22}$, are shown in Figure 19 and Figure 20, respectively. It can be seen that there were no reverse-recovery currents, due to the ZCS turn-off feature. The voltage stresses were equal to 100 V, which was only one-fourth of the output voltage. The measured results agreed with the analyzed results.

Figure 21 shows the switch current and voltage waveforms. The switch currents $i_{ds1}$ and $i_{ds2}$ rose linearly from 0 when each switch began to conduct. The ZCS turn-on performance was achieved to reduce the switching losses.

The voltage waveforms of the output capacitors $C_1$, $C_2$ and $C_3$ are shown in Figure 22. The voltage $V_{C1}$ was slightly more than 100 V and the voltages $V_{C2}$ and $V_{C2}$ were about 150 V, which was in keeping with the results of the analysis. The simulation results were consistent with the experimental results.

Figure 23a shows the output voltage response and the input voltage variation between 24 V and 27 V. On the other hand, the output voltage response and the output current under the step-on and step-off load changes between 500 W and 1000 W are illustrated in Figure 23b. As shown in the figures, the transient ripples of output voltage were clearly very small. The results demonstrated good voltage regulation performance, due to the well-designed controller, for the closed-loop control system.

The measured efficiency of the prototype converter at different output powers is illustrated in Figure 24. The highest efficiency was 95.52% at 200 W, and the efficiency at 1000 W full load was 87.36%.

6. Conclusions

By applying the three-winding coupled-inductor technique, a new high voltage gain interleaved DC–DC converter for renewable energy systems is introduced in this paper. The voltage gain is further extended and the semiconductor voltage stresses are reduced by the voltage multiplier modules. The principle of operation, steady-state analysis, design considerations and controller design are presented. The high voltage conversion ratio is accomplished without a very large duty ratio. The designer can adopt low on-state resistance MOSFETs and low forward voltage drop diodes to reduce the conduction losses, due to their low voltage stresses. With the help of the leakage inductors of the coupled-inductors, the ZCS condition turn-on is intrinsically provided for the switches. The interleaved operation reduces the input current ripple. The leakage energy is recycled to eliminate the voltage spikes on the switches. A performance comparison with other similar converters was carried out to reveal the merits of the introduced converter. Moreover, a closed-loop controller was designed and implemented to ensure effective output voltage regulation. Finally, the simulation and experimental results, using a 1000 W prototype, are provided to validate the derived analysis and to demonstrate the advantages of the presented converter. Thus, the proposed DC-DC converter with high voltage gain and high efficiency is suitable for renewable energy systems.