Search Results (86)

In hybrid-series-converter-based LCC-HVDC systems, controllable capacitor modules can provide additional voltage–time area during commutation, thereby improving inverter-side fault tolerance under AC faults. However, their switching behavior makes the commutation path impedance state-dependent, while most existing commutation-failure prediction methods still rely on fixed-reactance assumptions. To address this problem, this paper proposes a reactance-corrected predictive control and coordinated switching method. First, a capacitor switching coefficient is introduced to describe the insertion state of the controllable capacitor modules, and an equivalent commutation reactance of the HSC valve arm is derived. Then, the corrected reactance is incorporated into an extinction-angle margin index and an energy-margin index to quantify the influence of reactance variation on commutation capability. A segmented firing-angle controller with smooth compensation is further designed, and energy-margin feedback is coordinated with capacitor insertion control. PSCAD/EMTDC simulations verify that the proposed method reduces prediction error, provides a prediction lead time of 0.7–4.5 ms, and improves fault ride-through capability. Full article

This paper presents a passive residue-coupled discrete-time delta–sigma ($\Delta \Sigma$) modulator for low-power narrowband sensing applications. Instead of adding a fourth active integrator, the proposed architecture keeps a third-order switched-capacitor main loop and reuses the intrinsic top-plate residue of an 8-bit asynchronous successive-approximation-register (SAR) quantizer. The retained capacitive digital-to-analog converter (CDAC) residue is passively reinjected through a charge-redistribution path, introducing an additional high-pass error-propagation factor in the effective noise transfer function (NTF). Under a bounded effective coupling coefficient, the proposed loop approaches fourth-order-like in-band noise suppression while retaining third-order active-loop complexity. Behavioral simulations show that the Enhanced mode improves the peak signal-to-noise-and-distortion ratio (SNDR) by 16.9 dB over the Baseline third-order mode at an oversampling ratio (OSR) of 128. Circuit-level corner verification of the standalone SAR confirms correct bit cycling and a settled residue-retention window under typical–typical (TT), slow–slow (SS), and fast–fast (FF) conditions: with the slowest conversion window of about 21.4 ns at the SS corner and a sampling period of 39.06 ns at $f_s=25.6$ MHz, roughly 17.66 ns of timing margin remains for residue holding, passive reinjection, and clock non-overlap. The proposed method provides an architecture-level route for improving in-band noise shaping without increasing the number of active integrator stages, and is particularly attractive for low-power, narrowband, and sensor-oriented analog-to-digital converter (ADC) applications. Full article

Pulse thyristors are extensively utilized in pulsed plasma discharge applications. In this study, a pulse switch prototype is built using two parallel valve groups, each consisting of seven series-connected thyristors. Each thyristor is equipped with an anti-parallel protection diode, a static voltage-sharing resistor, and an RCD (resistor-capacitor-diode) dynamic voltage-sharing circuit. The prototype withstands 24 kV, delivers 150 kA peak current, operates at 10 Hz, and can run continuously for 1 s. Thermal analysis is essential under narrow-pulse high-current conditions to avoid failure from localized overheating. By investigating the expansion process of the conduction zone during thyristor turn-on, a single-thyristor turn-on model and a finite-element model of the multi-layer series thyristor module are established to analyze transient temperature distributions. Results show a non-uniform temperature profile across the silicon wafer, with the hottest zone near the gate ring. During repetitive pulses, the silicon temperature fluctuates rapidly, while the copper base heats up gradually. At a spreading speed of 30 m/s, the gate terminal temperature rises about 38 °C—within safe limits for now, but projected to exceed them under future operating conditions. Thus, improved thermal management will be critical in further development. Full article

The integration of solar energy into smart grids requires high-efficiency power conversion to support grid stability. However, Partial Shading Conditions (PSCs) remain a primary obstacle by inducing multiple local maxima on P–V characteristic curves. This paper presents a hardware-aware and memory-enhanced Maximum Power Point Tracking (MPPT) approach based on a modified Dragonfly Algorithm (DA) for grid-connected microinverter-based photovoltaic (PV) systems. The proposed method utilizes a quasi-switched Boost-Switched Capacitor (qSB-SC) topology, where the DA is specifically tailored by combining Lévy-flight exploration with a dynamic damping factor to suppress steady-state oscillations within the qSB-SC ripple constraints. Coupling the MPPT stage to a seven-level Packed-U-Cell (PUC) microinverter ensures that each PV module operates at its independent Global Maximum Power Point (GMPP). A ZigBee-based Wireless Sensor Network (WSN) facilitates rapid data exchange and supports ‘swarm-memory’ initialization, matching current shading patterns with historical data to seed the population near the most probable GMPP region. This integration reduces the overall response time to 0.026 s. Hardware-in-the-loop experiments validated the approach, attaining a tracking accuracy of 99.32%. Compared to current state-of-the-art benchmarks, the proposed model demonstrated a significant improvement in tracking speed, outperforming the most recent 2025 GWO implementation (0.0603 s) by approximately 56% and conventional metaheuristic variants such as GWO-Beta (0.46 s) by over 94%.These results confirmed that the modified DA-based MPPT substantially enhanced the microinverter efficiency under PSC through cross-layer parameter adaptation. Full article

This paper proposes a novel seven-level switched-capacitor multilevel inverter featuring a shared front-end DC-link structure that achieves triple voltage gain with reduced component count. A distinctive feature of this design is its inherent capacitor voltage self-balancing capability, thereby eliminating the need for complex control algorithms typically associated with multilevel converters. Moreover, the topology demonstrates particularly significant advantages in three-phase implementations, where a single DC source, front-end switching devices, and capacitors can be shared across all phases—thus substantially reducing component count and system complexity compared to conventional designs. Additionally, this paper proposes an improved carrier-based modulation strategy for this topology requiring only a single triangular carrier, along with a systematic method for determining optimal capacitance values. Through detailed comparative assessment against state-of-the-art switched-capacitor seven-level inverters, the superior performance characteristics of the proposed topology are clearly demonstrated. Finally, simulation results under various operating conditions are presented and subsequently validated through experimental testing on a laboratory prototype, confirming the practical viability of the proposed solution. Full article

This paper proposes a small-signal model of a DC–DC parallel resonant converter operating in continuous conduction mode based on asymmetric pulse-width modulation (APWM) under light-load conditions. The parallel resonant converter enables soft switching and no-load control over a wide load range because the resonant capacitor is connected in parallel with the load. However, the resonant energy required for soft switching is already sufficient, and the current flowing through the resonant tank is independent of the load magnitude; therefore, as the load decreases, the energy that is not delivered to the load and instead circulates meaninglessly inside the resonant tank increases. This results in conduction loss and reduced efficiency. To address this issue, APWM with a fixed switching frequency is required, which reduces circulating energy and improves efficiency under light-load conditions. Precise small-signal modeling is required to optimize the APWM controller. Unlike PFM or PSFB, APWM includes not only sine components but also DC and cosine components in the control signal due to its asymmetric switching characteristics, and this study proposes a small-signal model that can relatively accurately reflect these multi-harmonic characteristics. The proposed model is derived based on the Extended Describing Function (EDF) concept, and the derived transfer function is useful for systematically analyzing the dynamic characteristics of the APWM-based parallel resonant converter. In addition, it provides information that can systematically analyze the dynamic characteristics of various APWM-based resonant converters and control signals that reflect various harmonic characteristics, and it can be widely applied to future control design and analysis studies. The validity of the model is verified through MATLAB (R2025b) and PLECS (4.7.5) switching-model simulations and experimental results, confirming its high accuracy and practicality. Full article

In order to achieve a long-pulse-width output, a new long-pulse-width modulator based on the charging power supply of LCC-type high-frequency resonant converters and the pulse-generating unit in series IGBT switching technology has been designed. The relationship between the resonant cavity gain and the switching frequency has been derived. In the charging phase, the critical intermittent control mode is used to increase the charging speed, and in the voltage stabilization phase, the hysteresis burst control strategy is used to improve voltage accuracy. The simulation results show that the output pulse amplitude is 10 kV, the pulse width can reach 650 μs, and the top-drop is about 12%. Thus, a long pulse width modulator is developed. The output pulse voltage can reach 4 kV, and the output pulse width is 650 μs. The power supply reduces the capacity of the energy storage capacitor, which has industrial application value. Full article

This article proposes a high-efficiency isolated three-port resonant converter for DC microgrids, combining a dual active bridge (DAB)–LLC topology with hybrid Pulse Width Modulat-Pulse Frequency Modulation (PWM-PFM) phase shift control. Specifically, the integration of a dual active bridge and LLC resonant structure with interleaved buck/boost stages eliminates cascaded conversion losses. Energy flows bidirectionally between ports via zero-voltage switching, achieving a 97.2% efficiency across 150–300 V input ranges, which is a 15% improvement over conventional cascaded designs. Also, an improved PWM-PFM shift control scheme dynamically allocates power between ports without altering switching frequency. By decoupling power regulation and leveraging resonant tank optimization, this strategy reduces control complexity while maintaining a ±2.5% voltage ripple under 20% load transients. Additionally, a switch-controlled capacitor network and frequency tuning enable resonant parameter adjustment, achieving a 1:2 voltage gain range without auxiliary circuits. It reduces cost penalties compared to dual-transformer solutions, making the topology viable for heterogeneous DC microgrids. Based on a detailed theoretical analysis, simulation and experimental results verify the effectiveness of the proposed concept. Full article

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in the ISDM stage is presented. The ADC employs an improved high-precision double-bootstrapped switch, and the synchronous clock is also double-bootstrapped to work under the low supply voltage. A modified merged capacitor switching (MCS) approach is presented to maintain a stable VCM at the differential input. The chip was fabricated using a 0.18 µm CMOS process, with a core area of 0.21 mm². It consumed only 0.42 µW at a 0.6 V supply and a sampling rate of 10 kS/s, which achieved an effective number of bits (ENOB) of 11.03. The resulting figure of merit (FOM_W) was 20.05 fJ/conversion-step, which is the lowest reported for ADCs of this architecture in a 0.18 µm process. Full article

The authors of this study suggest an improvement to their recently released quadruple-diode boost regulator (QDBC), which may be used in two configurations: without or with a voltage multiplier unit (VMU). This voltage multiplier unit consists of two switch capacitors diagonally connected across two diodes, or vice versa. During each operational cycle, energy can be stored and released through the switch capacitive filters and inductive chokes, increasing voltage gain and decreasing output fluctuation. ANSOFT/SIMPLORER 7, PLECS 4.9.5, and SIMULINK 2021a are further used to simulate the proposed regulator’s linearized version to investigate its frequency response and stability. Hence, to improve the harmonic performance of the proposed regulator, the authors of this study used a delta modulation current regulator (DMCR), sometimes referred to as a variable bandwidth delta modulation current regulator. The findings show that the QDBC has, when using the DMCR, a voltage gain of $1+D/{(1-D)}^2$, an efficiency of 97%, and a shorter settling time of 0.04 s when compared to other DC-DC regulators (SEPIC, boost, and quadratic boost). Finally, to validate the theoretical analysis and simulation results of the proposed QDBC structure, a 250 W regulator prototype was built utilizing similar design exercise requirements. Full article

The sub-module capacitor is the most vulnerable component in a modular multilevel converter (MMC), and its aging poses a significant challenge to system stability. To accurately monitor capacitor aging, this article utilizes capacitor voltage fluctuations to recognize the inserted window for capacitance calculation using nearest-level modulation. Additionally, a time-slicing method is developed to improve accuracy. The proposed method, which combines the inserted window recognition method with the time-slicing algorithm, offers a simple, easy-implementation approach. Simulations and experimental results validate that the method achieves high accuracy (less than 0.5%). Moreover, it does not require additional sensors, precise extraction of switching signals, or interruption to the system’s normal operation, making it highly suitable for MMC systems with a large number of sub-modules. Furthermore, the proposed method also demonstrates strong robustness in dynamic conditions and can be extended to all sub-modules. Full article

This study proposes a novel fault diagnosis algorithm based on Equivalent Series Resistance (ESR) estimation to enhance the accuracy of capacitor life diagnosis techniques for the DC link in marine electric propulsion systems. Accurate ESR estimation is critical for maintaining the reliability and efficiency of DC-Link capacitors, which play a key role in stabilizing voltage, reducing harmonics, and ensuring the smooth operation of electric propulsion systems. By preventing capacitor failures, this algorithm contributes to reducing the risk of catastrophic damage to entire systems. The ESR value is determined by extracting AC voltage and current data within the frequency range of 10 kHz to 30 kHz using a band-pass filter. To improve reliability, the algorithm compensates for input errors based on the modulation index and switching pattern, with error data stored in a lookup table. By addressing limitations in existing ESR estimation techniques, the proposed method reduces estimation errors across the entire range and enhances fault diagnosis accuracy. Experimental results validate the algorithm’s improved accuracy, reliability, and stability, demonstrating its effectiveness in preventing damage to power conversion devices. Full article

A single-phase multilevel inverter with a switched-capacitor multilevel (SC-MLI) configuration is developed to provide 13-level output voltages. An improved genetic algorithm (GA) with adaptive mutation and crossover rates is employed to achieve robust harmonic mitigation by avoiding local optima and ensuring optimal performance. The topology introduces an SC-MLI that generates AC output voltage at desired levels using only two capacitors, two asymmetrical DC sources, one diode, and 11 switches. This allows the inverter to use fewer gate drivers and, hence, increases the power density of the converter. A significant challenge in the normal operation of SC-MLI circuits relates to the self-voltage balance of the capacitors, which easily becomes unstable, particularly at low modulation indices. The proposed design addresses this issue without the need for ancillary devices or complex control schemes, ensuring stable self-balanced operation across the entire spectrum of the modulation index. In this context, the harmonic mitigation technique optimized through GA applied in this inverter ensures low harmonic distortion, achieving a total harmonic distortion (THD) of 6.73%, thereby enhancing power quality even at low modulation indices. The performance of this SC-MLI is modeled under various loading scenarios using MATLAB/Simulink^® 2023b with validation performed through an Opal-RT real-time emulator. Additionally, the inverter’s overall power losses and individual switch losses, along with the efficiency, are analyzed using the simulation tool PLEXIM-PLECS. Efficiency is found to be 96.62%. Full article

Busbars are critical components that connect high-current and high-voltage subcomponents in high-power converters. This paper reviews the latest busbar design methodologies and offers design recommendations for both laminated and PCB-based busbars. Silicon Carbide (SiC) power devices switch at much higher speeds compared to traditional silicon devices, making them more susceptible to parasitic elements within the busbar. In high-frequency SiC converters, using thicker copper offers limited improvement in high-frequency current handling due to the reduced skin depth at such frequencies. PCB busbars, however, provide several advantages, including reduced loop inductance, enhanced high-frequency current capacity, simplified assembly, and lower costs. Additionally, they enable the integration of components such as sensors, capacitors, and resistors, which can further optimize overall system performance. This paper also presents optimized busbar designs for both module-based and discrete device-based SiC high-power converters, comparing various SiC power module packages and offering design insights. Finally, this paper showcases a 75 kW three-phase inverter utilizing a PCB busbar, demonstrating its potential for achieving high power density and cost-effectiveness in discrete SiC device-based high-power converters. Full article

Photovoltaic (PV) modules are often connected in series to achieve the desired voltage level in practical applications. A common issue with this setup is module mismatch, which can be either permanent or temporary and is caused by various factors. The differential power processing (DPP) concept has emerged as a prominent solution to address this problem. However, a significant drawback of current DPP topologies is their reduced performance under certain conditions, particularly in cases of permanent mismatch. As a result, applications involving the DPP concept for permanent mismatches remain underexplored. In this context, the goal of this work is to develop and implement a novel DPP topology capable of increasing energy harvesting in PV systems under permanent mismatch. The proposed hybrid architecture combines features from both bidirectional buck–boost (BBB) and resonant switched capacitor (ReSC) converters. The ReSC converter operates under soft-switching conditions, minimizing undesirable losses. Key advantages of the proposed converter include fewer switches, lower voltage stress, and soft-switching operation, making it suitable for PV systems with mismatched modules. Experimental tests showed an energy harvesting improvement under the assessed conditions. Full article