Currently, the design of resonant power converters has only been developed while operating in the steady state, while the design operating in the transient stage has not been considered nor reported. This paper is interested in testing the performanc...
The main contribution of this paper is to show the analysis and design of a resonant converter which was designed to operate in the transient stage and with underdamped response, where the resonant network stage has a frequency equal to “n&rdqu...
A high-efficiency frequency multiplier is presented in 65-nm CMOS with a core area of 0.06 mm2. A low-cost five-segment triangular-resistance phase interpolation scheme is proposed. By performing resistive interpolation on four-path orthogonal triang...
A microwave photonic frequency multiplier with low phase noise based on an optoelectronic oscillator (OEO) is proposed and experimentally demonstrated. In this scheme, a dual-parallel Mach–Zehnder modulator (DPMZM) is employed to generate the t...
This study presents a synthesizer topology based on a delay-locked loop (DLL) and programmable frequency multiplier for 5G+ communication systems. The proposed synthesizer comprises a 512-phase DLL, an intermediate frequency generator (IFG), and an R...
Millimeter-wave (mmWave)/terahertz (THz) devices relying on conventional semiconductor technologies face significant performance bottlenecks, constraining their use in next-generation electronic systems. To address these challenges, this work demonst...
12 December 2023
A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for f...
A 17.8–34.8 GHz (64.6%) locking range current-reuse injection-locked frequency multiplier (CR-ILFM) with dual injection technique is presented in this paper. A dual injection technique is applied to generate differential signal and increase the power...
This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the rece...
Usually many applications of radar transceivers and heterodyne frequency synthesizers assume a spurious signal power level below −60 dBc. In the case of modern synthesizers using direct digital synthesis (DDS) systems, the number of emerging sp...
This paper summarizes the development of novel Schottky-diode-based terahertz frequency multipliers. The basic structure and manufacturing process of planar Schottky barrier diodes (SBDs) are reviewed, along with other diode structures that have been...
Frequency multipliers are essential components in communication systems, and graphene’s exceptional electrical properties make it highly promising for flexible electronics. This paper addresses the technical challenges of multi-frequency multip...
This paper proposes a compact inductor design for LC-tank injection-locked frequency multipliers (ILFMs) fabricated using a 0.18 μm CMOS process. The ILFMs use an 8-shaped inductor with two lobes, suppressing the magnetic field generation. Its con...
We propose a terahertz frequency multiplier based on high order harmonic generation in a GaAs-based miniband superlattice driven by an electric field. The performance of the frequency multiplier is analyzed using the balance equation approach, which...
Based on a W-band high-power source, two schemes are proposed to realize a 335 GHz frequency multiplier source. The first scheme involves producing a 335 GHz signal with a two-stage doubler. The first doubler adopts two-way power-combined technology...
This letter presents a scheme for obtaining a microwave photonic frequency multiplier with low phase noise, in which an optoelectronic oscillator (OEO) is integrated with a directly modulated laser (DML)-based injection-locking technique. The system...
A broadband H-band (220 GHz–325 GHz) frequency tripler using the triple-push technique is presented in 250-nm InP heterojunction bipolar transistors (HBT) technology. It consisted of three identical unit-cell multipliers, which were individuall...
The passive multipliers based on semiconductor diodes, most frequently a Schottky type, should be driven by a certain value of input power, where the conversion losses are optimal. This means that the variation in the input power level causes the cha...
This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock pha...
The emergence of the Internet of Things (IoT) technologies has greatly enhanced the lives of individuals with disabilities by leveraging radio frequency identification (RFID) systems to improve autonomy and access to essential services. However, thes...
To improve the detection speed for wide-frequency dense signals (WFDSs), a fast minimization algorithm (FMA) was proposed in this study. Firstly, this study modeled the WFDSs and performed a Taylor-series expansion of the sampled model. Secondly, we...
Utilising a nonlinear (regime-switching) mixed-frequency panel vector autoregression model, we study the effects of government spending shocks in the United States (US) over the business cycle, while considering the role of partisan conflict. In part...
For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive...
Mobile technology is currently trending toward supporting multiple communication standards on a single device. This means that some reconfigurable techniques must be the foundation of their design. The two essential requirements of channel filters ar...
A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplicatio...
The authors of this study suggest an improvement to their recently released quadruple-diode boost regulator (QDBC), which may be used in two configurations: without or with a voltage multiplier unit (VMU). This voltage multiplier unit consists of two...
This paper proposes centralized and distributed optimization models for V2G applications to provide frequency regulation in power systems and the electricity market. Battery degradation and dynamic
We extend the classical fractal uncertainty principle (FUP) framework in time-frequency analysis by exploring several novel directions. First, we generalize the FUP beyond the classical Gaussian window by investigating non-Gaussian windows and the co...
A global design method for a terahertz monolithic integrated frequency multiplier is proposed. Compared with a traditional independent design, the method in this paper adopts overall optimization and combines the device with the circuit design. The a...
In this paper, a type of effective electronic counter-countermeasures (ECCM) technique for suppressing the high-power deception jamming using an orthogonal frequency division multiplexing (OFDM) radar is proposed. Concerning the velocity deception ja...
An optical frequency comb (OFC) generator based on an electro-optic Talbot laser and cross-phase modulation (XPM) in a high nonlinear fiber (HNLF) is designed and demonstrated. The Talbot laser is an electro-optic frequency shifting loop that is used...
This study investigates the influence of loading pattern, analysis level, and nodal connection stiffness on the stability and dynamic behaviour of a low-rise steel dome. Three joint configurations and two loading scenarios, symmetrical and asymmetric...
This paper presents a broadband frequency quadrupler (FQ) implemented with a standard 130-nm SiGe BiCMOS process. Two broadband push-push frequency doublers (×2) operate at an input frequency of 32.5–55 GHz and 65–110 GHz, respectiv...
This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison b...
In this paper, D-band (110–170 GHz) frequency tripler module is presented using anti-parallel GaAs Schottky diode pair and waveguide-to-microstrip transitions. The anti-parallel diode pair is used as a nonlinear device generating harmonic compo...
Radio frequency energy harvesting (RF-EH) is a potential technology via the generation of electromagnetic waves. This advanced technology offers the supply of wireless power that is applicable for battery-free devices, which makes it a prospective al...
A novel Schottky diode frequency doubler in E-band, using biased series-connected diodes in the output waveguide, is reported. The doubler was implemented using a GaAs Schottky Monolithic Microwave Integrated Circuit (MMIC) process with integrated ca...
An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast l...
In recent years there have been significant developments in satellite transmitter technology to follow the rapid innovation of sensors on-board new satellites. The CCSDS 131.2-B-1 standard for telemetry downlink, released in 2012, is part of the next...
The exigency for continuous use of electrical devices has created greater demands for electricity along with more efficient transmission techniques. Energy from natural resources can be solar, thermal, vibration, friction, or Radio Frequencies (RF) s...
This paper presents a 220 GHz × 2 amplifier–doubler chain composed of a rat-race balun, a 6-stage driver amplifier, and a frequency doubler. The presented amplifier–doubler chain was fabricated in commercial 40 nm bulk CMOS technolo...
Radio-frequency (RF) energy harvesting (EH) is emerging as a reliable and constantly available free energy source. The primary factor determining whether this energy can be utilized is how efficiently it can be collected. In this work, an RF EH syste...
With high renewable penetration, primary frequency regulation (PFR) in low-inertia power systems faces a critical challenge of balancing frequency security with sustainable energy storage system (ESS) utilization. Existing ESS-based PFR studies mainl...
This paper describes recent engineering designs that allow full-duplex SerDes connectivity between a number of cascaded Xilinx radio frequency system-on-chip (RF-SoC) and VCU FPGA systems. The design allows for unlimited scalability with all-to-all c...
In synthetic aperture radar (SAR) signal processing, compared with the raw data of level-0, level-1 SAR images are more readily accessible and available in larger quantities. However, an amount of level-1 images are affected by radio frequency interf...
The millisecond-level volatile fluctuations in workloads in large-scale intelligent computing clusters pose significant challenges to traditional electricity markets. Constrained by optical–electrical–optical conversion bottlenecks, these...
The development of a millimeter-wave unbalanced frequency tripler based on the nonlinear characteristics of planar Schottky varactors is presented. The entire module is designed by hybrid integration. A frequency multiplier circuit model was establis...
Information is pivotal in contemporary society, highlighting the necessity for a secure cryptographic system. The emergence of quantum algorithms and the swift advancement of specialized quantum computers will render traditional cryptography suscepti...
Multiplication is the dominant operation for many applications implemented on field-programmable gate arrays (FPGAs). Although most current FPGA families have embedded hard multipliers, soft multipliers using lookup tables (LUTs) in the logic fabric...
This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field r...
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