Search Results (375)

Polarimetric high-resolution range profiles (HRRPs) contain rich amplitude and phase information scattered from targets, making them essential for radar remote sensing applications. However, current HRRP imaging methods still face challenges in achieving precise full-polarization measurements. In addition, they are either affected by off-grid errors thus introducing spurious scattering centers (SCs), fail to utilize polarimetric priors from the channels, or encounter high computational complexity. Some of these issues limit the quality of polarimetric HRRPs, while others result in excessive computational load, hindering their application on orbital remote sensing platforms. This paper proposes a fast gridless polarimetric HRRP imaging method. First, we introduce the novel virtual full polarization sparse stepped-frequency waveforms (VFP-SSFW) to improve channel isolation, in which each pulse is transmitted with either horizontal (H) or vertical (V) polarization, selected uniformly at random. Then, we propose a polarimetric atomic norm minimization (P-ANM)-based imaging framework formulated within distributed compressed sensing (DCS), which fully exploits the joint sparsity across polarization channels while inherently eliminating off-grid errors. Additionally, we develop a fast algorithm based on alternating direction method of multipliers (ADMM) to enable efficient implementation. The proposed method can circumvent transmission channel crosstalk and can efficiently yield high-quality polarimetric HRRPs with co-registered SCs . The validity of the proposed method is demonstrated through simulated, electromagnetic, and measured experimental results. Full article

The millisecond-level volatile fluctuations in workloads in large-scale intelligent computing clusters pose significant challenges to traditional electricity markets. Constrained by optical–electrical–optical conversion bottlenecks, these markets struggle to achieve real-time response and risk substantial social welfare loss. Leveraging existing fiber-optic infrastructure to build All-Optical Networks (AONs) presents a cost-effective evolutionary path. This paper develops a distributed energy trading strategy based on all-optical multicast. By utilizing the physical multicast properties of the underlying light-tree architecture instead of traditional protocols, the proposed strategy bypasses end-to-end latency constraints. This enables rapid transaction synchronization and dynamic tracking of social welfare optima within millisecond-level time-slots. Simulation results demonstrate that the proposed scheme elevates the transaction saturation threshold by two orders of magnitude compared with traditional strategies, effectively breaking the physical locking effect of latency on system throughput. Across various topologies, the social welfare gains exceed those of conventional schemes by more than 20 times. This study validates the engineering value of all-optical architectures for high-frequency trading and provides critical technical support for ultra-dynamic power trading algorithms. Full article

This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, and spectral purity. The review covers several topologies from the standard push–push (PP) doubler to its power-efficient evolution, the complementary push–push (CPP) doubler. Furthermore, this paper focuses on more recent and advanced topologies, including the complementary common gate capacitive cross-coupled (CCGCCC) doubler. Finally, this work proposes and evaluates an improved version of the CCCGCC doubler, offering insights into the state of the art and future directions in mm-wave frequency multiplication. Full article

Generalized Sinusoidal Frequency Modulation (GSFM) signals can enhance Continuous Active Sonar (CAS) performance by providing high sub-signal processing gain while achieving high target update rates. However, conventional processing methods for GSFM often exhibit high sidelobe levels arising from the waveform’s autocorrelation which degrade detection performance, especially in severe multipath environments. To address this issue, a Mismatched-Channel Filtering (MMCF) method for GSFM in CAS is proposed to focus multipath energy while suppressing sidelobe levels. Adopting the sub-pulse processing scheme, we incorporate the orthogonality of GSFM sub-signals (optimized via a genetic algorithm) and sparse channel estimates into the MMCF design for each sub-signal. The design is formulated as a Quadratically Constrained Quadratic Program (QCQP) and solved iteratively using the Alternating Direction Method of Multipliers (ADMM) for long-duration signal processing in CAS. Numerical simulations demonstrate that, compared with the matched filtering and matched channel filtering methods, the proposed MMCF method effectively suppresses sidelobe levels by approximately 20 dB and produces a Dirack-like main-lobe peak, while efficiently focusing multipath energy. The method’s effectiveness is further validated using experimental data from a lake trial. Therefore, this algorithm has distinct advantages for signal processing in multipath environments. Full article

This paper presents a dual-core RISC-V architecture designed for energy-efficient AI acceleration at the edge, featuring dynamic MAC unit sharing, frequency scaling (DFS), and FIFO-based resource arbitration. The system comprises two RISC-V cores that compete for shared computational resources—a single Multiply–Accumulate (MAC) unit and a shared external memory subsystem—governed by a channel-based arbitration mechanism with CPU-priority semantics, while each core maintains private instruction and data caches. The architecture implements a tightly coupled Neural Processing Unit (NPU) with CONV, GEMM, and POOL operations that execute opportunistically in the background when the MAC unit is available. Dynamic frequency scaling (DFS) with three levels (100/200/400 MHz) is applied to the shared MAC unit, allowing the dynamic acceleration of CNN workloads. The arbitration mechanism uses SystemC sc_fifo channels with CPU-priority polling, ensuring that CPU execution is minimally impacted by background AI processing while the NPU makes progress during idle MAC slots. The NPU supports 3 × 3 convolutions, matrix multiplication (GEMM) with 10 × 10 tiles, and pooling operations. The implementation is cycle-accurate in SystemC, targeting FPGA deployment. Experimental evaluation demonstrates that the dual-core architecture achieves 1.87× speedup with 93.5% efficiency for parallel workloads, while DFS enables 70% power reduction at low frequency. The system successfully executes simultaneous CPU and AI workloads, with CPU-priority arbitration ensuring no CPU starvation under contention. The proposed design offers a practical solution for embedded AI applications requiring both general-purpose computation and neural network acceleration, validated through comprehensive SystemC simulation on modern FPGA platforms. Full article

This paper proposes an optoelectronic oscillator (OEO)-based scheme for generating frequency-doubled binary phase-coded microwave pulses. The architecture employs a cascaded dual-polarization quadrature phase shift keying modulator (DP-QPSK) and a polarization modulator (PolM) to generate carrier-suppressed ±2nd-order sidebands and an orthogonally polarized optical carrier. By applying opposite phase modulation to the two polarization components and subsequently converting them into the same polarization state using a polarization controller (PC) and a polarizer, frequency-doubled phase-coded microwave pulses are obtained after photodetection. The operating principle of the scheme is theoretically analyzed and experimentally validated. A 5 GHz OEO signal is successfully converted into a 10 GHz phase-coded microwave pulse without the use of an external electronic frequency multiplier or an additional intensity modulator for pulse carving. Binary phase-coded pulses with coding rates of 0.1 Gb/s and 0.25 Gb/s are experimentally demonstrated. The measured temporal waveforms, recovered phase information, and autocorrelation results agree well with theoretical predictions. The proposed scheme provides a structurally simple and frequency-doubling solution for OEO-based phase-coded microwave pulse generation with reduced system complexity. Full article

Filters supporting dynamic reconfiguration that use the spectral parameter approximation (SPA) technique, together with other methodologies, and the interpolated spectral parameter approximation (ISPA) technique offer dynamic adjustment of the cutoff frequency (f_c) with a narrow transition bandwidth and a very wide f_c range. However, they suffer from a high multiplier requirement, leading to increased hardware resource usage. With fewer multipliers, we suggest the Multiply and Accumulate (MAC)-based SPA (MAC-SPA) and MAC-based interpolated SPA (MAC-ISPA) filter in this article. This article describes a unified MAC structure utilizing Time-Division Multiplexing (TDM) that uses the resource-sharing concept to implement an MAC-SPA and MAC-ISPA filter. The developed dynamically reconfigurable filter is implemented and realized using a 0.18 µm CMOS process. Additional testing was done on the Xilinx xc6vlx760-1ff1760 FPGA device. Relative to the filter that incorporates SPA along with the modified coefficient decimation method (MCDM), the obtained results reveal that the proposed MAC-SPA and MAC-ISPA channel filters, synthesized on FPGA, achieve a reduction in occupied slice count by approximately 7% and 4.76%, respectively. Although their operating speeds are slightly lower by about 9.4% for the MAC-SPA filter and 13.89% for the MAC-ISPA filter, this tradeoff is offset by significant savings in hardware resources, making both designs more area-efficient with only a modest reduction in speed. Full article

After approximately 60 years of service, the 2856 MHz LINAC injector, of the Canadian Light Source (CLS), has been retired to make space for a new 3000.24 MHz LINAC injector, the frequency of which is a multiple of the 500.04 MHz CESR-B-type superconductive radio frequency cavity used in the CLS storage ring. The new CLS LINAC injector has been designed and built by RI Research Instruments GmbH. The design is based on their robust S-band RF traveling-wave accelerating structures technology already serving other laboratories in the USA, Australia, Taiwan, Switzerland, and Sweden. In order to reduce cost and optimize space, the CLS has replaced its six accelerating RF structures, each 3.05 m long, delivering a 250 MeV electron beam with three 5.26 m long accelerating structures that will deliver the same beam energy. In order to do so, one RF structure is powered by one klystron modulator, and the last two RF structures receive their RF power from a second klystron modulator that passes through a SLED system. The SLED system multiplies the peak power by a factor of 5 to 6 and is then equally split to power each structure. We are reporting on the issues encountered during the commissioning of this new injector, on how we have tackled them and where the injector, compared to its technical specification, is standing today. Full article

Multi-regional electricity markets increasingly struggle to balance data privacy requirements with the computational burden of centralized clearing. To address this issue, this study proposes a distributed joint-clearing framework based on the Alternating Direction Method of Multipliers (ADMM) to co-optimize pumped storage hydropower (PSH) and battery energy storage systems (BESS) across energy, frequency regulation, and reserve markets. A mixed-integer programming model is formulated to maximize social welfare, explicitly capturing the time-coupled, energy-oriented characteristics of PSH and the fast-response, power-oriented capabilities of BESS. The global problem is decomposed into regional subproblems that can be solved in parallel. An adaptive penalty parameter strategy is further introduced to dynamically balance primal and dual residuals, thereby improving convergence and robustness in the mixed-integer setting. To address the limited economic interpretability of dual variables in mixed-integer programming (MIP) models, an approximate marginal pricing mechanism based on subproblem sensitivity analysis is proposed. A two-region, 24 h case study shows that the proposed method converges in around 65 iterations and achieves a social welfare outcome within 0.61% of the centralized optimum. By minimizing information exchange, the framework offers a scalable and privacy-aware solution for future multi-regional market operations involving heterogeneous energy storage resources. Full article

A transparent, end-to-end pathway from learning-level training to deployable fixed-point hardware is presented and framed as gradients to gates. A didactic XOR convolutional network is first employed so that backpropagation, post-training quantization in INT8, and fixed-point arithmetic can be made concrete and verified with exact checks. The same methodology was applied to a compact LeNet-5 case study. On the software side, the training-to-export flow was formalized, and a bit-accurate Python reference was constructed for the quantized network. On the hardware side, a synthesizable INT8 datapath was implemented in Verilog, including multiply–accumulate units, sigmoid activation stages, and per-layer requantization with rounding and saturation. Test benches are provided so that the exported weights and activations can be ingested, and layer-wise matches can be reported. A co-simulation harness was used to coordinate framework inference, quantization, file conversion, HDL simulation, and regression checks, which enabled deterministic comparisons of the activations, partial sums and outputs. The complete loop was mapped to Artix-7 on the CMOD A7 development board, and the resource usage, maximum clock frequency, inference latency, and throughput were determined. The approach aligns with an educational HDL-to-Caffe pipeline by using reusable parameterized Verilog primitives for convolution, pooling, activation, and fully connected layers, training in Colab with AccDNN, Caffe, quantization, and an automated bit-for-bit verification regime before FPGA synthesis. Methodological contributions are provided, including a minimal and auditable XOR CNN that exposes scales, shifts, and saturation; a practical quantization recipe with INT32 accumulation and unit tests that guarantee agreement within one least significant bit between RTL and the INT8 reference; and a scalable mapping to LeNet-5 using a row-stationary and line-buffered dataflow on an Artix-7 FPGA. Empirical evidence shows feasibility at 100 MHz with representative utilization, millisecond-scale latency and zero mismatches across large test sets, which validates the quantization configuration and the verification strategy. Full article

This paper presents a subtractive-dither-assisted background calibration technique for a 2 GS/s 12 bit pipelined analog-to-digital converter (ADC). A large 7 bit pseudo-random dither is injected in both the flash and the multiplying digital-to-analog converter (MDAC) to decorrelate the differential nonlinearity (DNL) errors caused by the inherent quantization error nonlinearity, capacitor mismatching, and inter-stage amplifier nonlinearity from the input signal. Designed in a 28 nm CMOS process with a 1 V supply, post-layout simulations demonstrate a 10.2 dB improvement in spurious-free dynamic range (SFDR), from 73.8 dB to 84.4 dB, with dithering enabled under a close-to-Nyquist input frequency of 985 MHz. Although the injected dither cannot be completely removed in the digital domain, the proposed ADC exhibits only a 0.5 dB degradation in signal-to-noise-and-distortion ratio (SNDR) for full-scale input, achieving an SNDR of 62.3 dB and an effective number of bits (ENOB) of 10.1 bits. Dithering also improves static performance, with DNL and INL optimized to +0.54/−0.53 LSBs and +0.85/−0.88 LSBs, respectively. Moreover, the proposed dither-based calibration technique introduces an additional power consumption of less than 2 mW. Full article

To address the challenges of insufficient frequency regulation capability of individual stations, poor collaborative economic performance, and unfair benefit allocation caused by fluctuations in photovoltaic (PV) output and variations in electric vehicle (EV) connectivity during vehicle-to-grid (V2G) interactions under high-penetration PV integration, this paper proposes a coordinated optimal operation strategy for peer-to-peer (P2P) energy sharing and joint frequency regulation among multiple electric vehicle charging stations (EVCSs). First, a collaborative framework for P2P energy sharing and joint frequency regulation among EVCSs is constructed to describe the operational mechanism of inter-station energy mutual support and coordinated response to frequency regulation signals. Subsequently, an aggregate model of the dispatchable potential for EV clusters within each station is established based on Minkowski Summation (M-sum), characterizing the charging and discharging power boundaries and frequency regulation potential of the EV clusters. Meanwhile, distributionally robust chance constraints (DRCC) based on the Kullback–Leibler (KL) divergence are introduced to handle the uncertainty of PV power generation within the EVCS. On this basis, a dynamic frequency regulation output model for EV clusters and a multi-station P2P energy sharing model are designed, with the optimization objective of minimizing the total operating cost. Finally, to quantify the differential contributions of each EVCS in the collaborative operation, an asymmetric Nash bargaining benefit allocation mechanism is proposed, which incorporates a comprehensive contribution index considering both energy sharing and joint frequency regulation, The model is solved in a distributed manner using the alternating direction method of multipliers (ADMM). Simulation results demonstrate that, compared to non-cooperative operation, the frequency regulation completeness rates of the EVCSs after cooperation increase by 5.7%, 5.2%, and 4.4%, respectively; meanwhile, the total operating cost drops from CNY 16,187.61 under non-cooperative operation to CNY 15,997.47, achieving a reduction of 1.18%. The proposed strategy not only meets grid frequency regulation demands but also enhances the economic efficiency of multi-station collaborative operation and the fairness of benefit distribution. Full article

In this study, the density of magnesium sulfate-based foam concrete was regulated by adjusting the foam dosage and the ratio of the foam stabilizer xanthan gum (XG) to the specialized foaming agent GX-7. The evolution of the pore structure was evaluated using bleeding rate tests and scanning electron microscopy (SEM). This investigation further elucidated the critical roles of density variation and pore morphology in determining the mechanical performance (compressive strength) and thermal insulation efficiency of the material. The results indicate that increasing the addition of high-stability modified foam significantly increased the pore density of the ultra-lightweight foam concrete while simultaneously reducing the average pore diameter. These microstructural changes led to a progressive decrease in bulk density, accompanied by a corresponding reduction in compressive strength. When the foam dosage reached 100% of the MgO mass, the material’s density decreased to 136.3 kg/m³, with a corresponding thermal conductivity of 0.081 W/(m·K). SEM micrographs revealed that, under these conditions, the pores exhibited a uniform morphology and well-defined structure, indicating an optimized pore architecture. However, when the foaming multiplier exceeded 125%, the frequency of bubble rupture increased markedly. Full article

This paper presents a compact floating memtranstor (MT) emulator, a memory element characterized by a direct φ–q relationship, realized without analog multipliers or complex circuitry. The proposed design employs only two active blocks—a voltage differential transconductance amplifier (VDTA) and a voltage differential current conveyor (VDCC)—along with three grounded capacitors and a single grounded electronically tunable resistor. The emulator accurately reproduces the fundamental φ–q dynamics, exhibiting origin-crossing pinched hysteresis loops under sinusoidal excitation, and operates at a low supply voltage of ±0.9 V. Electronic tunability is achieved via bias-controlled transconductance modulation, enabling flexible adaptation across excitation frequencies and operating conditions. Validation is performed through analytical modeling, Monte Carlo simulations, temperature sensitivity analysis, and full LTspice post-layout simulations using a 180 nm CMOS process. The full-custom layout occupies 2529.49 μm², with robust performance confirmed under parasitic and process variations. Adaptive learning simulations demonstrate the emulator’s artificial synaptic plasticity, highlighting its suitability for neuromorphic computing, chaos-based circuits, and nonlinear dynamical systems. The compact, low-power, and multiplier-free architecture establishes the proposed MT emulator as a practical platform for emerging analog memory-centric applications. To validate the feasibility of the proposed solution, experimental tests are performed using commercially available components. Full article

This paper presents a hardware-efficient field-programmable gate array (FPGA) implementation of a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes in very small aperture terminal (VSAT) satellite communication systems. The decoder is described in C++ and synthesized using the Xilinx Vitis high-level synthesis (HLS) 2025 (AMD Xilinx, San Jose, CA, USA) tool, and then packaged and integrated as an intellectual property (IP) core within the Vivado Design Suite 2024 (AMD Xilinx, San Jose, CA, USA), enabling rapid prototyping and portability across FPGA platforms. Unlike conventional normalized min-sum (NMS) and two-dimensional normalized min-sum (2D-NMS) architectures, the proposed 2D-CNMS scheme employs dyadic, multiplier-free normalization combined with two-level magnitude correction, achieving near sum-product performance with reduced complexity and latency. The design is implemented on a Zynq UltraScale+ multiprocessor system-on-chip (MPSoC) (AMD Xilinx, San Jose, CA, USA) and supports real-time operation with a throughput of 29–41 Mbps at 100 MHz, while using only 9.6–22.4 k look-up tables (LUTs), 2.1–5.9 k flip-flops (FFs), and no digital signal processing (DSP) slices or block random-access memories (BRAMs). Bit-error-rate (BER) simulations over an additive white Gaussian noise (AWGN) channel show no error floor down to ${10}^{-8}$. These results demonstrate that the proposed HLS-based 2D-CNMS IP core provides a resource-efficient, high-performance LDPC decoding solution as compared with existing LDPC implementation approaches. This LDPC solution targets performance enhancement in wireless communication systems and has been deployed on a multi-frequency time-division multiple-access (MF-TDMA) satellite link to assess its overall behavior, demonstrating improved performance with reduced resource usage. Full article