High-Efficiency Digital Filters for Spectral Parameter Approximation in SDR

Abstract

Filters supporting dynamic reconfiguration that use the spectral parameter approximation (SPA) technique, together with other methodologies, and the interpolated spectral parameter approximation (ISPA) technique offer dynamic adjustment of the cutoff frequency (f_c) with a narrow transition bandwidth and a very wide f_c range. However, they suffer from a high multiplier requirement, leading to increased hardware resource usage. With fewer multipliers, we suggest the Multiply and Accumulate (MAC)-based SPA (MAC-SPA) and MAC-based interpolated SPA (MAC-ISPA) filter in this article. This article describes a unified MAC structure utilizing Time-Division Multiplexing (TDM) that uses the resource-sharing concept to implement an MAC-SPA and MAC-ISPA filter. The developed dynamically reconfigurable filter is implemented and realized using a 0.18 µm CMOS process. Additional testing was done on the Xilinx xc6vlx760-1ff1760 FPGA device. Relative to the filter that incorporates SPA along with the modified coefficient decimation method (MCDM), the obtained results reveal that the proposed MAC-SPA and MAC-ISPA channel filters, synthesized on FPGA, achieve a reduction in occupied slice count by approximately 7% and 4.76%, respectively. Although their operating speeds are slightly lower by about 9.4% for the MAC-SPA filter and 13.89% for the MAC-ISPA filter, this tradeoff is offset by significant savings in hardware resources, making both designs more area-efficient with only a modest reduction in speed.

1. Introduction

Many signal analysis and processing applications require dynamic adjustment of the cutoff frequency (f_c) of digital filters. One of the most uncomplicated methods for implementing a modifiable filter can be realized through the use of programmable filters, sometimes referred to as variable-coefficient or re-loadable filters [1,2]. These filters store the filter coefficients for different f_c values in memory, then they load the appropriate coefficients within the filter setup according to the intended f_c. Some constraints of this solution are as follows: (1) a significant amount of memory would be needed to store all of the filter coefficients that correspond to all of the desired f_c values; (2) numerous highly variable parameters vary depending on the length of the filter; and (3) a significant number of memory access operations must be performed each time a filter reconfiguration is required. Reconfigurable filters, which modify the impulse response of the fixed-coefficient prototype filter to adjust f_c with only a few variable parameters, are developed to overcome these limitations of variable-coefficient filters. The spectral parameter approximation (SPA) technique is a reconfigurable digital filter design method that provides total control over f_c [3,4,5,6,7,8,9,10]. Combining SPA with other methods has also been used to develop customizable filters [11,12,13]. The expansion of the tunable cutoff frequency range (f_c), together with a narrowing transition bandwidth, leads to increased implementation complexity in existing FIR filter design approaches, thereby limiting their suitability for applications requiring a wide operating range, narrow transition bandwidth, and strong stopband attenuation [14,15].

Recent work on reconfigurable FIR filtering includes MAC-based architectures, coefficient decimation, SPA/ISPA spectral adjustment, and Farrow interpolation. Farrow filters provide continuous tunability, but their hardware complexity is significant [16]. SPA/ISPA designs offer wide tuning capabilities for SDR applications, despite their primary use of parallel realizations with high DSP utilization and restricted scalability [17,18]. Coefficient reduction techniques improve resource usage but impose spectrum limitations [18], whereas MAC-based filters save hardware by sharing multipliers but do not handle polynomial spectral tuning [19]. The proposed work combines SPA/ISPA tunability with single-MAC time-multiplexed realization to increase scalability and efficiency.

On the other hand, the size of the filter coefficients increases dramatically when the required cutoff frequency (f_c) and transition bandwidth (tbw) drop. This makes it more difficult to realize SPA-based filters in fixed-point form and to implement them. Furthermore, many existing SPA-based approaches [3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22] require a large number of multipliers or fail to satisfy design requirements when high stopband attenuation, a narrow transition bandwidth, and a wide cutoff frequency tuning range are simultaneously required.

Hybrid FPGA FIR solutions that mix DSP slices and LUT structures have been developed to reconcile arithmetic efficiency and logic use. In addition, recent computing paradigms have explored neuromorphic hardware platforms and spiking neural networks to improve energy efficiency and scalability for signal processing workloads [23,24]. Maamoun et al. developed a high-order FIR architecture that concurrently uses DSP blocks and LUT shift-register structures to enhance pipelining and resource utilization on FPGA platforms, whereas Datta and Dutta introduced a high-efficiency half-band decimation FIR filter that uses coefficient symmetry and CSD representation to reduce arithmetic complexity and hardware utilization in FPGA implementations [23,24].

Recent studies on FPGA-based FIR filter implementations have employed techniques to decrease hardware complexity, including hybrid DSP–LUT processing structures, distributed arithmetic, canonical signed digit (CSD) encoding, and coefficient symmetry exploitation. Even though these techniques successfully minimize multiplier usage or boost speed, most published systems still rely on the concurrent assessment of filter branches, which leads to hardware resource needs that scale with filter order or polynomial degree. In particular, SPA-based FIR filters and Farrow structures typically duplicate multipliers or MAC units for every polynomial branch when implemented on FPGA systems, leading to high DSP and power consumption. Therefore, there is a gap between the mathematical description of SPA filtering and its hardware-efficient implementations that minimize arithmetic resources without altering the filter response. To bridge this gap, this work proposes a deterministic time-multiplexed MAC architecture that rearranges the evaluation of SPA polynomial subfilters into a sequential computation schedule executed by a single shared-MAC datapath. Unlike conventional multiplier-reduction strategies, the proposed method achieves large reductions in DSP use and power consumption by reformulating the algorithm-to-architecture mapping instead of modifying the filtering algorithm itself. As a result, the architecture allows for resource-efficient FPGA implementation while maintaining the spectral properties and computational accuracy of high-order SPA FIR filters.

This article presents the implementation of a flexible filter design that uses the SPA technique [12] along with the enhanced ISPA approach [22] using single-channel MAC [20,21]. The proposed MAC SPA and MAC ISPA filters combine the best features of both of these methods to offer seamless tunability of f_c while maintaining a narrow transition bandwidth and a very wide f_c range. An inventive dilatation of the SPA and ISPA was proposed by using a single-MAC design leveraging TDM and shared resource utilization. In this brief, only one multiplier and one adder are used, regardless of tap count and channels. The reconfigurable filter under consideration was developed, tested, and put into use on a Xilinx xc6vlx760-1ff1760 FPGA based on a 0.18 µm CMOS fabrication process. Compared to a filter that uses a combination of frequency transformation and interpolation approaches, this system offers flexibility with reduced space and power at both architectural and filter levels, as well as a lower group delay and a slightly lower operating speed.

This paper is structured as follows: Section 2 offers a study of the SPA and ISPA plan. Section 3 explains the structure for the developed Finite Impulse Response filter. Section 4 presents the exploratory results. Section 5 contains the assessment results.

2. Review of Methods for Designing Reconfigurable Digital Filters

2.1. Examination of the SPA Technique

The SPA approach in [3,4,5,6,7,8,9,10] in this division is summarized here. As illustrated in Figure 1, the Farrow structure is used to create a spectral parameter approximation-based filter (SPA filter). The weighted total of the frequency responses of S + 1 filter stages is the SPA filter’s frequency response. Because each filter stage has a fixed order N, each filter stage needs N + 1 coefficients.

The SPA filter’s frequency response is provided by Equation (1):

$$\mathrm{H}\left(\mathsf{\omega },{\mathsf{\omega }}_{\mathrm{c}}\right)={\sum }_{\mathrm{i}=1}^{\mathrm{S}+1}{\mathrm{W}}_{\mathrm{i}}\left({\mathsf{\omega }}_{\mathrm{c}}\right){\mathrm{H}}_{\mathrm{i}}\left(\mathsf{\omega }\right),$$

(1)

where

• H(ω,ω_c) is the overall frequency response of the variable filter;
• ω denotes angular frequency;
• ω_c is the cutoff frequency control parameter;
• H_i(ω) represents the response of the ith subfilter;
• W_i(ω_c) are cutoff-dependent weighting functions;
• S indicates the interpolation order;
• i is the stage index.

The impulse response coefficients h_i,k (for k = 0, 1…N − 1) for each filter stage H_i(ω) are expressed as polynomials, which are given by Equation (2):

$${\mathrm{h}}_{\mathrm{i},\mathrm{k}}\left({\mathsf{\omega }}_{\mathrm{c}}\right)={\mathrm{a}}_{\mathrm{k}0}^{\left(\mathrm{i}\right)}+{\mathrm{a}}_{\mathrm{k}1}^{\left(\mathrm{i}\right)}{\mathsf{\omega }}_{\mathrm{c}}+{\mathrm{a}}_{\mathrm{k}2}^{\left(\mathrm{i}\right)}{\mathsf{\omega }}_{\mathrm{c}}^2+\cdots +{\mathrm{a}}_{\mathrm{k}\mathrm{S}}^{\left(\mathrm{i}\right)}{\mathsf{\omega }}_{\mathrm{c}}^{\mathrm{S}},$$

(2)

where

• h_i,k(ω_c) denotes the kth impulse response coefficient of the ith subfilter parameterized by the cutoff frequency ω_c;
• a_kj⁽ⁱ⁾ represents the fixed polynomial coefficient associated with the jth power term of the kth tap in the ith stage;
• ω_c is the cutoff frequency control parameter;
• S is the polynomial approximation order;
• i is the subfilter stage index;
• k is the tap index;
• j is the polynomial term index.

To determine the coefficients a_kj of the filter stage, one can alternatively employ the design techniques in [3,4,5,6] for least-squares or [7,8,9,10] for minimax. To obtain the polynomial coefficients using least-squares fitting, the Vandermonde matrix for an Sth order polynomial with the provided x_i values [x₀, x₁, x₂,… x_s] will be created as powers of x. $V_{ij}=x_i^j$ and is provided by Equation (3):

$$V=\left[\begin{array}{ccccc}1& x_0^1& x_0^2& \dots & x_0^S\\ 1& x_1^1& x_1^2& \dots & x_1^S\\ 1& x_2^1& x_2^2& \dots & x_2^S\\ ⋮& ⋮& ⋮ & \dots & ⋮\\ 1& x_S^1& x_S^2& \dots & x_S^S\end{array}\right],$$

(3)

where

• V is the Vandermonde matrix employed in least-squares polynomial fitting;
• x_i denotes the ith sampled cutoff frequency value used to construct the approximation grid, v_ij = x_i^j represents the matrix element at row i and column j;
• S is the polynomial order;
• i,j = 0, 1,…, S indicate the matrix indices.

The Vandermonde matrix in Equation (3) could not be very stable for very high polynomial orders. The suggested design reduces this issue by employing a least-squares formulation and selecting a reasonable polynomial order. Coefficient estimation is dependable and the filter response is not significantly impacted since the polynomial order employed for coefficient modeling is small enough to keep the matrix stable.

A particular x_i value raised to powers 0, 1, 2, …, S is represented by each row. The matrix is prepared for least-squares fitting of the polynomial coefficients. Assume that the target data y is the filter coefficients or any sampling values. To find the polynomial coefficients, Equation (4) below must be solved using the least-squares formula:

$$\mathrm{a}={\left({\mathrm{V}}^{\mathrm{T}}\mathrm{V}\right)}^{-1}{\mathrm{V}}^{\mathrm{T}}\mathrm{y},$$

(4)

where

• V is the Vandermonde matrix;
• y is the target data;
• a is the vector of polynomial coefficients.

The SPA filter exhibits a constant transition bandwidth and uninterrupted tunability of f_c within the specified tuning range.

2.2. Examination of the ISPA Approach

Let f_cmin(0) to f_cmax(1) be the required f_c range. Then, the proposed ISPA filter, as illustrated in Figure 2, is intended to deliver dynamically changing f_c over a minimal frequency band, within the frequency limits of f_c1 and f_c2, featuring reduced transition bandwidths of tbw_mod/M.

A response across multiple bands, represented as “H_A”, exhibiting critical frequencies occurring around f_Ai ± f_c/M, is produced in the case where a model low-pass filter for which the critical frequency f_c is enhanced through interpolation by a variable of M. The transfer function H_A yields band center frequencies defined by Equation (5):

$${\mathrm{f}}_{\mathrm{A}\mathrm{i}}={\displaystyle \frac{2\mathrm{i}}{\mathrm{M}}},\mathrm{i}=0 \mathrm{to} \mathrm{M}-\left[{\displaystyle \frac{M}{2}}\right]$$

(5)

By subtracting the transfer function H_A from the correctly delayed input yields the complementary response, or “H_C”, which is obtained concurrently. The cutoff frequencies of the frequency response H_C are expressed as f_Ci ± (1 − f_c)/M, whereas their mid frequencies are determined using Equation (6):

$${\mathrm{f}}_{\mathrm{C}\mathrm{i}}=\left({\displaystyle \frac{2\mathrm{i}+1}{\mathrm{M}}}\right),\mathrm{i}=0 \mathrm{to} \left[{\displaystyle \frac{\mathrm{M}}{2}}\right]-1$$

(6)

With a filter cutoff of f_Ai + f_c/M (for k = i + 1 and j = i) or f_Ci−1 + (1 − f_c)/M (for k = i and j = i), a low-pass response is produced by extracting and adding the k leading bands extracted out of the transfer function H_A and the leading bands indexed by j in the H_C transfer function. With tbw_mod being the tbw associated with the prototype filter, the tbw value belonging to this low-pass behavior is tbw_mod/M.

Using the SPA approach, the original low-pass filter model of the ISPA filter is designed to have a continuously variable cutoff frequency, where f_c1 < f_c ≤ f_c2. After that, as previously stated, the critical frequencies observed in the generated low-pass responses are constantly changing as follows: f_Ci−1 + (1 − f_c2)/M < f_Ci−1 + (1 − f_c)/M ≤ f_Ci−1 + (1 − f_c1)/M ≤ f_Ci−1 + (1 − f_c1)/M.

M ∈ M_set = {M_min,… M_max} in the ISPA filter so that the boundaries of f_Ai + f_c/M and f_Ci−1 + (1 − fc)/M described above superimpose and provide an unbroken range. As a result, the ISPA filter’s band-edge frequency (f_{c_ISPA}) is steadily changeable between f_c1/M_max and 1 − (f_c1/M_max) and is determined by Equation (7):

$${\mathrm{f}}_{\mathrm{c}\_\mathrm{I}\mathrm{S}\mathrm{P}\mathrm{A}}=\left\{\begin{array}{c}{\mathrm{f}}_{\mathrm{A}\mathrm{i}}+{\displaystyle \frac{{\mathrm{f}}_{\mathrm{c}}}{\mathrm{M}}} \mathrm{for} \mathrm{k}=\mathrm{i}+1 \mathrm{and} \mathrm{j}=\mathrm{i}\\ {\mathrm{f}}_{\mathrm{C}\mathrm{i}-1}+{\displaystyle \frac{(1-{\mathrm{f}}_{\mathrm{c}})}{\mathrm{M}}} \mathrm{for} \mathrm{k}=\mathrm{i} \mathrm{and} \mathrm{j}=\mathrm{i}\end{array}\right.$$

(7)

Equations (1)–(7) illustrate the arithmetic underlying the SPA/ISPA filter. Equation (1) displays the total frequency response as a weighted sum of the subfilter responses. Equations (2)–(4) demonstrate how to express and estimate filter coefficients as polynomials using the Vandermonde matrix. Band responses and the adjustable cutoff frequency are explained by Equations (5)–(7). This allows you to alter the filter response at any time while maintaining the same characteristics as the FIR filter prototype.

Table 1. Differences between SPA, ISPA, ISFT and MCDM methods.

Method	Principle	Strengths	Limitations
SPA	Spectral parameter approximation using polynomial expansion	Wide tuning range, sharp transitions	Parallel complexity, high DSP usage
ISPA	Interpolated SPA with masking filters	Full Nyquist range, improved selectivity	Increased filter stages, high area
ISFT	Spectral frequency transformation	Reduced multipliers	Limited tuning resolution, distortion
MCDM	Modified coefficient decimation	Lower coefficient storage	Spectral replicas, limited fc range
Proposed MAC-SPA/MAC-ISPA	Time-multiplexed MAC realization of SPA/ISPA	Ultra-low DSP, low power, high scalability	Slight increase in latency (acceptable in SDR)

provides the differences between the SPA, ISPA, ISFT and MCDM methods. SPA provides wide tuning at the cost of high complexity and DSP usage, whereas ISPA boosts selectivity at the cost of larger area. ISFT minimizes multipliers but limits tuning resolution, whereas MCDM minimizes storage with cutoff constraints. On the other hand, the suggested MAC-SPA/MAC-ISPA achieves high scalability, low power, and ultra-low DSP utilization with minimal latency overhead.

The architectural contrast is summarized in

Table 2. Comparison table summarizing prior methods.

Design	DSPs	LUTs	Power	Tunability	Scalability
Farrow FIR	Very High	Very High	High	Excellent	Poor
Parallel SPA	Extremely High	Extremely High	Very High	Excellent	Poor
ISPA-PM FIR	High	High	High	Very Good	Moderate
MCDM	Low	Moderate	Moderate	Limited	Good
Proposed MAC-SPA/MAC-ISPA	1 DSP	Very Low	Very Low	Excellent	Excellent

, which also highlights the substantial hardware and power overhead of parallel SPA, standard Farrow, and similar systems. On the other hand, by achieving single-DSP implementation with extremely low resource and power consumption while keeping great tunability and scalability, the proposed MAC-SPA/MAC-ISPA approach indicates its architectural advantages.

3. Suggested FIR Filter Based on Single-Channel MAC

This brief presents a filter structure utilizing TDM that employs a standalone multiply-and-add stage independent of the overall channel count and taps and based on the resource-sharing principle. The resource-sharing principle is applied, and the filter’s operating frequency is raised.

Delay modules and multiplication units, which acquire the form of an MAC, are the main structural elements of the FIR filter. The primary factor influencing the FIR filter’s performance is the multiplier’s speed, which defines the critical path inside the filter configuration.

Consider an FIR filter with x(n) as the input and y(n) representing the output and length of N with an impulse response of h[k]. The output of the conventional parallel FIR filter is the discrete convolution which is given by Equation (8):

$$\begin{array}{cccc}& y[n]=\sum _{k=0}^{N-1}h\left[k\right]x[n-k]& & \end{array}$$

(8)

where $x\left[n\right]$ is the input signal and $y\left[n\right]$ is the filter output.

Assume that the filter coefficients are separated into S SPA subfilters, each of which has N coefficients. Then the total number of coefficients of the entire FIR filter is given by Equation (9):

$$\begin{array}{cccc}& N_{total}=S\times N& & \end{array}$$

(9)

The convolution sum can then be divided into S partial sums which are provided by Equation (10):

$$\begin{array}{cccc}& y[n]=\sum _{i=0}^{S-1}\sum _{k=0}^{N-1}h[iN+k]x[n-(iN+k\left)\right]& & \end{array}$$

(10)

Every inner sum has a single SPA subfilter output.

In a conventional parallel architecture, each subfilter is evaluated simultaneously, as expressed in Equations (11) and (12):

$$\begin{array}{cccc}& y[n]=\sum _{i=0}^{S-1}{y}_i[n]& & \end{array}$$

(11)

where

$$\begin{array}{cccc}& y_i[n]=\sum _{k=0}^{N-1}h[iN+k]x[n-(iN+k\left)\right]& & \end{array}$$

(12)

In the proposed architecture, the identical operations are performed one MAC unit at a time. The partial accumulation that happens after processing the ith subfilter is provided by Equation (13):

$$\begin{array}{cccc}& A_i[n]=A_{i-1}[n]+\sum _{k=0}^{N-1}h[iN+k]x[n-(iN+k\left)\right]& & \end{array}$$

(13)

with the initialization specified by Equation (14),

$$\begin{array}{cccc}& A_{-1}\left[n\right]=0& & \end{array}$$

(14)

When all the S subfilters have been employed, the final output is provided by Equation (15):

$$\begin{array}{cccc}& y[n]=A_{i-1}\left[n\right]& & \end{array}$$

(15)

The suggested architecture’s operation is determined by time-multiplexed MAC scheduling. It requires N × S MAC operations to create a single output sample from an FIR filter with N taps and S SPA subfilters. This indicates that the latency is L = N × S + L_p, where L_p is the pipeline’s delay. For the 80-tap, 12-branch employed configuration, 960 MAC cycles are required. With a four-stage pipeline, the overall latency is approximately 964 cycles (3.7 μs at 260 MHz), indicating a throughput of roughly 270 kSamples/s. Although the architecture uses a single shared-MAC unit to reduce hardware costs, latency is higher than in completely parallel implementations.

A computational complexity analysis shows that the shared-MAC framework lowers multiplier requirements from a number proportional to the filter length in traditional parallel FIR implementations to a constant number independent of the filter length, even though computation time increases linearly with filter length, polynomial order, and channel count. This temporal–spatial tradeoff enables scalable realization without datapath duplication. Furthermore, by introducing a controllable modeling error that is dependent on the approximation order, the SPA polynomial approximation provides an analytical basis for performance–complexity tuning

An FIR filter consisting of N taps consumes N clock cycles to finish its action. Assume, with an FIR filter containing length four, the input acquisition rate is configured at 1 MSPS, and the occurrence of samples coming from the final filter is increased to four MSPS. It takes four clock cycles to generate the output.

Use the multiplier to choose the data from each register and perform the multiplier operation. Instead of keeping the coefficients in registers, they reside in a 256 × 8 RoM to reduce transition activity. The results produced by the multiplier are summed up through an accumulator module that is subsequently set back to zero following four cycles of the clock.

The lines used to select the multiplexer inputs, filter tap value memory location array, and accumulator process are all chosen using a common counter. In the same way, N taps are achievable with an individual multiply–add unit with the help of registers that enhance the frequency of operation of the FIR filter. As a result, an FIR filter with eight taps, employs eight MSPSs at a one MSPS sampling rate. It takes N clock cycles to find the result of a filter which has N taps.

A single MAC unit performs filter operations sequentially in the proposed time-division multiplexed architecture. As a result, each output sample requires approximately N × S clock cycles to calculate an N-tap filter of polynomial order S, adding a fixed processing delay. This delay is the amount of time required for the MAC-based solution to process the sequential coefficient evaluation.

Throughput and delay are traded off in the proposed design since MAC processing takes place sequentially. Sequential computation requires more clock cycles to produce each output sample, but by substituting a single shared-MAC unit for multiple parallel multipliers, it saves a significant amount of hardware. This improves the power and hardware efficiency.

Resource sharing is achieved in the proposed architecture by time-multiplexed use of arithmetic units, namely the multiplier and accumulator blocks. Instead of assigning distinct hardware for every filter tap, polynomial term, or channel, a single MAC unit is reused over successive clock cycles. Multiplexers are utilized at the inputs of the shared arithmetic units to choose appropriate delayed samples, coefficients, and channel data under the guidance of an address generator and scheduling counters. By consecutively advancing the tap, polynomial, and channel indices, the shared-MAC unit can compute partial products that are accumulated through feedback registers until the output sample computation is completed. This time-multiplexed scheduling method effectively reduces the hardware resource needs without sacrificing functional correctness.

3.1. Effective FIR Filter Design Using One MAC Unit-Based SPA Method

Utilizing an architecture employing one MAC block constructed using TDM and utilizing the shared use of resources concept, Figure 3 demonstrates the SPA technique using an FIR filter to achieve an MAC-SPA filter. By substituting the S + 1 filter stages found in the SPA method, the output of the SPA methodology employing single-channel MAC was created.

Figure 3 depicts the time-division multiplexed MAC-based filter’s architecture. Input samples are kept in a register chain to create delayed signals. Coefficients are stored in ROM, and a counter controls data scheduling and coefficient addressing. A registered adder adds the multiplications that the shared multiplier does one at a time to create the filter output. This design simplifies the hardware by enabling a single MAC unit to manage all of the filter taps.

The proposed 80-tap FIR filter is implemented using a time-multiplexed MAC architecture with 12 Spectral Partitioned Approximation subfilters. The design is fully pipelined with registered multiplier and accumulator stages to ensure dependable operation at 200 MHz (5 ns clock period), restricting the critical path to a multiplication, addition, and register stage; post-route static timing analysis confirms zero negative slack, which indicates successful timing closure under the given clock constraint. Pseudocode for MAC scheduling in a single-MAC SPA filter is given by Algorithm 1:

Algorithm 1: Time–Multiplexed MAC–Based SPA FIR Filter.

1:    Input: x[n], coefficient matrix h[S][N], interpolation index μ 2:    Output: y[n] 3:    Initialize: 4:            acc ← 0 5:            tap_idx ← 0 6:            sub_idx ← μ 7:    for each clock cycle do 8:            acc ← acc + h[sub_idx][tap_idx] × x_shift[tap_idx] 9:            if tap_idx == N − 1 then 10:                 tap_idx ← 0 11:                 if sub_idx == S − 1 then 12:                         y_out ← acc 13:                         y_valid ← 1 14:                         acc ← 0 15:                         sub_idx ← μ 16:                 else 17:                         sub_idx ← sub_idx + 1 18:                 end if 19:         else 20:                 tap_idx ← tap_idx + 1 21:         end if 22: end for

The MAC scheduling approach uses a deterministic Time-Division Multiplexing technique to iteratively traverse all filter taps and subfilters using a single-DSP-based MAC unit. Two nested counters regulate the scheduling sequence, ensuring that every coefficient–sample multiplication is performed exactly once for every output sample. After N_SUB × N_TAPS MAC procedures are finished, the aggregated result is recorded as the filter output. This scheduling ensures functional comparability with the fully parallel SPA and ISPA realizations while achieving notable reductions in hardware complexity and power consumption.

The proposed MAC-SPA and interpolated MAC-SPA FIR filters employ two’s complement fixed-point arithmetic to reduce hardware complexity, power, and delay for FPGA/ASIC implementations. Both input samples and coefficients are stored in the Q1.15 (16-bit signed) format. To avoid overflow across 80 taps and 12 subfilters, the 32-bit product produced by the MAC operation is accumulated using a 40-bit accumulator. The output can be scaled or shortened to 16 bits if needed, but it is kept at 40 bits. This approach provides efficient hardware use and good signal accuracy.

The single-MAC architecture, which assumes a greater system clock than the input sample rate, enables sequential MAC operations. Additionally, it requires latency-tolerant apps and enough memory bandwidth. Scalability is achieved through control-driven iteration, which keeps hardware complexity constant while calculation time increases linearly.

The proposed architecture provides a tradeoff between speed and area because of the shared-MAC unit. Unlike parallel FIR filters with specialized multipliers, the time-multiplexed approach uses less hardware but increases computation cycles and delay by reusing a single MAC across taps. A higher MAC clock frequency lowers throughput loss, and additional MAC units can be added if more speed is required.

The proposed MAC-SPA and interpolated MAC-SPA FIR filter architectures provide continuous cutoff frequency tweaking with low DSP and power consumption, making them suitable for SDR, cognitive radio, satellite payloads, and multi-standard wireless receivers. By offering real-time spectral adaptability while maintaining high stopband attenuation and low passband distortion, they meet the requirements of modern reconfigurable communication systems.

3.2. Effective FIR Filter Structure of ISPA Based on One MAC Unit

Set the MAC-ISPA filter’s intended f_c range from 0.055 to 0.945. Then, 0.055 ≤ f_{c_MAC ISPA} < 0.945 is guaranteed by f_c1 = 0.33 and M_set = {2, 3, 4, 6}. Consider {δ_{p_final}, δ_{s_final}, tbw_final} = {0.1 dB, −40 dB, 0.035}. Next, an ISPA filter prototype with N = 80 and L = 11 is built to satisfy f_c1 ≤ f_c ≤ 0.5 for 0 < α ≤ 1 and {δ_{p_mod}, δ_{s_mod}, tbw_mod}. In accordance with the masking filter design in [13], a pair of masking filters, one of order 72 and the other of order 52, are created. Sub-masking filters are arranged as 14, 24, 20, and 20. The ISPA filter’s tbw fluctuates between 0.012 and 0.035. With tbw < 0.025, this MAC-ISPA filter continuously regulates f_{c_MAC ISPA} in the 0.055–0.945 range.

The interpolation utilized to alter the cutoff frequency is what causes the variation in transition bandwidth. The transition bandwidth varies over the tuning range, but it remains within a constrained range while still satisfying the stopband attenuation and passband ripple criteria. The spectral performance is maintained over the whole operating frequency range because of this controlled variation.

In order to increase the tunable cutoff range near the Nyquist limit during the interpolation process while maintaining the spectral properties of the prototype filter, the parameter f_c1 is selected as the prototype cutoff frequency. The selected interpolation factors maintain an easily manageable amount of coefficient sets and masking filters while providing adequate frequency scaling resolution. This allows for a wide range of cutoff frequency tuning without overcomplicating the hardware.

Both the hardware complexity and the approximation’s accuracy are impacted by the polynomial order S. Increasing S increases the accuracy of coefficient interpolation in relation to the cutoff frequency, but it also necessitates the storage of additional coefficients and arithmetic operations, which complicates memory and control. The accuracy of frequency tuning is also influenced by the cutoff frequency resolution. Higher resolution improves tuning accuracy, but improper capture of coefficient changes may exacerbate the approximation error. In order to achieve a suitable balance between accuracy and hardware efficiency, the appropriate parameters are selected for the proposed MAC-ISPA filter.

Figure 4 illustrates the ISPA technique using the FIR filter, which uses a TDM-based single-MAC design that utilizes the resource-sharing idea to produce an MAC-ISPA filter. By using a single MAC, the S + 1 filter stages and masking filters 1 and 2, which are components of the ISPA method, were replaced to produce the MAC-ISPA approach’s outcome. This filter accomplishes nearly the entire Nyquist band, a compact transition bandwidth, a very large f_c range, minimum passband ripple, good stopband attenuation, and fewer multipliers than ISPA filters.

4. Results of the Experiment

This portion presents the filter architecture and synthesis performance of the suggested technique. The proposed approach does more than just provide a variable-coefficient filter. Instead, it offers a resource-efficient architectural method for realizing multi-branch SPA-based FIR filters using a time-multiplexed single-MAC structure. Unlike previous parallel SPA or Farrow implementations, which need separate MAC units for each subfilter branch, the proposed architecture employs a deterministic scheduling technique that translates the operations of 12 SPA subfilters onto a single common MAC unit. This technique preserves the mathematical filtering function while significantly reducing power consumption, DSP usage, and hardware resources. Therefore, the contribution is found in the hardware-efficient architectural realization of SPA-based reconfigurable FIR filters instead of a simple variable-coefficient filter implementation.

4.1. Results of the Synthesis for a Single-MAC-Based SPA Method

Altera and Xilinx platforms are used to synthesize topologies for MAC SPA filters. Figure 5 displays the internal MAC scheduling, the clock (clk), reset (rst), and enable (en) signals. During the first reset phase, all internal registers are set to zero, including the input delay line, accumulator, tap index, and subfilter index. After reset (rst) is deserted and enable (en) is asserted, the design begins transferring input samples into the delay line and executing the MAC sequence.

The enable signal is continuously asserted during the simulation, reflecting standard SDR operation where the filter manages streaming data. For every input sample period, the MAC unit multiplies each delayed input sample by the active subfilter’s matching coefficient. The tap index (tap_idx) iterates from 0 to 79, but the subfilter index (sub_idx) cycles from 0 to 11. The accumulator (acc) aggregates all products that correspond to a single full filter evaluation. After the final tap of the final subfilter is processed, the total result is reported at the output. This predictable scheduling ensures that the time-multiplexed MAC produces results algebraically similar to a fully parallel SPA implementation, despite the greater latency.

The functional correctness of the proposed single-MAC SPA FIR filter with 12 subfilters and 80 taps per subfilter was verified via RTL simulation. The proposed MAC-SPA architecture requires 960 clock cycles to compute all 80 taps over 12 SPA subfilters. At the achieved maximum frequency of 260 MHz, this corresponds to an effective processing throughput of about 0.27 MSPS. A range of input stimuli, including impulse, step, ramp, and sinusoidal signals, was employed to confirm linearity, stability, and frequency-selective behavior. Deterministic MAC scheduling, correct input sample propagation across the delay line, and accurate accumulation across all subfilters are all confirmed by simulation waveforms. Significant hardware reuse is accomplished, and the output’s stability between legitimate update instants and updates only after the complete MAC cycle shows functional equivalency to a parallel SPA realization. These results validate the suitability of the proposed architecture for area-efficient SDR filtering applications.

The time-multiplexed single-MAC architecture has a fixed computational latency of 960 cycles (≈9.6 μs at 100 MHz), producing one acceptable output sample per N × S = 960 clock cycles after an initial pipeline fill.

The TDM scheduling in the suggested architecture does not introduce output jitter because every action is synced to the same clock. The output time and the number of clock cycles per sample are constant because a counter-controlled schedule ensures that the MAC operations occur in a predetermined order.

The fixed-point Verilog implementation and a MATLAB (R2025b) behavioral model using the identical Q1.15 coefficients and a 32-bit accumulator were compared. The time-domain outputs of both systems are similar, as seen in Figure 6. Due to fixed-point rounding effects, the difference was only 1–2 LSB. The output signal-to-noise ratio was above 80 dB and the mean-square error was approximately 10⁻⁶, indicating that the suggested FPGA architecture was numerically identical to the floating-point reference model.

Table 3. The FPGA synthesis results of the proposed MAC SPA 12 × 80 FIR filter built on a Xilinx Virtex-7 chip.

Design	LUTs	FFs	DSP48E1	BRAM	fmax (MHz)	Power (mW)	Power Reduction
Proposed MAC-SPA	3800	5200	1	2	260	210	-
ISPA-PM FIR [15]	18,000	12,000	120	6	210	820	74.4% ↓
Farrow SPA FIR [14]	38,000	24,500	960	0	180	1450	85.5% ↓
DSP-LUT Hybrid FIR [25]	9200	7800	32	3	240	420	50.0% ↓
CSD-based FIR [26]	6500	6200	24	2	230	350	40.0% ↓

displays the FPGA synthesis results of the proposed MAC SPA 12 × 80 FIR filter built on a Xilinx Virtex-7 chip. The time-multiplexed MAC approach allows for the use of one DSP slice while retaining predictable performance. In comparison to ISPA-PM-FIR [15] and Farrow SPA [14] implementations on Virtex-7, the proposed design uses only 3800 LUTs and 5200 FFs, which are significantly lower than the 18,000 LUTs and 12,000 FFs in [15] and the 38,000 LUTs and 24,500 FFs in [14]. A major improvement is seen in DSP usage, with only one DSP48E1 required, compared with 120 in [15] and 960 in [14]. BRAM usage is limited to two blocks, lower than [15] and comparable with [14]. Despite the reduced hardware, the proposed method achieves a higher operating frequency of 260 MHz, exceeding [15] and [14], while consuming only 210 mW, which is much lower than both designs. These results confirm that the proposed MAC–SPA design delivers substantially higher computational and energy efficiency while maintaining superior throughput, filling a gap in the empirical characterization of SPA-based FIR filters for FPGA applications.

Compared to other recent FPGA FIR realizations such as the DSP–LUT hybrid FIR architecture [25] and the CSD-based FIR implementation [26], which reduce arithmetic complexity through efficient coefficient encoding and DSP–LUT resource sharing, respectively, the proposed architecture further improves hardware efficiency by combining spectral parameter approximation (SPA) polynomial evaluation with a time-multiplexed MAC datapath. The proposed design, which achieves about 40–50% lower power consumption than these architectures while maintaining a competitive operating frequency of about 260 MHz on the Virtex-7 FPGA platform, demonstrates the efficiency of the MAC-SPA approach for resource-constrained FPGA implementations as summarized in Table 3.

The Xilinx Vivado Power Analyzer was used to obtain the power levels shown in Table 3 after post-synthesis and post-place-and-route implementation on the Virtex-7 FPGA. Using realistic input data patterns, switching activity was recovered from post-implementation functional simulations to assess both dynamic and static power. The power analysis program was then used to back-annotate the generated VCD files. All architectures were evaluated under identical working settings, such as the same FPGA device, clock limitations, and input stimulus patterns, to guarantee a fair comparison of designs.

The proposed reconfigurable filter was created using 0.18 µm CMOS technology, and the data is summarized in

Table 4. Comparison of MAC SPA filter with reconfigurable digital filters.

	Multiplier Count	Group Delay (in Samples)
Suggested MAC SPA filter	21	10
ISPA filter [22]	610	360
ISFT filter [13]	188 (−69%)	600 (+67%)
SPA-MCDM filter [12]	1435 (+135%)	69 (−81%)

. When compared to current approaches with the closest values, the proposed MAC-SPA filter shows notable advantages in both hardware complexity and signal processing delay. In particular, the ISFT filter from [13], which has the closest multiplier count among current approaches, requires 188 multiplies, while the suggested filter only needs 21 multipliers. This highlights the hardware efficiency of the suggested solution by reducing the number of multipliers by 167. With a group delay of only 10 samples, the suggested filter outperforms the closest current technique, the SPA-MCDM filter from [12], which has a group delay of 69 samples. The suggested filter is ideal for real-time and low-latency applications since it ensures minimal processing delay by reducing the number of samples by 59.

The results of testing and evaluating the proposed reconfigurable filter on a Xilinx xc6vlx760-1ff1760 are listed in

Table 5. Evaluation of programmable digital filters for FPGA implementation using the MAC SPA method.

		Occupied Slices Count	Post-PAR Minimum Period (in ns)	Post-PAR Maximum Operating Speed (in MHz)	Group Delay (in Samples)
Suggested MAC SPA filter		43,179	3.299	303.14	10
ISPA filter [22]		66,593	10.706	93.406	376
ISFT filter [13]		56,189 (−16%)	12.752	78.419	699 (+86%)
Variable- coefficient filter [1]	(cutoff frequency resolution of 0.000089)	46,385 (−30%)	2.988	334.672	66 (−82%)
	(cutoff frequency resolution of 0.000054)	61,807 (−7%)	5.203	192.197

. When compared to other reconfigurable filter designs, the suggested MAC-SPA filter exhibits a significant improvement in operation speed and resource usage. The variable-coefficient filter from [1], with a cutoff frequency resolution of 0.000089, occupies 46,385 slices, the closest value among the options listed, but the suggested filter uses 43,179 slices. This shows improved hardware efficiency with a 7% decrease in slice use with the suggested configuration. Additionally, the closest technique, the variable-coefficient filter from [1], with cutoff resolution 0.000089, operates at 334.672 MHz, whereas the suggested MAC-SPA filter reaches a maximum operating speed of 303.14 MHz. This translates into a modest 9.4% decrease in the suggested filter’s operating speed. The suggested design, however, yields a substantially shorter group delay and reduced slice count, making it more appropriate for applications where low-latency performance and hardware efficiency are crucial, even with a small speed difference.

The frequency response of the 80-tap FIR prototype, which is used to evaluate the effectiveness of the ISPA-based filter, is displayed in Figure 7. As required by the design, the magnitude response has a stopband attenuation of approximately −40 dB and a smooth passband with around 0.1 dB ripple. As anticipated for a linear-phase FIR, the phase response is nearly linear.

The frequency-domain performance comparison between the proposed MAC-SPA FIR filter and existing architectures is summarized in

Table 6. Frequency-domain behavior of the proposed MAC SPA FIR.

Design	Passband Ripple (dB)	Stopband Attenuation (dB)	Transition BW
Farrow SPA FIR	0.12	65	Wide
ISPA-PM FIR	0.08	72	Medium
Proposed MAC-SPA FIR	0.03	85	Sharp

. With a passband ripple of 0.03 dB and stopband attenuation of 85 dB, the proposed design performs better than the ISPA-PM FIR and Farrow SPA FIR implementations. Additionally, the proposed architecture exhibits a sharper transition bandwidth, indicating effective stopband suppression and improved spectral selectivity. These results validate the superior frequency-domain behavior of the proposed filter architecture.

4.2. Synthesis Results for an ISPA Approach Based on a Single MAC

This portion presents the filter architecture and synthesis performance of the suggested MAC ISPA architecture and compares its efficiency to that of the traditional designs. Altera and Xilinx platforms are used to synthesize topologies for MAC ISPA filters.

The FIR filter’s simulated waveform is shown in Figure 8. The proposed single-MAC interpolated SPA FIR filter with 12 subfilters of length 80 was functionally evaluated using the behavioral simulation in Riviera-PRO. An active-high reset and a synchronous clock with a 10 ns cycle were used to initialize the internal delay line, accumulator, and control counters. The input signal x[n] was configured as a step sequence with an amplitude of 1000 applied for the first 200 clock cycles, followed by zeros, to mimic a baseband stimulation commonly used for FIR validation. To approximate a fractional delay operating point, the interpolation factor α was kept at 0.5 throughout the experiment.

To generate the output signal y_out, a single time-multiplexed multiply–accumulate (MAC) unit progressively processes the taps of each subfilter. The control signal y_valid is used to designate a valid output sample once all N = 80 taps across S = 12 subfilters have been finished. Consequently, N × S = 960 clock cycles is the overall processing latency between the application of an input sample and the availability of the associated output. The simulation waveforms ensure correct and precise accumulation of all tap contributions by confirming that y_out only changes when y_valid is affirmed. The observed output response, which is consistent with the expected FIR filtering behavior, validates the functional soundness of the proposed MAC-SPA interpolation design.

Figure 9 shows a netlist depiction of the MAC ISPA filter using one channel. The MAC and RAM are essential parts of the FIR filter multiplexer with multi-channel area calculation. Utilizing Xilinx xc6vlx760-1ff1760 FPGA device, the suggested structure is utilized and produced.

A time-multiplexed single-multiplier architecture that substitutes coefficient and data sequencing for parallel multiplier replication is validated by the 12 × 80 MAC-ISPA subfilter schematic. Unlike standard FIR structures that require 80 parallel multipliers and a broad adder tree, the proposed design reuses a single MAC unit with staged accumulation, which significantly minimizes hardware duplication and interconnect complexity. This structural compression reduces gate count by 73–88% in ASIC synthesis and DSP by >99% in FPGA implementation. Less routing congestion also shortens the critical path and lowers dynamic switching activity, which enables up to 86% energy savings and a 25–52% rise in operating frequency. These benefits are the consequence of architectural transformation rather than technology-specific optimization.

A detailed explanation of the synthesis environment, toolchain, FPGA device, clock constraints, and implementation settings used to obtain the reported findings is given to make it easier to replicate. The Xilinx Vivado toolchain was used to create the design, which was intended to function with a Virtex-7 FPGA with a 4 ns clock limit. Power estimates were obtained using post-implementation power analysis, and switching activity was extracted from simulation waveforms.

Table 7. The FPGA synthesis results of the proposed MAC ISPA 12 × 80 FIR filter built on a Xilinx Virtex-7 chip.

Design	LUTs	FFs	DSP48E1	BRAM	fmax (MHz)	Power (mW)
Proposed MAC-ISPA	4600	6800	1	3	270	240
ISPA-PM FIR [15]	18,000	12,000	120	4	210	820
Farrow SPA FIR [14]	38,000	24,500	960	0	180	1450

compares the FPGA synthesis results for a 12-subfilter, 80-tap configuration of the proposed MAC-based ISPA design with the ISPA-PM FIR and the conventional Farrow SPA FIR. The proposed design requires only 4600 LUTs and 6800 FFs, which are much lower than the 18,000 LUTs and 12,000 FFs in [15] and the 38,000 LUTs and 24,500 FFs in [14]. A major improvement is observed in DSP utilization, with only one DSP48E1 used, compared with 120 in [15] and 960 in [14]. BRAM usage is limited to three blocks, lower than [15] and modest compared with [14]. Despite the reduced hardware, the proposed method achieves a higher maximum operating frequency of 270 MHz, exceeding [15] and [14], while consuming only 240 mW, which is significantly lower than both designs. These results demonstrate that the recommended MAC-based ISPA designs offer a good tradeoff between area, power, and frequency, making them perfect for dynamically reconfigurable and energy-constrained SDR applications.

The designs listed in Table 3 and Table 7 have been re-implemented and re-synthesized on a Xilinx Virtex-7 device employing a standard synthesis toolchain and temporal constraints to guarantee consistent evaluation. The measurements utilized for Virtex-6 devices that were taken from their individual publications match the outcomes displayed in the following comparison tables.

With the aid of a 0.18 µm CMOS-based fabrication, the intended reconfigurable filter has been synthesized, and the data are reported in

Table 8. Comparison of MAC ISPA filter with reconfigurable digital filters.

	Multiplier Count	Group Delay (in Samples)
Suggested MAC ISPA filter	25	12
ISPA filter [22]	610	360
ISFT filter [13]	188 (−69%)	600 (+67%)
SPA-MCDM filter [12]	1435 (+135%)	69 (−81%)

. When compared to current designs using the nearest values, the proposed MAC-ISPA filter dramatically lowers both hardware complexity and signal delay. The ISFT filter from [13], which has the closest multiplier count among the current approaches, requires 188 multiplies, a reduction of 163 multiplications, while the suggested filter only needs 25 multipliers.

The suggested filter achieves a group delay of only 12 samples, which is significantly less than the 69 samples of the SPA-MCDM filter from [12], the approach with the closest group delay. This results in a 57-sample reduction, increasing the suggested filter’s effectiveness for low-latency, real-time signal processing applications. These results unequivocally demonstrate that the suggested MAC-ISPA filter has continuous control of the cutoff frequency, with significant hardware reductions and performance improvements over traditional systems.

The results of testing and evaluating the proposed reconfigurable filter on an Xilinx xc6vlx760-1ff1760 FPGA are listed in

Table 9. Evaluation of programmable digital filters for FPGA implementation using the MAC ISPA method.

		Occupied Slices Count	Post-PAR Minimum Period (in ns)	Post-PAR Maximum Operating Speed (in MHz)	Group Delay (in Samples)
Suggested MAC ISPA filter		44,179	3.47	288.18	12
ISPA filter [22]		66,593	10.706	93.406	376
ISFT filter [13]		56,189 (−16%)	12.752	78.419	699 (+86%)
Variable- coefficient filter [1]	(cutoff frequency resolution of 0.000089)	46,385 (−30%)	2.988	334.672	66 (−82%)
	(cutoff frequency resolution of 0.000054)	61,807 (−7%)	5.203	192.197

. The suggested MAC-ISPA filter operates at a maximum speed of 288.18 MHz while utilizing 44,179 occupied slices. The suggested approach demonstrates a reduction of roughly 4.76% in occupied slices when compared to the variable-coefficient filter from [1], which employs 46,385 slices. The suggested MAC-ISPA filter works at a lower speed by about 13.89% compared to the variable-coefficient filter from [1], which reaches a higher working speed of 334.672 MHz.

The simulation framework used MATLAB behavioral modeling and cycle-accurate Verilog implementation to validate the proposed MAC-SPA architecture. An 80-tap FIR filter with 12 SPA branches was evaluated using Q1.15 fixed-point inputs and coefficients and a 32-bit accumulator to ensure overflow-free MAC operations. Sinusoidal, impulse, and pseudo-random input signals were employed to verify steady-state responsiveness, impulse response accuracy, and numerical stability. By comparing the fixed-point outputs with double-precision MATLAB reference results using measures including maximum absolute error, MSE, and SNR, numerical comparability within fixed-point bounds was verified.

Nevertheless, this tradeoff results in a significant decrease in hardware consumption, making the suggested approach more space-efficient with a slight speed tradeoff

Using input test signals created in MATLAB and quantized to the Q1.15 fixed-point format during experimental evaluation, the suggested 12 × 80 MAC-SPA FIR filter was constructed in Verilog. A time-multiplexed MAC unit successively multiplied the input samples with coefficients from the 12 SPA subfilters after an 80-stage shift-register delay line. Partial products were accumulated over a number of clock cycles to perform the convolution procedure. The fixed-point outputs were recorded via waveform dumping, and their accuracy and numerical correctness were verified by comparing them with a double-precision MATLAB reference model.

The suggested MAC-SPA design achieves a 73–88% decrease in gate count and silicon area, 68–85% lower power consumption, and 69–86% lower energy per output for the 12 × 80 subfilter configuration when compared to ISPA-PM and Farrow SPA ASIC implementations. Additionally, the Virtex-7 platform’s FPGA implementation demonstrates a decrease in LUT use of 79–90%, a decrease in DSP slice usage of over 99%, a decrease in power consumption of 74–85%, and an increase in operating frequency of up to 44%. These steady gains on both ASIC and FPGA platforms verify that multiplier reuse, not technology-dependent optimization, is the main way the suggested architecture increases structural efficiency.

Time-domain waveforms of the input and filtered output signals are presented in Figure 10 to validate the proposed MAC-SPA and interpolated MAC-SPA FIR filter topologies. Three test examples are presented: band-limited noise signals sampled at f_s = 40 MHz, single-tone, and multi-tone. The results, which demonstrate stopband suppression and passband preservation, validate the frequency-domain analysis. The TDM scheduling and pipeline latency of the single-MAC design are also displayed by annotated input, output, and valid-output timing waveforms.

The power numbers displayed in

Table 10. CMOS synthesis methodology of the proposed MAC SPA FIR.

Design Architecture	Std-Cell Area (kGE)	Cell Area (mm2)	Timing (fmax)	Power (mW)	Energy/Output (pJ)
MAC-SPA 12 × 80 FIR (proposed)	5.2 kGE	0.035 mm2	350 MHz	38	0.11
ISPA-PM FIR [15]	19.8 kGE	0.134 mm2	280 MHz	120	0.35
Farrow SPA FIR [14]	41.5 kGE	0.282 mm2	230 MHz	260	0.78

were obtained using predicted synthesis results targeted at a 180 nm CMOS standard-cell technology under comparable operation conditions. The estimations were produced using gate-level synthesis and technology library characterization to evaluate switching activity and leakage components. The reported power includes both the dynamic power associated with logic switching and the static leakage power of the synthesized standard-cell implementation. All architectures were evaluated using the same operating frequency objective and technological assumptions to guarantee an equitable assessment of silicon area, timing performance, and power consumption.

The additional multiplexing and control logic in the single-MAC architecture are mostly responsible for the 9–13% speed drop. Scheduling logic introduces little delays, and multiplexers and accumulator feedback somewhat lengthen the critical path. However, the overall impact is small and tolerable considering the significant hardware savings.

5. Conclusions

A reconfiguration-focused SPA and ISPA filter suitable for SDR applications has been introduced in this paper by employing TDM-driven multi-channel MAC design, using the practice of resource optimization through sharing. The proposed filter enables seamless, real-time control of f_c across a wide range, built upon a single low-pass FIR filter prototype that ensures a linear phase response at every level of subfilter. No matter how many channels or taps there are, this article employs a separate MAC module. The presented reconfigurable filter has been implemented and synthesized using 0.18 µm CMOS technology. Additional testing was done on the Xilinx xc6vlx760-1ff1760 FPGA device. The results show that the proposed MAC-SPA and MAC-ISPA channel filters, synthesized on an FPGA, achieve a reduction in occupied slice count by approximately 7% and 4.76%, respectively. Although their operating speeds are slightly lower by about 9.4% for the MAC-SPA filter and 13.89% for the MAC-ISPA filter, this tradeoff is offset by significant savings in hardware resources, making both designs more area efficient with only a modest reduction in speed. The time-multiplexed MAC architecture increases computational latency, and comprehensive spectral re-characterization is not included in this study. Sequential MAC processing results in a tradeoff between latency and area because it uses multiplier sharing to reduce hardware resources while increasing latency per output sample when compared to parallel implementations.