Search Results (23)

Field-programmable gate arrays (FPGAs) are extensively utilized to accelerate virtualized network functions (VNFs) within cloud networks. Imposing rate limits on different flows can enhance the overall bandwidth utilization of the network. Existing hardware token bucket approaches fundamentally trade off resource efficiency against configuration granularity when supporting massive queues (>512). This paper proposes a novel rate-limiting method based on the token bucket algorithm and achieves efficient resource utilization through head packet scheduling and token-to-time conversion. The experimental results show that our method achieves 1.16% lookup-table (LUT) and 2.62% flip flop (FF) resource usage compared to state-of-the-art methods, while supporting 512 queues with <0.4% rate deviation across a 100 Kbps–10 Gbps range (5-decade dynamic range). Full article

Tiny machine learning (TinyML) demands the development of edge solutions that are both low-latency and power-efficient. To achieve these on System-on-Chip (SoC) FPGAs, co-design methodologies, such as hls4ml, have emerged aiming to speed up the design process. In this context, fast estimation of FPGA’s utilized resources is needed to rapidly assess the feasibility of a design. In this paper, we propose a resource estimator for fully customized (bespoke) multilayer perceptrons (MLPs) designed through the hls4ml workflow. Through the analysis of bespoke MLPs synthesized using Xilinx High-Level Synthesis (HLS) tools, we developed resource estimation models for the dense layers’ arithmetic modules and registers. These models consider the unique characteristics inherent to the bespoke nature of the MLPs. Our estimator was evaluated on six different architectures for synthetic and real benchmarks, which were designed using Xilinx Vitis HLS 2022.1 targeting the ZYNQ-7000 FPGAs. Our experimental analysis demonstrates that our estimator can accurately predict the required resources in terms of the utilized Look-Up Tables (LUTs), Flip-Flops (FFs), and Digital Signal Processing (DSP) units in less than 147 ms of single-threaded execution. Full article

In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A specific connection between these buffers allows cyclical charging and discharging of a parasitic capacitance associated with an external FPGA pin. If a few pins of an FPGA chip are not connected to any external components, they can be targeted to build the TRNG. The proposed TRNG requires only three external FPGA pins dedicated to capacitive oscillators, as well as 18 look-up tables (LUTs) and 20 flip-flops (FFs). Its throughput amounts to 11–13 Mbit/s. To pass all NIST SP800-22 statistical tests for a wide range of operating temperatures, the TRNG requires a post-processing circuit. The characteristic feature of the proposed TRNG is that it internally generates a signal indicating that a random bit was just produced. Therefore, no external clock signal is needed to sample the output. Full article

This paper proposes a unique configuration for an all-optical D Flip Flop (D-FF) utilizing a quasi-square ring resonator (RR) and T-Splitter, as well as NOT and OR logic gates within a 2-dimensional square lattice photonic crystal (PC) structure. The components realizing the all-optical D-FF comprise of optical waveguides in a 2D square lattice PC of 45 × 23 silicon (Si) rods in a silica (SiO₂) substrate. The utilization of these specific materials has facilitated the fabrication process of the design, diverging from alternative approaches that employ an air substrate, a method inherently unattainable in fabrication. The configuration underwent examination and simulation utilizing both plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methodologies. The simulation outcomes demonstrate that the designed waveguides and RR effectively execute the operational principles of the D-FF by guiding light as intended. The suggested configuration holds promise as a logic block within all-optical arithmetic logic units (ALUs) designed for digital computing optical circuits. The design underwent optimization for operation within the C-band spectrum, particularly at 1550 nm. The outcomes reveal a distinct differentiation between logic states ‘1’ and ‘0’, enhancing robust decision-making on the receiver side and minimizing logic errors in the photonic decision circuit. The D-FF displays a contrast ratio (CR) of 4.77 dB, a stabilization time of 0.66 psec, and a footprint of 21 μm × 12 μm. Full article

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented. Full article

The vortex-induced vibrations of two side-by-side flexible cylinders in a uniform flow were studied using a three-dimensional direct numerical simulation at Reynolds number Re = 350 with an aspect ratio of 100, and a center-to-center spacing ratio of 2.5. A mixture of standing-traveling wave pattern was induced in the in-line (IL) vibration, while the cross-flow (CF) vibration displayed a standing-wave characteristic. The ninth vibration mode prominently occurred in both IL and CF directions, along with competition between multiple modes. Proximity effects from the neighboring cylinder caused the primary frequency to be consistent between IL and CF vibrations for each cylinder, deviating from the IL to CF ratio of 2:1 in isolated cylinder conditions. Repulsive mean lift coefficients were observed in both stationary and vibrating conditions for the two cylinders due to asymmetrical vortex shedding in this small gap. Comparatively, lift and drag coefficients were notably increased in the vibrating condition, albeit with a lower vortex shedding frequency. Positive energy transfer was predominantly excited along the span via vortex shedding from the cylinder itself and the neighboring one, leading to increasing lower-mode vibration amplitudes. The flip-flopping (FF) wake pattern was excited in the stationary and vibrating cylinders, causing spanwise vortex dislocations and wake transition over time, with the FF pattern being more regular in the stationary cylinder case. Full article

Neurons are crucial components of neural networks, but implementing biologically accurate neuron models in hardware is challenging due to their nonlinearity and time variance. This paper introduces the SC-IZ neuron model, a low-cost digital implementation of the Izhikevich neuron model designed for large-scale neuromorphic systems using stochastic computing (SC). Simulation results show that SC-IZ can reproduce the behaviors of the original Izhikevich neuron. The model is synthesized and implemented on an FPGA. Comparative analysis shows improved hardware efficiency; reduced resource utilization, which is a 56.25% reduction in slices, 57.61% reduction in Look-Up Table (LUT) usage, and a 58.80% reduction in Flip-Flop (FF) utilization; and a higher operating frequency compared to state-of-the-art Izhikevich implementation. Full article

Due to the advantages of parallel architecture and low power consumption, a field-programmable gate array (FPGA) is typically utilized as the hardware for convolutional neural network (CNN) accelerators. However, SRAM-based FPGA devices are extremely susceptible to single-event upsets (SEUs) induced by space radiation. In this paper, a fault tolerance analysis and fault injection experiments are applied to a CNN accelerator, and the overall results show that SEUs occurring in a control unit (CTRL) lead to the highest system error rate, which is over 70%. After that, a hybrid hardening strategy consisting of a finite state machine error-correcting circuit (FSM-ECC) and a triple modular redundancy automatic hardening technique (TMR-AHT) is proposed in this paper to achieve a tradeoff between radiation reliability and design overhead. Moreover, the proposed methodology has very small workload and good migration ability. Finally, by full exploiting the fault tolerance property of CNNs, a highly reliable CNN accelerator with the proposed hybrid hardening strategy is implemented with Xilinx Zynq-7035. When BER is 2 × 10⁻⁶, the proposed hybrid hardening strategy reduces the whole system error rate by 78.95% with the overhead of an extra 20.7% of look-up tables (LUTs) and 20.9% of flip-flops (FFs). Full article

Flip-flop (FF) serves as a fundamental unit in various sequential logic circuits and complex digital electronic systems for generating, transforming, and temporarily storing digital signals. Nonvolatility plays a crucial role in FFs by ensuring instant data recovery after unexpected data loss. Nonvolatile flip-flop can quickly recover in a self-powered environment, making it suitable for application environments such as the Internet of Things (IOT). Unfortunately, most existing nonvolatile FFs (NVFFs) suffer from extended delays and high energy consumption during data backup and restore operations. In this paper, we propose two innovative voltage-controlled nonvolatile FFs (VC-FFs), namely VC-DFF (voltage-controlled D-FF) and VC-SRFF (voltage-controlled SR-FF), which address these challenges using voltage-controlled spin-orbit torque (VC-SOT) devices. The proposed designs are evaluated using a 40 nm CMOS process. Simulation results demonstrate that the proposed designs achieve significant improvements in write (recovery) energy consumption, with over 7.2× (1.54×) and 18.7× (2×) enhancements compared to their STT- and SOT-based counterparts, respectively. Full article

This paper reviews recent advancements in all-optical memory components, particularly focusing on various types of all-optical flip-flops (FFs) based on photonic crystal (PC) structures proposed in recent years. PCs, with their unique optical properties and engineered structures, including photonic bandgap control, enhanced light–matter interaction, and compact size, make them especially suitable for optical FFs. The study explores three key materials, silicon, chalcogenide glass, and gallium arsenide, known for their high refractive index contrast, compact size, hybrid integration capability, and easy fabrication processes. Furthermore, these materials exhibit excellent compatibility with different technologies like CMOS and fiber optics, enhancing their versatility in various applications. The structures proposed in the research leverage mechanisms such as waveguides, ring resonators, scattering rods, coupling rods, edge rods, switches, resonant cavities, and multi-mode interference. The paper delves into crucial properties and parameters of all-optical FFs, including response time, contrast ratio, and operating wavelength. Optical FFs possess significant advantages, such as high speed, low power consumption, and potential for integration, making them a promising technology for advancing optical computing and optical memory systems. Full article

Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations. In addition, a hardware implementation can provide the possibility of unifying the functionality with some secure primitive, for example, a true random number generator (TRNG) or a physical unclonable function (PUF). This paper presents a unified PUF-ChaCha20 in a field-programmable gate-array (FPGA) implementation. The problems and solutions of the PUF implementation are described, exploiting the metastability in latches. The Xilinx Artix-7 XC7A100TCSG324-1 FPGA implementation occupies 2416 look-up tables (LUTs) and 1026 flips-flops (FFs), reporting a 3.11% area overhead. The PUF exhibits values of 49.15%, 47.52%, and 99.25% for the average uniformity, uniqueness, and reliability, respectively. Finally, ChaCha20 reports a speed of 0.343 cycles per bit with the unified implementation. Full article

Transport Layer Security (TLS) provides a secure channel for end-to-end communications in computer networks. The ChaCha20–Poly1305 cipher suite is introduced in TLS 1.3, mitigating the sidechannel attacks in the cipher suites based on the Advanced Encryption Standard (AES). However, the few implementations cannot provide sufficient speed compared to other encryption standards with Authenticated Encryption with Associated Data (AEAD). This paper shows ChaCha20 and Poly1305 primitives. In addition, a compatible ChaCha20–Poly1305 AEAD with TLS 1.3 is implemented with a fault detector to reduce the problems in fragmented blocks. The AEAD implementation reaches 1.4-cycles-per-byte in a standalone core. Additionally, the system implementation presents 11.56-cycles-per-byte in an RISC-V environment using a TileLink bus. The implementation in Xilinx Virtex-7 XC7VX485T Field-Programmable Gate-Array (FPGA) denotes 10,808 Look-Up Tables (LUT) and 3731 Flip-Flops (FFs), represented in 23% and 48% of ChaCha20 and Poly1305, respectively. Finally, the hardware implementation of ChaCha20–Poly1305 AEAD demonstrates the viability of using a different option from the conventional cipher suite based on AES for TLS 1.3. Full article

Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node. Full article

In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%. Full article

To date, most studies focus on complex designs to realize offset cancelation characteristics in nonvolatile flip-flops (NV-FFs). However, complex designs using switches are ineffective for offset cancelation in the near/subthreshold voltage region because switches become critical contributors to the offset voltage. To address this problem, this paper proposes a novel cross-coupled NMOS-based sensing circuit (CCN-SC) capable of improving the restore yield, based on the concept that the simplest is the best, of an NV-FF operating in the near/subthreshold voltage region. Measurement results using a 65 nm test chip demonstrate that with the proposed CCN-SC, the restore yield is increased by more than 25 times at a supply voltage of 0.35 V, compared to that with a cross-coupled inverter-based SC, at the cost of 18× higher power consumption. Full article