Search Results (462)

Under weak-grid conditions, grid-following (GFL) control of doubly fed induction generators (DFIGs) suffers from reduced stability margins, deteriorated dynamic performance, and intensified oscillations near the stability boundary. To address these issues, a pre-synchronized switching strategy between GFL and grid-forming (GFM) modes, triggered by locally measured operating variables, is proposed. Based on the GFL control model, the evolution of system dynamics with decreasing short-circuit ratio is analyzed, thereby elucidating how reduced grid strength progressively weakens robustness and disturbance rejection and eventually leads to instability. To characterize this deterioration, a set of normalized indices is constructed to quantify the oscillation levels of active power, phase-locked loop frequency, and point of common coupling voltage, enabling reliable identification of control-performance deterioration. A pre-synchronization scheme based on a virtual power closed loop is then developed, allowing the target mode to converge to the current operating point prior to takeover and enabling smooth bidirectional switching between GFL and GFM modes. Hardware-in-the-loop results demonstrate that the proposed strategy accurately detects GFL performance deterioration and effectively suppresses boundary oscillations while mitigating switching transients, thereby enhancing the adaptability of DFIGs to variations in grid strength. Full article

As renewable energy is increasingly integrated via high-voltage direct current (HVDC) transmission, hybrid multi-infeed receiving-end grids containing both line-commutated converters (LCC) and modular multilevel converters (MMC) have become common, and wideband resonance problems in power-electronized networks are growing more prominent. This paper proposes an active resonance analysis and suppression strategy for such systems. First, a wideband current source converter model and a wideband voltage source converter model are adopted to describe the LCC and MMC, respectively, and a positive-sequence s-domain model of the system is established. A two-stage s-domain nodal admittance matrix method is then applied to efficiently determine the wideband resonance modes and the corresponding mode shape eigenvectors. A dual criterion combining the matching degree between resonance frequencies and LCC characteristic harmonics with the modal damping ratio identifies high-risk resonance modes. On this basis, an active damping strategy that realizes a parallel virtual resistance on the AC side through MMC supplementary control is proposed, together with a quantitative design method for the virtual conductance. At the control implementation level, a modulation wave reconstruction bypass injection scheme superimposes the high-frequency damping command directly in the $\alpha \beta$ stationary reference frame, thereby bypassing the PI controller and reducing the amplitude attenuation and phase distortion caused by the high-frequency limitation of the integral path. PSCAD/EMTDC simulation results on an IEEE 9-bus test system demonstrate that the proposed strategy effectively suppresses resonance amplification and wideband power oscillations excited by LCC characteristic harmonics without affecting the fundamental power transmission. Full article

Wireless power transfer (WPT) systems for electric vehicles (EVs) are increasingly being studied in the MHz range to increase power density and reduce the size of passive components. However, operation at higher frequencies significantly changes electromagnetic interference (EMI) behaavior. Fast switching in SiC- and GaN-based inverters, high-Q resonant operation, and frequency-dependent parasitic capacitances create conductive, capacitive, and magnetic interference mechanisms that are less significant in conventional kHz-range systems. Although many existing studies focus on power-transfer efficiency and converter optimization, EMI mechanisms in MHz-range EV WPT systems remain insufficiently systematized from a system-level electromagnetic perspective. This paper presents a state-of-the-art review of EMI generation mechanisms and system-level effects in high-frequency WPT systems for electric vehicles. The review considers the main interference sources and coupling paths, including switching-induced common-mode currents, resonant amplification of current and voltage stress, capacitive coupling between the coupler and nearby conductive structures, and magnetic-field redistribution caused by coil misalignment. Special attention is given to the transition from lumped-element assumptions to more distributed electromagnetic behavior at higher frequencies. The review also discusses the possible impact of these mechanisms on vehicle electronic subsystems and highlights the need for frequency-aware electromagnetic design, integrated modeling, and more rigorous EMC assessment for reliable MHz-range wireless EV charging systems. Full article

This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this study demonstrates that, when combined with self-cascode structures, BD architectures achieve competitive intrinsic gain, enhanced input common-mode range, and improved slew rate efficiency under nanoampere bias conditions. To support these claims, closed-form analytical derivations, dynamic analysis, and comprehensive Monte Carlo and PVT simulations are provided to quantify robustness and mismatch sensitivity. The results establish a systematic framework for evaluating BD versus GD architectures under identical technology and power constraints, offering practical design guidelines and optimized self-cascoded topologies for next-generation energy-autonomous systems. Full article

Decoupled maximum power point tracking control and output voltage control can be accomplished simultaneously using dual-duty cycle control. However, developed triple switch triple mode (TSTM) exhibits absence of the common ground between the solar panel and output load therefore causing the leakage current to flow which creates safety concern especially for household electrification. In addition to having a negative effect on the solar panel, leakage current increases power losses. Thus, this work proposes a unique TSTM dc-dc converter. The suggested converter has the following advantages: (1) The presence of a common ground between the output load and the solar panel eliminates the leakage current. (2) Reduced electromagnetic interference issues present due to leakage current. (3) Enhanced voltage gain over wider duty cycle. (4) Enables simultaneous decoupled control of MPPT and output voltage. (5) Absence of voltage oscillation across the switches. The proposed TSTM converter is an unique combination of switched inductor and switched capacitor. Both inductor and capacitors are connected in order to boost the level of voltage at the output terminal. The operating principle, design equations and device stress are analyzed in detail for the proposed TSTM. The comparison over existing converter in terms of voltage gain and switch stresses are highlighted in details. Lastly, a laboratory prototype (40/400 V) for 400 W is created and thoroughly tested in order to validate mathematical calculations. Full article

This paper presents a 7-bit 1.6 GS/s hybrid capacitive-to-charge-injection DAC (C-CIDAC)-based flash-assisted time-interleaved (FATI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that improves the limited input range and temperature-induced gain variation in conventional CIDAC-based SAR ADCs. In the proposed architecture, a DAC voltage common-mode (V_CM) shift up to 48 LSBs is internally generated during the coarse conversion, enabling a rail-to-rail ADC input range while improving V_CM independence. In addition, a fully on-chip background gain-calibration scheme is introduced to compensate for the gain error between the CDAC and CIDAC caused by temperature variation. By taking advantage of the pulse-activation-based CIDAC operation scheme, the proposed calibration achieves robust gain tracking without any external bias control. The proposed four-channel FATI-SAR ADC was designed using a 65 nm CMOS process and occupies 13,628 μm², including the background calibration circuitry. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.60/−0.60 LSB and +0.72/−0.76 LSB at −40 °C and 105 °C, respectively. At Nyquist input, the simulated SNDR and SFDR are 41.52 dB and 53.36 dB, respectively. The ADC consumes 8.551 mW and achieves an FoM_W of 54.6 fJ/conversion step. Comprehensive post-layout simulation results show that the proposed FATI-SAR ADC operates at 1.6 GS/s and maintains an ENOB above 6.3 across a temperature range from −40 °C to 105 °C at Nyquist input. Full article

This paper introduces an electrocardiogram (ECG) noise removal front-end amplifier circuit based on a current-feedback operational amplifier (CFOA) that uses the current feedback to detect error signals and control the output. This ECG circuit focuses on denoising the ECG noise to accentuate the ECG electrical signals from the heart. Noises in ECG refer to baseline wander (BW), powerline interference (PLI) and motion artifacts. We proposed a CFOA-based ECG pre-amplifier using the AD844 commercial operational amplifier built inside with a positive second-generation current conveyor (CCII+) and a voltage follower circuit. This work introduces an ECG noise removal front-end amplifier based on a CFOA. The primary innovation lies in the balancing instrumentation amplifier architecture that utilizes the high-speed and robust properties of the AD844 commercial operational amplifier to achieve superior noise rejection. To protect against high-frequency interference, we introduce a novel cascaded low-pass filter (LPF) stage that ensures a sharper cut-off compared to traditional single-stage designs. Experimental results validate the design’s effectiveness, achieving a high common-mode rejection ratio (CMRR) of 75.4 dB and a mid-band gain of 46.5 dB. These performance metrics, combined with the circuit’s ability to eliminate BW and PLI, confirm its robust suitability for high-fidelity wearable ECG monitoring. Full article

Grid-forming (GFM) converters enhance power system stability by emulating synchronous generators, but their limited overcurrent capability under grid faults poses a critical challenge to transient stability. Existing current-limiting methods often force a trade-off between fault current suppression and voltage support. To address this, a direct internal voltage control (DIVC)-based fault current-limiting strategy is proposed. The DIVC framework eliminates inner control loops and directly regulates the internal voltage amplitude and phase by leveraging measurements at the point of common coupling (PCC) and the converter output, enabling fast, accurate current control within a virtual synchronous generator (VSG) architecture. Under mild faults, the strategy prioritizes maintaining the terminal voltage to preserve voltage source behavior; under severe faults, it smoothly transitions to a current-limiting mode that preserves the terminal voltage phase angle to support transient synchronization. The scheme incorporates compensation-enabling criteria, dual-mode amplitude/phase compensation, and power reference modification. Experimental results under an 80% voltage sag demonstrate that the proposed method limits the transient current peak to 1.1 p.u. and ensures oscillation-free recovery within 0.1 s, significantly outperforming conventional current saturation and virtual impedance techniques. The proposed approach also exhibits strong current-limiting capability under unbalanced faults. Full article

Accurate non-invasive voltage measurement is critical for the stable operation of ultra-high-voltage direct-current (UHVDC) grids. In practical converter valve environments, voltage inversion based on the charge simulation method (CSM) may be affected by nearby charged conductors. To address this problem, this paper proposes a non-invasive voltage measurement method combining radially aligned near-conductor two-sensor differential electric-field measurement with three-dimensional electrostatic finite-element modelling. The differential electric field between two radial sensing positions is used for voltage inversion, which suppresses distant common-mode interference. When a nearby interference conductor exists, a weighted differential correction coefficient k is introduced to compensate for the residual radial interference component. Theoretical and simulation results show that k is a scenario-dependent coefficient affected by the measured voltage, sensor spacing, interference voltage, and geometric configuration. In an ultra-high-voltage (UHV) converter valve bridge-arm scenario with a 400 kV interference conductor, the absolute voltage inversion error is reduced from 0.50–1.57% FS before correction to below 0.20% FS after correction. Experiments on a 30 kV-scaled platform further verify the method under different measured voltages, sensor spacings, and interference-voltage levels, with the best-tested case reducing the maximum error from 0.93% FS to 0.16% FS. Full article

Direct Torque Control (DTC) for induction motors (IMs) is an advanced method derived from Field-Oriented Control (FOC). In DTC, a voltage source inverter (VSI) is employed to directly regulate the stator flux linkage and electromagnetic torque through space vector modulation (VSM), where the optimal switching vector is selected for the VSI. Similarly to FOC, the stator flux and electromagnetic torque are independently controlled to deliver enhanced dynamic performance. However, DTC still suffers from certain drawbacks, such as slow transient response, limited dynamic performance, and high ripples in torque and flux. In this paper, an improved DTC method is proposed for a three-phase squirrel-cage induction motor. Specifically, a Type-2 fuzzy logic controller is employed to regulate both the stator flux and electromagnetic torque (T2FLC). The proposed method (FLCDTC) combines a three-level VSI with dual-band hysteresis (DBHW) switching to generate the gating signals for the insulated gate bipolar transistors (IGBTs). This approach effectively reduces the total harmonic distortion (THD) in torque and stator current, lowers the common-mode voltage (CMV), and enhances the overall motor performance. Simulation results under random noise distribution demonstrate the robustness of the proposed controller, even at low operating speeds. Finally, the effectiveness of the algorithm is validated in real-time through hardware-in-the-loop (HIL) implementation. Full article

This paper proposes a digital potentiometer-based adaptive gas sensor interface for stable detection without signal saturation under extreme environmental fluctuations. Conventional fixed-gain circuits often suffer from limited dynamic range, leading to data loss when severe baseline drifts exceed ADC input limits. To address this, we developed a real-time control algorithm that actively adjusts attenuator and amplifier gains, maintaining the ADC input voltage (V_ADC) near the common-mode voltage (V_CM). Experimental results demonstrate that the interface remains stable even when the buffer voltage reaches 2.75 V, significantly surpassing the 1.2 V ADC limit. Sensor resistance data, reconstructed by inversely calculating updated circuit parameters, achieved high accuracy with a Mean Absolute Percentage Error (MAPE) of 1.628% and a maximum relative error under 4.8%. Consequently, this study proves that logically extending the physically limited ADC dynamic range enables high-precision gas sensing in diverse environments without requiring high-performance computing devices. This approach provides a cost-effective and robust solution for compact IoT-based gas monitoring systems. Full article

In high-frequency 400 V/48 V matrix planar LLC resonant converters for data center power supplies, enlarged interwinding parasitic capacitance can induce significant transformer-related common-mode (CM) displacement currents. However, the effects of secondary-side rectifier commutation and local winding position on the resulting CM spikes have not been sufficiently clarified. This paper establishes a unified analytical expression for the transformer-related CM current in a converter with a half-bridge primary and a full-bridge synchronous-rectifier (SR) secondary. The analysis shows that asynchronous SR commutation shifts the secondary reference potential and introduces additional excitation through the interwinding parasitic capacitances, thereby producing double-pulse CM current spikes. The unequal spike amplitudes among different secondary-side rectifier units are further explained by the combined effects of local winding position and distributed parasitic coupling. Based on these findings, a shielding-layer scheme was then proposed and verified on a 400 V/48 V, 300 kHz, 3 kW prototype. The experimental results show average reductions of about 15 dB over 150 kHz–800 kHz and 20 dB over 800 kHz–6.5 MHz in the CM voltage spectrum, whereas the prototype achieves a peak efficiency of 97.78%. Full article

In the open-winding motor fed by a common DC bus, unbalanced inverter common-mode voltage (CMV), zero-sequence components of the permanent magnet flux linkage, and the PWM dead-time effect can induce a zero-sequence current (ZSC) through the inherent current path. For an open-winding five-phase permanent magnet synchronous motor (OW-FPPMSM) applied in an aerospace rocket starter-generator system, two ZSC suppression strategies based on zero-sequence voltage (ZSV) generation mechanisms are proposed in this paper, which improve motor performance in a simple and efficient manner. In the first strategy, the conventional method is modified to enable asynchronous operation of the two inverters, thereby generating the required ZSV pulses. The switching order and time offset between the two inverters are determined by the reference ZSV. The second strategy employs basic voltage vectors with larger magnitudes, resulting in higher DC bus voltage utilization. By adjusting the switching sequence of the second inverter, the ZSC components at the carrier frequency are eliminated. Both strategies also achieve the injection of the third-harmonic current. Finally, the two strategies are further analyzed in terms of the modulation index and ZSV modulation range. Simulation and experimental results verify the effectiveness of the ZSC suppression strategies. Full article

The cascaded H-bridge static synchronous compensator (STATCOM) has been widely employed in medium- and high-voltage reactive power compensation applications due to its high modularity, fast response speed, and direct grid connection capability. However, the DC-link voltage exhibits an inherent double-frequency ripple, which poses a serious challenge to power quality. Therefore, numerous Active Power Decoupling (APD) techniques have been proposed. However, existing schemes still exhibit certain limitations: independent APD topologies are associated with higher costs, whereas single bridge-arm multiplexed APD topologies are confronted with issues such as elevated DC-side voltage and increased current stress on the multiplexed arm. Consequently, comprehensive optimization is difficult to achieve in terms of the number of power devices, decoupling accuracy, level of capacitor multiplexing, and device stress. To address the above issues, this paper proposes a DC split capacitor (DC-SC)-based dual bridge-arm multiplexed cascaded H-bridge STATCOM with active power decoupling capability, along with its corresponding control method. By constructing a fundamental-frequency common-mode voltage on the decoupling capacitor, this method effectively suppresses the double-frequency ripple in the DC-side voltage and reduces the current stress on the switching devices. The simulation and experimental results have verified the correctness and effectiveness of the proposed topological structure and control method. Full article

This work introduces a trimming technique based on eTrim technology to minimize both the input-referred offset voltage and its temperature drift in the operational amplifiers. The proposed low-voltage op-amp utilizes the body effect to maintain a constant bandwidth across the rail-to-rail input common-mode range under low supply voltages. During input common-mode transitions, the current in the folded cascode stage remains stable, ensuring a robust output stage. Furthermore, a specialized gain-boosting structure enhances the low-frequency gain while preventing occasional latch-up during low-voltage power-up. A pin-multiplexing scheme is employed for trimming data input, thereby eliminating the need for dedicated trimming pins and mitigating post-package parameter variations. At room temperature, a constant-current injection mechanism reduces the DC offset to microvolt levels. At high temperature, temperature-compensated current injection cancels the first-order drift component. Implemented in a low-voltage operational amplifier, post-layout simulation results demonstrate that with a 100-pF capacitive load, the amplifier achieves a gain–bandwidth product exceeding 10 MHz, a low-frequency gain greater than 140 dB, and an input-referred noise of 2.54 µVp-p for the P-channel input and 3.95 µVp-p for the N-channel input. The trimming process reduces the residual offset to the microvolt range and effectively suppresses offset drift, ensuring accurate offset compensation across the specified temperature range. Full article