A Precision Operational Amplifier with eTrim-Based Offset Calibration and Two-Point Temperature Drift Trim

Abstract

This work introduces a trimming technique based on eTrim technology to minimize both the input-referred offset voltage and its temperature drift in the operational amplifiers. The proposed low-voltage op-amp utilizes the body effect to maintain a constant bandwidth across the rail-to-rail input common-mode range under low supply voltages. During input common-mode transitions, the current in the folded cascode stage remains stable, ensuring a robust output stage. Furthermore, a specialized gain-boosting structure enhances the low-frequency gain while preventing occasional latch-up during low-voltage power-up. A pin-multiplexing scheme is employed for trimming data input, thereby eliminating the need for dedicated trimming pins and mitigating post-package parameter variations. At room temperature, a constant-current injection mechanism reduces the DC offset to microvolt levels. At high temperature, temperature-compensated current injection cancels the first-order drift component. Implemented in a low-voltage operational amplifier, post-layout simulation results demonstrate that with a 100-pF capacitive load, the amplifier achieves a gain–bandwidth product exceeding 10 MHz, a low-frequency gain greater than 140 dB, and an input-referred noise of 2.54 µVp-p for the P-channel input and 3.95 µVp-p for the N-channel input. The trimming process reduces the residual offset to the microvolt range and effectively suppresses offset drift, ensuring accurate offset compensation across the specified temperature range.

1. Introduction

Precision operational amplifiers are essential components in various high-accuracy applications, including bioelectronics [1,2,3,4,5], memory circuits [6,7], and MEMS systems [8,9]. Their widespread adoption stems from their inherently low offset voltage and minimal temperature drift. Nevertheless, in practical implementations, the input offset voltage is often degraded by device mismatches and package-induced mechanical stress. Additionally, temperature fluctuations during normal operation further contribute to offset drift [10]. These non-ideal effects collectively limit the suitability of conventional operational amplifiers for high-precision applications. Consequently, extensive research has been dedicated to offset voltage compensation techniques. These methods can be categorized into two primary approaches: dynamic offset cancellation (DOC) and trimming [11,12].

Dynamic offset cancellation techniques, such as auto-zeroing [13,14,15] and chopper stabilization [12,16,17], are capable of reducing the offset voltage to the microvolt level. A key advantage of these approaches is their ability to perform real-time calibration during normal circuit operation. However, they are not without limitations. The switching activities inherent in DOC circuits introduce charge injection and clock feedthrough, which generate additional noise components and may cause spikes in the input bias current [18]. Furthermore, chopper-stabilized amplifiers often exhibit residual output ripple. This ripple cannot be adequately suppressed by simple low-pass filtering without compromising the signal bandwidth. As a result, dedicated ripple suppression feedback loops are typically required, which increase both the power consumption and the overall complexity of the system [19,20].

A review of several trimming techniques reveals distinct advantages and limitations for precision amplifier design. Common approaches include fuse trimming, laser trimming [21], floating-gate trimming [22], and memristor-based trimming [23,24]. The primary limitation of laser trimming lies in its susceptibility to post-packaging parameter drift, which degrades the long-term accuracy after device assembly. Meanwhile, both floating-gate and memristor-based methods require additional non-standard process steps, rendering them incompatible with mainstream BCD technology platforms. Given these considerations, fuse trimming is therefore adopted for this design owing to its full compatibility with the BCD process. This choice ensures that the proposed trimming scheme can be readily integrated into a wide range of industrial applications without requiring process modifications.

For operational amplifiers employing MOS input stages, the offset voltage is often in the millivolt range [25], which severely limits their application in high-precision scenarios. One approach employs single-temperature trimming to compensate for both the offset and its drift by distinguishing the individual contributions from load resistors and transistors and compensating them separately [26]. However, identifying these contributions relies on chopper techniques, which introduce additional design complexity and significant area overhead. To address this limitation, advanced techniques such as on-chip heater-based self-trimming have been developed [27]. These methods employ a two-temperature trimming procedure to simultaneously minimize both the absolute offset and its temperature coefficient. However, this benefit comes at the cost of additional pin requirements for inputting trimming signals, thereby increasing system complexity and overall manufacturing cost.

To address the aforementioned limitations, this paper presents a trimming scheme implemented using eTrim technology. A key feature of the proposed approach is its capability to perform post-package trimming, thereby compensating for parameter shifts induced by packaging stress. To achieve this without increasing the pin count, the design employs a pin multiplexing technique for trimming data input, which eliminates the need for dedicated trimming pins. The trimming procedure itself consists of two distinct phases. First, at room temperature, a constant-current injection mechanism is applied to nullify the amplifier’s input-referred offset voltage. Second, at an elevated temperature, a temperature-dependent current injection technique is employed to cancel the first-order temperature coefficient of the offset. By combining these two trimming steps, the proposed scheme achieves a low residual offset across the entire operating temperature range, resulting in significant suppression of offset voltage drift.

The remainder of this paper is structured as follows. Section 2 provides an analysis of device mismatch characteristics and their impact on operational amplifier offset. Section 3 describes the proposed low-voltage, low-noise operational amplifier, including its architectural design and circuit implementation. Section 4 presents the post-layout simulation results, accompanied by a discussion of trimming effectiveness and performance analysis. Finally, Section 5 concludes the paper.

2. Device-Level and Chip-Level Mismatch

2.1. Mismatch of CMOS Device

The mismatch in drain current for a MOS transistor pair, as depicted in Figure 1a, is predominantly governed by the mismatches in threshold voltage ($\Delta V_{TH}$) and current factor ($\Delta \beta$), where $\beta =\mathrm{\mu }{C}_{OX}W/L$. The relationship for drain current mismatch of the MOS transistor pair shown in Figure 1a can be expressed as [26]:

$${\displaystyle \frac{\Delta I_D}{I_D}}={\displaystyle \frac{gm}{I_D}}·\Delta V_{TH}+{\displaystyle \frac{\Delta \beta }{\beta }}$$

(1)

where $gm$ is the effective transconductance. In applications demanding high current matching precision, a lower drain current mismatch can be achieved by biasing the transistors in strong inversion to minimize $gm/I_D$.

The offset voltage of the MOS input stage shown in Figure 1b, assuming identical load resistors, can then be expressed as [26]:

$$V_{OS}=\Delta V_{TH}+{\displaystyle \frac{I_D}{gm}}·{\displaystyle \frac{\Delta \beta }{\beta }}$$

(2)

This implies that for applications requiring low input-referred offset voltages, MOS input pairs should be biased in weak inversion to maximize $gm/I_D$, thereby minimizing the contribution of the current-factor mismatch.

The standard deviation of the threshold voltage may be approximated by:

$${\sigma }_{VTH}^2={\displaystyle \frac{A_{VTH}^2}{WL}}+S_{VTH}^2·D^2$$

(3)

where $A_{VTH}$ and $S_{VTH}$ are process- related constants, and D denotes the inter- transistor distance. This leads to the conclusion that the standard deviation of $\Delta V_{TH}$ exhibits an inverse dependence on $\sqrt{area}$ and a linear dependence on D.

Instead of increasing the transistor size to improve offset behaviour, it can be considered to add extra circuitry for offset trimming or dynamic offset compensation [28].

2.2. Mismatch of Operational Amplifier

When employing a trimming network to adjust an operational amplifier’s offset voltage, it is essential to ensure that the trimming range fully covers the expected spread of the offset. The proposed low-voltage, low-noise operational amplifier designed in this work is shown in Figure 2. Its first stage is a rail-to-rail input folded cascode amplifier, and the second stage is a feedback-biased class-AB output stage [29]. To reduce both the offset voltage range and the input-referred noise, a source-degeneration resistor is introduced in the folded cascode stage.

Assuming the resistors are ideal, the mismatch voltage of the operational amplifier is given by the following expression:

$$\begin{array}{c}\hfill V_{OS\_RTI}\approx \Delta V_{OS\_IN}+{\displaystyle \frac{g{m}_N}{g{m}_{IN}}}·\Delta V_{OS\_N}+{\displaystyle \frac{g{m}_P}{g{m}_{IN}}}·\Delta V_{OS\_P}+\\ \hfill {\displaystyle \frac{I_D}{g{m}_{IN}}}·({\displaystyle \frac{\Delta {\beta }_{in}}{{\beta }_{in}}}+{\displaystyle \frac{\Delta {\beta }_N}{{\beta }_N}}+{\displaystyle \frac{\Delta {\beta }_P}{{\beta }_P}})\end{array}$$

(4)

where $\Delta V_{OS\_IN}$ is the offset voltage of the input pair, $g{m}_{IN}$ is the transconductance of the input pair, $\Delta V_{OS\_N}$ is the offset voltage of the N-load transistors, $g{m}_N$ is the transconductance of the N-load transistors, $\Delta V_{OS\_P}$ is the offset voltage of the P-load transistors, and $g{m}_P$ is the transconductance of the P-load transistors. $\Delta$$\beta$ represents the current factor mismatch of the corresponding devices. Figure 3 shows the distribution of the operational amplifier’s input offset voltage without any suppression method. It can be seen from the figure that the input offset voltage of the operational amplifier is on the order of millivolts, making it difficult to perform precision signal processing tasks.

To effectively reduce the offset voltage, the transconductance of the current-source transistors M12–M13, and that of the current-mirror pair M22–M23 should be minimized, which implies these devices should be biased in strong inversion. For optimum offset performance, the input-stage transistors should exhibit a high transconductance while their aspect-ratio mismatch should be as small as possible; consequently, the input pair M1–M2 and M2–M4 is designed to operate in weak inversion.

The trimming range is determined by the selected current injection points and the magnitude of the current. For instance, injecting at nodes $P\_Vos\_Add\_A$ and $P\_Vos\_Add\_B$ yields a range given by Equations (5) and (6).

$$VtrimRangeA={\displaystyle \frac{g{m}_{in}}{I_{TRIM}}}$$

(5)

$$VtrimRangeB={\displaystyle \frac{g{m}_{LOAD}·Rs·I_{TRIM}}{g{m}_{IN}·(1+g{m}_{LOAD}·Rs)}}$$

(6)

In above expression, $I_{TRIM}$ denotes the trimming current, and Rs represents the source- degeneration resistor.

3. Topology and Circuit Design

The proposed low-voltage, low-noise precision operational amplifier featuring eTrim-based offset calibration is shown in Figure 4. The circuit comprises three blocks: the amplifier core, the eTrim module, and the current-steering DAC module. The eTrim module comprises the Control Signal module, the Trim Control module, and the Fuse Array module. The Control Signal module works with the peripheral circuitry and test signals to generate the Clk and Trim signals. The Trim Control module then counts the Clk pulses and, in conjunction with a decoder, performs fuse addressing, outputting the final Trim signal and the Pretrim signal. The Fuse Array module determines whether to blow the fuses based on the output signals from the Trim Control module. The current-steering DAC module then performs the actual trimming, adjusting both the operational amplifier’s offset voltage and its temperature drift. Based on the control word from the Fuse Array module, the current distribution within the current-steering DAC module is altered, thereby modulating the amplifier’s offset voltage. In conjunction with the proposed two-temperature trimming scheme, this enables the simultaneous trimming of both the offset voltage and its temperature drift.

3.1. Operational Amplifier Design Considerations

(1) At low supply voltage, grounding the bulk of the NMOS input pair introduces a dead zone in the low input common-mode range, which reduces the tail current Ib1 of the PMOS input pair; once the input common-mode voltage drops below the NMOS threshold voltage, the NMOS input pair turns off, forcing Ib2 into the linear region, which lowers the total input transconductance $(g{m}_{IN\_P}+g{m}_{IN\_N})$ and degrades the op amp’s gain–bandwidth product, a key factor affecting the op amp’s performance in low-voltage scenarios. To overcome this issue, the Substrate Bias Circuit uses isolated transistors for the NMOS input pair M3 and M4, with their bulk terminals connected to the emitter of Q1, and the MOS body effect is utilized to lower the threshold voltage, which prevents transconductance drop during common mode transitions at low supply voltage and maintains a stable gain–bandwidth product for the op amp. The threshold voltage variation with VSB is expressed as:

$$V_{THN}=V_{THN0}+\gamma (\sqrt{V_{SB}+2·\left|V_{fp}\right|}-2·\sqrt{|V_{fp}|})$$

(7)

where $V_{THN}$ is the threshold voltage of the MOS transistor, $V_{THN0}$ is the zero bias threshold voltage, $V_{fp}$ is the substrate Fermi potential, $V_{SB}$ is the source to bulk voltage, and $\gamma$ is the body effect factor.

As can be seen from the results in Figure 5a, under low-voltage supply, the effect brought by the substrate bias circuit is significant when the common-mode voltage varies.

(2) Employing a translinear loop to bias the output power transistors provides a simple and efficient control scheme, but it imposes a minimum supply voltage constraint. With the continuous advancement of wearable devices driving down the required chip supply voltage, the headroom demanded by the translinear loop limits its application scope. To enable operation down to 1.7 V, this work utilizes a feedback-biased Class-AB biasing circuit for the output stage. The translinear loop structure employs two diode-connected MOS transistors to bias the output devices, resulting in a minimum supply voltage greater than $2V_{gs}+V_{ds}$. In contrast, the feedback-biased topology only requires a minimum supply voltage of $V_{gs}+2V_{ds}$, which significantly reduces the supply voltage requirement. Compared to [29], the proposed design incorporates second-stage cascode transistors M8, M9, and M10. Under high supply voltage conditions, these devices reduce the drain-source voltage of M14, M15, M16, and M21, thereby minimizing their substrate leakage current. Furthermore, they enforce voltage equality between nodes A and B and between nodes C and D, which helps reduce the systematic offset voltage.

Additional current-mirror transistors M30 and M31 are included to mitigate channel-length modulation effects, ensuring that M32 accurately samples the output stage current and enabling precise control of the output quiescent current. Another current mirror, formed by M24, M25, and M26, is added. Under quiescent conditions, M25 and M26 operate in the deep linear region, leaving the minimum-current selection circuit unaffected. When the output stage sinks or sources large currents, this mirror limits the current through M6, restricts the voltage difference between VbiasA and VbiasB, and reduces the overload recovery time.

(3) In the feedback-biased Class AB circuit, the input differential pair is formed by M15, M16, and M17, while the output load consists of M19, M20, and M21. To ensure stable loop bandwidth and avoid abrupt changes in loop stability during input common mode transitions, a Common Source Stage Biasing Circuit (shown in Figure 2) is employed. In this circuit, auxiliary amplifier enforces equality between the voltages at nodes E and F. By precisely matching transistors M7 and M14, the current in the folded cascode branch is well defined. Consequently, the quiescent current remains constant during input common mode switching, thereby stabilizing the loop bandwidth of the output stage. It can be observed that the corresponding effect is illustrated in Figure 5b.

(4) A startup anomaly in the bias circuit can cause the gain boost amplifier to output an erroneous voltage, which prevents the chip from functioning correctly. To address this problem, the cascode transistor is split into M19 and M20. The gate of M19 is tied to a fixed bias (Vb2), while the gate of M20 is connected to the output of the gain boost amplifier. If the output latches during power up, current flows through the M19 branch, lowering the voltage at the inverting input of the gain boost amplifier and forcing its output to a normal operating level.

This method trades off a portion of the loop gain for two key benefits. First, it prevents output stage latch-up caused by an abnormal gain boost output node under low supply voltage conditions. Second, it reduces the loop feedback factor, thereby enhancing loop stability (see the derivation in Figure 6b).

The output impedance of a conventional gain boost stage is given by $A·(g{m}_a+g{m}_b)·(R_A\left|\right|R_B)·R_C$. After splitting the cascode transistor, the expression can be written as follows: Combining the above equations yields:

$$V_X=I_T·R_C$$

(8)

$$V_T=V_X+(I_T+g{m}_a·V_X+g{m}_a·A·V_X)·R_A\left|\right|R_B$$

(9)

The output impedance is reduced by a factor of $g{m}_a/(g{m}_a+g{m}_b)$. Figure 6c illustrates the impact of the conventional gain-boosted circuit and the proposed gain-boosted circuit with cascode transistor splitting on the low-frequency gain of the amplifier. It can be observed that the low-frequency gain is reduced by approximately 10 dB.

(5) Model the circuit (see Figure 7) to evaluate noise magnitude. Taking the P_input differential pair as an example, without IDAC, equivalent input noise voltage is:

$$\begin{array}{cc}\hfill \overline{V_{n,IN}^2}& ={\displaystyle \frac{8kT}{3·g_{m1,2}}}+{\displaystyle \frac{k}{C_{OX}·{\left(WL\right)}_{1,2}·f}}+{\displaystyle \frac{8kT·g_{m3,4,\mathrm{eff}1}}{3·g_{m1,2}^2}}\hfill \\ \hfill & +{\displaystyle \frac{k}{C_{OX}·{\left(WL\right)}_{3,4}·f}}·{\displaystyle \frac{g_{m3,4,\mathrm{eff}}^2}{g_{m1,2}^2}}+{\displaystyle \frac{4kT}{R_{3,4}}}·{\displaystyle \frac{g_{m3,4,\mathrm{eff}}}{g_{m1,2}^2}}\hfill \end{array}$$

(10)

where $g_{m3,4,\mathrm{eff}1}={\displaystyle \frac{g_{m3,4}}{1+g_{m3,4}·R_{3,4}}}$. After adding the IDAC, the equivalent input noise voltage becomes:

$$\begin{array}{cc}\hfill \overline{V_{n,IN}^2}& ={\displaystyle \frac{8kT}{3·g_{m1,2}}}+{\displaystyle \frac{k}{C_{OX}·{\left(WL\right)}_{1,2}·f}}+{\displaystyle \frac{8kT·g_{m3,4,\mathrm{eff}}}{3·g_{m1,2}^2}}\hfill \\ \hfill & +{\displaystyle \frac{k}{C_{OX}·{\left(WL\right)}_{3,4}·f}}·{\displaystyle \frac{g_{m3,4,\mathrm{eff}2}^2}{g_{m1,2}^2}}+{\displaystyle \frac{4kT}{R_{3,4,\mathrm{eff}}}}·{\displaystyle \frac{g_{m3,4,\mathrm{eff}}}{g_{m1,2}^2}}\hfill \\ \hfill & +{\displaystyle \frac{8kT·g_{mA,B}}{3·g_{m1,2}^2}}+{\displaystyle \frac{k}{C_{OX}·{\left(WL\right)}_{A,B}·f}}·{\displaystyle \frac{g_{mA,B}^2}{g_{m1,2}^2}}\hfill \end{array}$$

(11)

where $g_{m3,4,\mathrm{eff}2}={\displaystyle \frac{g_{m3,4}}{1+g_{m3,4}·R_{3,4,\mathrm{eff}}}}$ and $R_{3,4,\mathrm{eff}}=R_{3,4}\Vert R_{1,2}$. In comparison (10), IDAC1 reduces the input noise voltage contributed by resistors R3 and R4, while IDAC2 increases the input noise voltage. However, since $g_{mA,B}$ are much smaller than gm_1,2, their noise contribution can be neglected.

To reduce the overall input noise voltage of the op amp, M1 and M2 should operate in the subthreshold region to achieve a large gm/Id, while M3 and M4 should operate in the saturation region to achieve a small gm/Id ratio. While ensuring sufficient VDS headroom for M3 and M4, adjust R3 and R4 to reduce the equivalent input noise contributed by M3 and M4.

As shown in Figure 8a,b, under the P-input common-mode range, the integrated noise peak-to-peak value in the range of 0.1 10 Hz is $2.54\mathrm{\mu }{\mathrm{V}}_{\mathrm{p}\text{-}\mathrm{p}}$, and the spectral density at $1\mathrm{kHz}$ is $7.8\mathrm{nV}/\sqrt{\mathrm{Hz}}$. Under the N-input common-mode range, the integrated noise peak-to-peak value in the range of 0.1–10 Hz is $3.95\mathrm{\mu }{\mathrm{V}}_{\mathrm{p}\text{-}\mathrm{p}}$, and the noise spectral density at $1\mathrm{kHz}$ is $9.28\mathrm{nV}/\sqrt{\mathrm{Hz}}$.

3.2. eTrim Technology and Trim Scheme

3.2.1. eTrim Technology

By utilizing pin multiplexing, the eTrim module enables the input of control signals without adding extra trimming pins, which helps minimize system cost. The eTrim module comprises three sub-blocks: the Control Signal module, the Trim Control module, and the Fuse Array module. The Control Signal module works with the chip’s peripheral circuitry to generate the control signals Clk and Trim.

The Control Signal module, as shown in Figure 9, operates as follows during testing: current is sunk into or sourced from the $V_{OUT}$ node. This alters the current in the output transistors M1 and M11. Transistors M2 and M12 then proportionally mirror these output currents. Each mirrored current is compared against a fixed reference current. The result of this comparison is then shaped by a two-stage driver to generate the required control signals. A hysteresis response is incorporated into the circuit to prevent false triggering.

The trimming logic (see Figure 10) operates with CLK and TRIM as inputs, defining one cycle as the interval between two consecutive rising edges of CLK. The period from a CLK rising edge to the subsequent TRIM rising edge is designated as the pre-trim phase. During this interval, the system evaluates the effect that blowing the currently addressed fuse would have on the circuit’s output, allowing a decision to be made before any physical blowing occurs. To skip the addressed fuse without blowing it, two consecutive CLK rising edges are issued. When TRIM is held high, the system enters the trimming phase, during which the selected fuse is physically blown. The interval from a TRIM falling edge to the next CLK rising edge serves as idle time, allowing the operational amplifier’s output to settle before proceeding to the next fuse in the trimming sequence.

3.2.2. Trimming Scheme

This work implements a dual injection scheme for accurate offset compensation, integrating constant current injection with temperature-compensated current injection [30]. The constant current path targets the static DC offset at room temperature. It corrects the inherent offset from process variations and device mismatch by injecting a constant current into a specific bias node, trimming it to the microvolt level.

To address the first-order temperature coefficient, a temperature-compensated current injection method is employed alongside trimming logic. This approach dynamically modulates the injection current based on real-time thermal sensing, directly opposing the linear drift. The trimming logic orchestrates the parameters, ensuring seamless cooperation between the constant and temperature-dependent injection paths for precise, full temperature range offset correction.

In contrast to single temperature trimming, the two point temperature trimming scheme significantly reduces offset voltage drift, yielding superior acquisition accuracy. The key advantage of the proposed scheme is that it decouples the high temperature trim from the room-temperature trim, guaranteeing that the former does not interfere with the latter. This allows for generating a customized trimming code on a per-chip basis, ensuring high trimming precision. An additional advantage is that trimming at both temperatures simply involves correcting the offset to be within 1 LSB, thereby eliminating the need for complex computational overhead.

Figure 11 illustrates the overall trimming flow. After power-up, the eTrim module is initially disabled to measure the baseline power consumption, which determines the required power consumption trimming direction. Following this, the high-temperature trimming current is characterized at room temperature. Using pin multiplexing, this current is directed into the amplifier’s input pins INP and INN. In combination with a general purpose op-amp test circuit, the current is converted into an equivalent input-bias trimming current. The first step is to trim this current to a value below 20 nA. Next, at room temperature, the trimming voltage for the P-input path and the offset voltage for the N-input path are calibrated. Finally, at high temperature, a final trimming is performed on the offset voltages of both the P-input and N-input paths.

Figure 12 illustrates the generation of the required temperature-compensated current, which is precisely zero at room temperature. It operates as follows: transistors MN1 and MN2 form a current-comparing stage. When IPTAT < ICTAT, the comparator outputs a high level, turning MN3 ON and MP4 OFF. In this state, the current through MP1 becomes IMP1 = IPTAT − ICTAT. This difference current is then mirrored to produce the final trimming current ITRIM.

Conversely, when IPTAT > ICTAT, the comparator output goes low. This turns MN3 OFF and MP4 ON. The current difference ICTAT − IPTAT, then flows through MP4 into the current mirror branch, ultimately generating the trimming current ITRIM. Thus, the current ITRIM can be expressed by the following equation:

$$ITRIM=|IPTAT-ICTAT|$$

(12)

Due to process variations and device mismatches, the current ITRIM exhibits a non-zero residual at room temperature. This non-ideality would cause the subsequent high-temperature trimming operation to interfere with the result of the room-temperature trim, thereby degrading the overall trimming accuracy.

To address this issue, the IPTAT current is trimmed. Using pin multiplexing, the ITRIM current is mirrored by MN5 to generate IB−, which is connected to the op-amp’s INP pin. Simultaneously, it is mirrored by MP3 to generate IB+, connected to the INN pin. In conjunction with the trimming logic, the ITRIM current is trimmed first, before offset and drift compensation. By measuring the IB+ and IB− currents at room temperature, the temperature zone of ITRIM’s zero-crossing point can be determined. This identifies the required trimming direction and magnitude to bring ITRIM close to zero at room temperature. The specific decision method is outlined in

Table 1. ITRIM Trim Scheme.

IB−	IB+	State of IPTAT
<20 nA	∼	No Trim
>20 nA	>20 nA	Decrease
>20 nA	0 nA	Increase

.

4. Simulation Results

The circuit was implemented in a CSMC 0.15 μm 1P3M BCD process. The chip layout is shown in Figure 13, with a total area of 680 μm × 700 μm. The input stage of the amplifier was carefully matched to minimize mismatch, and it was placed at the center of the die to reduce the impact of dicing stress.

The post-layout DC and AC parameters of the operational amplifier are summarized in the following table (

Table 2. Simulation results of DC&AC parameters.

Parameter	LVCM Value	HVCM Value	Unit
DC Gain	>140	>140	dB
Phase Margin	52	56	°
Gain Margin	12	10	dB
IQ	1.38	1.3	mA
$V_{\mathrm{OS}\_\mathrm{RTI}}$ (Trimed)	<10	<10	μV
Input Voltage Noise	2.54	3.95	μVpp
GBW	11	10	MHz

).

A schematic of the test circuit is shown in Figure 14. An auxiliary operational amplifier forms a feedback loop, with resistors R1, R2, and R6 setting the gain. Resistors R3 and R4, together with switches S1 and S2, are used to measure IB+ and IB−. ITEST is an external current source that sinks or sources current into/from the device under test (DUT). In conjunction with the circuit, this enables the generation of the internal trimming signals Clk and Trim.

Based on the configuration in Figure 14, trimming signals are applied. The transient simulation results are shown in Figure 15. In the first four cycles, the system is initialized, and power consumption is trimmed. In the subsequent four cycles, the ITRIM current is measured and adjusted to approximately 0 μA at room temperature. Following this, the offset voltage and its temperature drift are trimmed. The trimming range for the P-path is 1.9 mV with a 1 LSB step of 2 μV, while the N-path has a range of 2.6 mV with a 1 LSB step of 2.6 μV.

To verify the feasibility of the proposed dual-temperature trimming scheme, an artificial offset voltage with second–order curvature was introduced into the operational amplifier, as shown in the left panel of Figure 16. The initial state exhibited a significant initial offset of $V_{OS}=1\mathrm{mV}$ and a temperature coefficient of $V_{OS\_TC}=3.5\mathrm{\mu }\mathrm{V}/°\mathrm{C}$, which represents typical non-ideal characteristics of untrimmed precision op-amps. Following the trimming sequence in Figure 15, the calibration was implemented in two stages: room-temperature trimming was first performed to eliminate the DC offset component, followed by high-temperature trimming to compensate for the first–order temperature drift of the offset voltage. The trimming results, presented in the right panels of Figure 16, clearly demonstrate the effectiveness of the proposed method. After room-temperature trimming (top-right), the residual offset voltage was reduced to $\Delta V_{OS}<10\mathrm{\mu }\mathrm{V}$, while the dual-temperature trimming (bottom-right) further suppressed the offset to $\Delta V_{OS}<10\mathrm{\mu }\mathrm{V}$ at room temperature and reduced the temperature coefficient to $V_{OS\_TC}<0.2\mathrm{\mu }\mathrm{V}/°\mathrm{C}$.

Table 3. Performance summary and comparison to prior art.

Parameters	This Work	[26]	[24]	[27]	[31]	[32]	[33]
Supply Voltage (V)	$1.7\sim 5.5$	5	1.8	1.8	$2.7\sim 5.5$	$1.7\sim 5.5$	$\sim 36$
External Pin for Trimming	N	N	Y	Y	N	N	N
DC Gain (dB)	>140	>120	85	unknown	>100	>100	>100
Phase Margin (°)	52	unknown	57	unknown	65	45	unknown
IQ for LVCM (mA)	1.38	1.1	0.122	0.89	1	1.22	1.8
Input Offset (μV)	<10	<45	<5.8	<57.8	<20	<10	<120
CMRR (dB)	120	120	110	79	100	120	140
PSRR (dB)	102	110	100	67	95	90	140
Settling Time 0.1% (μs)	0.42	unknown	unknown	unknown	<1	0.75	unknown
Slew Rate (V/μs)	17	unknown	5.6	unknown	5	4.5	20
Input Voltage Noise (0.1∼10 Hz, μVpp)	2.54	unknown	unknown	4	2.3	2	0.25
Input Voltage Noise Density (LVCM, 1 kHz, nV/$\sqrt{\mathrm{Hz}}$)	7.8	9.1	unknown	6.9	8	6.5	5.1
Chip Area (mm2)	0.476	1.43	unknown	0.14	unknown	unknown	2.1

compares the key parameters of this work with those in previous studies.

Table 4. Comprehensive Comparison of Trimming Technologies (Offset Voltage, Temperature Drift, Process & Cost).

Category/Parameter	eTrim (Proposed)	Laser Trimming	External Potentiometer	Chopper Stabilization
—Performance (Offset & Temperature Drift)—
Input Offset Voltage ($V_{OS}$), max (μV)	10	50+	50+	<1
Temperature Drift ($d{V}_{OS}/dT$) (μV/°C)	0.2	2.0	>5.0	<0.1
Full-Temperature Stability	Excellent	Poor	Poor	Excellent
Packaging Stress Compensation	Supported	Not Supported	Not Supported	Supported
—Process & Cost—
Calibration Timing	Post-Packaging	Wafer-Level	System-Level	Real-Time
Chip Area Overhead	Moderate	Low	None	Moderate
Reliability (Long-Term Drift)	High	Moderate	Low	High
Re-calibration Capability	One-Time (OTP)	None	Reusable	Real-Time

comprehensively compares the proposed eTrim trimming scheme with laser trimming, external potentiometer trimming, and chopper stabilization. In terms of offset voltage and temperature drift, the eTrim scheme achieves a maximum offset voltage of 10 μV and a temperature drift of 0.2 μV/°C, featuring excellent full-temperature stability and packaging stress compensation capability. From the perspective of process and cost, the post-packaging calibration scheme of eTrim has low mass production cost and is compatible with plastic packaging processes. It has advantages over laser trimming and is comparable to chopper stabilization in terms of reliability and recalibration flexibility. Despite these advantages, eTrim has inherent limitations in trimming accuracy and temperature drift compensation: first, eTrim relies on one-time programmable (OTP) fuse arrays to realize step-by-step adjustment with a typical resolution of 2 μV/step, which introduces quantization errors and makes it difficult to achieve high-precision trimming. Second, although eTrim can effectively suppress first-order temperature drift, it cannot compensate for second-order temperature drift under extreme temperature conditions, and the one-time calibration feature cannot adapt to dynamic drifts caused by device aging, limiting its application in high-reliability scenarios.

5. Conclusions

This paper addresses the core technical challenges of conventional precision operational amplifiers under low supply voltages, including large input offset voltage, significant temperature drift, and unstable bandwidth with varying common-mode voltages, by designing a precision operational amplifier integrated with an electrical trimming (eTrim) offset calibration scheme. The proposed amplifier is well-suited for low-voltage, high-precision applications such as bioelectronics, MEMS sensing, and portable precision measurement systems. Adopting a rail-to-rail input folded cascode architecture, the amplifier innovatively incorporates a substrate bias circuit that leverages the MOS body effect to dynamically adjust the threshold voltage of NMOS input transistors. This fundamentally eliminates transconductance degradation in the input stage during common-mode voltage transitions, ensuring a stable gain–bandwidth product across the full input common-mode range at a minimum supply voltage of 1.7 V. Aiming at the low-voltage latch-up issue of the gain-boosting architecture, a cascode transistor splitting technique is proposed, which not only suppresses output anomalies of the gain-boosting amplifier during low-voltage power-up but also optimizes loop stability by reducing the loop feedback factor. Through a reasonable trade-off of a small amount of low-frequency gain, the circuit robustness is significantly improved. For the output stage, a feedback-biased Class-AB circuit with additional cascode transistors and current mirror modules is employed, which effectively reduces substrate leakage current, lowers systematic offset voltage, and shortens overload recovery time, thus ensuring efficient and stable operation of the amplifier under low-voltage conditions.

To address the issues of low offset compensation accuracy, inadequate temperature drift suppression, and elevated system complexity induced by dedicated trimming pins in conventional trimming techniques, this paper proposes a dual-temperature (room and high temperature) offset trimming scheme based on eTrim technology with input and output pin multiplexing. This scheme integrates precise DC offset calibration through constant current injection at room temperature and active cancellation of first-order temperature drift via temperature-compensated current injection at high temperature, achieving complete decoupling of the high-temperature and room-temperature trimming processes. This eliminates mutual interference between the two processes at the design level and significantly enhances calibration accuracy over the full temperature range. Furthermore, by reusing the input and output pins as trimming data input ports, dedicated trimming pins are eliminated, which reduces the hardware complexity and manufacturing cost of the system while effectively compensating for post-packaging parameter drift caused by packaging stress. The current-steering DAC unit and fuse array in the eTrim module enable precise modulation of the trimming current, calibrating the input-referred offset voltage to below 10 μV at room temperature and limiting the offset temperature coefficient to less than 0.2 μV/°C. Compared with traditional single-temperature trimming schemes, the proposed approach achieves substantial improvements in drift suppression performance. In comparison with state-of-the-art precision operational amplifiers adopting trimming schemes, the proposed design exhibits a wide supply voltage range of $1.7\sim 5.5$ V, no dedicated trimming pins, and a lower calibrated offset voltage, along with excellent common-mode rejection ratio (120 dB) and power supply rejection ratio (102 dB). Therefore, it offers significant competitive advantages in integration, low-voltage adaptability, and calibration accuracy.

The core value of this research is to provide a highly integrated, low-cost, and industrialization-compatible precision operational amplifier solution for low-voltage, high-precision electronic systems. The proposed pin multiplexed eTrim scheme and dual-temperature trimming method can be directly integrated into mainstream BCD process flows without additional non-standard process steps, balancing design innovation and industrial production feasibility to facilitate mass manufacturing. Moreover, the innovative topologies designed in this work (e.g., the substrate bias circuit and cascode-split gain-boosting structure) provide reusable design concepts and technical references for the development of low-voltage, high-stability analog integrated circuits. These topologies can also be extended to the design optimization of similar analog circuits, demonstrating strong engineering application value. Future research directions of this work can be expanded in three aspects: First, the existing trimming scheme will be deeply integrated with digital calibration algorithms to realize adaptive real-time trimming of the offset voltage. This will further suppress second-order temperature drift and improve calibration accuracy under extreme temperature conditions, meeting the requirements of high-end precision applications such as aerospace systems. Second, low-power bias circuits and dynamic current adjustment technologies will be adopted to optimize the power consumption of the amplifier, enabling it to adapt to ultra-low-power Internet of Things (IoT) terminal applications and further expanding its application scenarios. Third, the eTrim-based calibration architecture will be extended to other analog and mixed-signal circuits (e.g., current references, analog-to-digital converters, and instrumentation amplifiers), broadening its application scope in integrated circuit systems. In addition, fabricating the chip and conducting experimental testing and characterization of the prototype will be key follow-up work in order to verify the actual performance of the design and provide experimental data for its industrial application.

In summary, the precision operational amplifier with eTrim-based offset calibration designed in this paper achieves collaborative optimization from both circuit topology and trimming scheme perspectives, effectively addressing the core technical challenges of conventional precision operational amplifiers in low-voltage scenarios. The proposed innovative design scheme not only enhances the low-voltage adaptability, calibration accuracy, and operational stability of precision operational amplifiers but also provides new insights for the low-voltage and high-stability design of high-precision analog integrated circuits, possessing important theoretical reference value and broad practical application prospects.