Search Results (34)

For high-voltage signal detection applications, an auto-zero and chopper operational amplifier (OPA) is proposed in this paper. With the auto-zero and chopper technique, the OPA adopts an eight-channel Ping-Pong mechanism to reduce the high-frequency ripple and glitch generated by chopper modulation. The main transconductor effectively suppresses low-frequency noise and offset by combining input coarse and output fine auto-zero. A common-mode voltage tracking circuit is presented to ensure constant gate-source and gate-substrate voltages of the chopper, which reduces the charge injection caused by threshold voltage drift of their transistors and improves output signal resolution. The OPA is implemented using CMOS 180 nm BCD process. The post-simulation results show that the unit gain bandwidth (UGB) is 2.5 MHz and common-mode rejection ratio (CMRR) is 137 dB when the power supply voltage is 5–55 V. The noise power spectral density (PSD) is 6.6 nV/√Hz, and the offset is about 47 µV. The overall circuit consumes current of 960 µA. Full article

Fully differential amplifier circuits are well suited for instrumentation front ends and signal-conditioning applications. They offer high common-mode rejection ratios (CMRRs) regardless of the passive component tolerances but remain sensitive to imbalances in active devices. By using power supply bootstrapping (PSB), the CMRRs of these circuits can be improved, where they become independent of mismatches in both passive and active components. This technique works by forcing the power supply nodes to follow the common-mode input voltage, which significantly enhances the CMRR. However, this approach introduces stability issues that must be addressed through dedicated compensation strategies without degrading the overall performance. In this work, the theoretical background, a design methodology, and experimental validation are presented. The proposed technique was applied to a fully differential amplifier built with general purpose operational amplifiers. Prior to the PSB, the amplifier exhibited a CMRR of 90 dB at 1 kHz. A straightforward application of PSB led to instability in the common-mode behavior; however, with the proposed compensation method, the amplifier achieved stable operation and an improved CMRR of 130 dB. Full article

Electroencephalography (EEG) remains an essential method for monitoring brain activity, but the limitations of conventional systems due to the complexity of installation and lack of portability have led to the introduction and development of in-ear EEG technology. In-ear EEG is an emerging method of recording electrical activity in the brain and is an innovative concept that offers multiple advantages both from the point of view of the device itself, which is easily portable, and from the user’s point of view, who is more comfortable with it, even in long-term use. One of the fundamental components of this type of device is the electrodes used to capture the EEG signal. This innovative method allows bioelectrical signals to be captured through electrodes integrated into an earpiece, offering significant advantages in terms of comfort, portability, and accessibility. Recent studies have demonstrated that in-ear EEG can record signals qualitatively comparable to scalp EEG, with an optimized signal-to-noise ratio and improved electrode stability. Furthermore, this review provides a comparative synthesis of performance parameters such as signal-to-noise ratio (SNR), common-mode rejection ratio (CMRR), signal amplitude, and comfort, highlighting the strengths and limitations of in-ear EEG systems relative to conventional scalp EEG. This study also introduces a visual model outlining the stages of technological development for in-ear EEG, from initial research to clinical and commercial deployment. Particular attention is given to current innovations in electrode materials and design strategies aimed at balancing biocompatibility, signal fidelity, and anatomical adaptability. This article analyzes the evolution of EEG in the ear, briefly presents the comparative aspects of EEG—EEG in the ear from the perspective of the electrodes used, highlighting the advantages and challenges of using this new technology. It also discusses aspects related to the electrodes used in EEG in the ear: types of electrodes used in EEG in the ear, improvement of contact impedance, and adaptability to the anatomical variability of the ear canal. A comparative analysis of electrode performance in terms of signal quality, long-term stability, and compatibility with use in daily life was also performed. The integration of intra-auricular EEG in wearable devices opens new perspectives for clinical applications, including sleep monitoring, epilepsy diagnosis, and brain–computer interfaces. This study highlights the challenges and prospects in the development of in-ear EEG electrodes, with a focus on integration into wearable devices and the use of biocompatible materials to improve durability and enhance user comfort. Despite its considerable potential, the widespread deployment of in-ear EEG faces challenges such as anatomical variability of the ear canal, optimization of ergonomics, and reduction in motion artifacts. Future research aims to improve device design for long-term monitoring, integrate advanced signal processing algorithms, and explore applications in neurorehabilitation and early diagnosis of neurodegenerative diseases. Full article

As integrated electronic microsystems advance, their internal components demonstrate increasing miniaturization, higher-density integration, and, consequently, significantly enhanced performance. This paper presents an on-chip transformer balun. The balun has a combination of planar coupled inductors and filtering capacitors using integrated passive device (IPD) technology, giving it the advantages of a more compact circuit size and lower cost to achieve single-ended to differential function on glass substrates. Moreover, it can be integrated in systems by flip-chip. The die has a size of 1.81 mm × 1.36 mm with a −15 dB single-ended return loss bandwidth of 2.07 GHz to 4.30 GHz. Within this bandwidth, the maximum insertion loss is 2.56 dB, and the amplitude imbalance is less than 2.04 dB. The phase difference between the differential signals is 180 ± 14.02° and the common mode rejection ratio (CMRR) is above 19.08 dB. The balun has the potential of miniaturization for integration on package or through-glass interposers (TGIs). Full article

This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm² on the chip, with a power consumption of 8.96 μW. Full article

Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Z_in) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Z_in of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm² CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µV_rms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials. Full article

Muscles play an indispensable role in human life. Surface electromyography (sEMG), as a non-invasive method, is crucial for monitoring muscle status. It is characterized by its real-time, portable nature and is extensively utilized in sports and rehabilitation sciences. This study proposed a wireless acquisition system based on multi-channel sEMG for objective monitoring of grip force. The system consists of an sEMG acquisition module containing four-channel discrete terminals and a host computer receiver module, using Bluetooth wireless transmission. The system is portable, wearable, low-cost, and easy to operate. Leveraging the system, an experiment for grip force prediction was designed, employing the bald eagle search (BES) algorithm to enhance the Random Forest (RF) algorithm. This approach established a grip force prediction model based on dual-channel sEMG signals. As tested, the performance of acquisition terminal proceeded as follows: the gain was up to 1125 times, and the common mode rejection ratio (CMRR) remained high in the sEMG signal band range (96.94 dB (100 Hz), 84.12 dB (500 Hz)), while the performance of the grip force prediction algorithm had an R² of 0.9215, an MAE of 1.0637, and an MSE of 1.7479. The proposed system demonstrates excellent performance in real-time signal acquisition and grip force prediction, proving to be an effective muscle status monitoring tool for rehabilitation, training, disease condition surveillance and scientific fitness applications. Full article

Amplification of wideband high-frequency and microwave signals is a fundamental element within every high-frequency circuit and device. Ultra-wideband (UWB) sensor applications use circuits designed for their specific application. The article presents the analysis, design, and implementation of ultra-wideband differential amplifiers for M-sequence-based UWB applications. The designed differential amplifiers are based on the Cherry–Hooper structure and are implemented in a low-cost 0.35 µm SiGe BiCMOS semiconductor process. The article presents an analysis and realization of several designs focused on different modifications of the Cherry–Hooper amplifier structure. The proposed amplifier modifications are focused on achieving the best result in one main parameter’s performance. Amplifier designs modified by capacitive peaking to achieve the largest bandwidth, amplifiers with the lowest possible noise figure, and designs focused on achieving the highest common mode rejection ratio (CMRR) are described. The layout of the differential amplifiers was created and the chip was manufactured and wire-bonded to the QFN package. For evaluation purposes, a high-frequency PCB board was designed. Schematic simulations, post-layout simulations, and measurements of the individual parameters of the designed amplifiers were performed. The designed and fabricated ultra-wideband differential amplifiers have the following parameters: a supply current of 100–160 mA at −3.3 V or 3.3 V, bandwidth from 6 to 12 GHz, gain (at 1 GHz) from 12 to 16 dB, noise figure from 7 to 13 dB, and a common mode rejection ratio of up to 70 dB. Full article

Wearable devices have been widely used for the home monitoring of physical activities and healthcare conditions, among which ambulatory electrocardiogram (ECG) stands out for the diagnostic cardiovascular information it contains. Continuous and unobtrusive sensing often requires the integration of wearable sensors to existing devices such as watches, armband, headphones, etc.; nonetheless, it is difficult to detect high-quality ECG due to the nature of low signal amplitude at these areas. In this paper, a high-performance system with multi-channel signal superposition for weak ECG real-time detection is proposed. Firstly, theoretical analysis and simulation is performed to demonstrate the effectiveness of this system design. The detection system, including electrode array, acquisition board, and the application (APP), is then developed and the electrical characteristics are measured. A common mode rejection ratio (CMRR) of up to 100 dB and input inferred voltage noise below 1 μV are realized. Finally, the technique is implemented in form of ear-worn and armband devices, achieving an SNR over 20 dB. Results are also compared with the simultaneous recording of standard lead I ECG. The correlation between the heart rates derived from experimental and standard signals is higher than 0.99, showing the feasibility of the proposed technique. Full article

This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm². The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mV_pp output. The amplifier can provide a noise level of 1.18 μV_rms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μV_rms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13. Full article

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth. Full article

Objective: We designed and validated a wireless, low-cost, easy-to-use, mobile, dry-electrode headset for scalp electroencephalography (EEG) recordings for closed-loop brain–computer (BCI) interface and internet-of-things (IoT) applications. Approach: The EEG-based BCI headset was designed from commercial off-the-shelf (COTS) components using a multi-pronged approach that balanced interoperability, cost, portability, usability, form factor, reliability, and closed-loop operation. Main Results: The adjustable headset was designed to accommodate 90% of the population. A patent-pending self-positioning dry electrode bracket allowed for vertical self-positioning while parting the user’s hair to ensure contact of the electrode with the scalp. In the current prototype, five EEG electrodes were incorporated in the electrode bracket spanning the sensorimotor cortices bilaterally, and three skin sensors were included to measure eye movement and blinks. An inertial measurement unit (IMU) provides monitoring of head movements. The EEG amplifier operates with 24-bit resolution up to 500 Hz sampling frequency and can communicate with other devices using 802.11 b/g/n WiFi. It has high signal–to–noise ratio (SNR) and common–mode rejection ratio (CMRR) (121 dB and 110 dB, respectively) and low input noise. In closed-loop BCI mode, the system can operate at 40 Hz, including real-time adaptive noise cancellation and 512 MB of processor memory. It supports LabVIEW as a backend coding language and JavaScript (JS), Cascading Style Sheets (CSS), and HyperText Markup Language (HTML) as front-end coding languages and includes training and optimization of support vector machine (SVM) neural classifiers. Extensive bench testing supports the technical specifications and human-subject pilot testing of a closed-loop BCI application to support upper-limb rehabilitation and provides proof-of-concept validation for the device’s use at both the clinic and at home. Significance: The usability, interoperability, portability, reliability, and programmability of the proposed wireless closed-loop BCI system provides a low-cost solution for BCI and neurorehabilitation research and IoT applications. Full article

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm². With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µV_rms, a closed-loop gain (A_V) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results. Full article

The study of wearable systems based on surface electromyography (sEMG) signals has attracted widespread attention and plays an important role in human–computer interaction, physiological state monitoring, and other fields. Traditional sEMG signal acquisition systems are primarily targeted at body parts that are not in line with daily wearing habits, such as the arms, legs, and face. In addition, some systems rely on wired connections, which impacts their flexibility and user-friendliness. This paper presents a novel wrist-worn system with four sEMG acquisition channels and a high common-mode rejection ratio (CMRR) greater than 120 dB. The circuit has an overall gain of 2492 V/V and a bandwidth of 15~500 Hz. It is fabricated using flexible circuit technologies and is encapsulated in a soft skin-friendly silicone gel. The system acquires sEMG signals at a sampling rate of over 2000 Hz with a 16-bit resolution and transmits data to a smart device via low-power Bluetooth. Muscle fatigue detection and four-class gesture recognition experiments (accuracy greater than 95%) were conducted to validate its practicality. The system has potential applications in natural and intuitive human–computer interaction and physiological state monitoring. Full article

In general, structures with rotational joints and linearized dynamic equations are used to facilitate the control of manipulator robots. However, in some cases, the workspace is limited, which reduces the accuracy and performance of this type of robot, especially when uncertainties are considered. To counter this problem, this work presents a redundant planar manipulator robot with Six-Degree-of-Freedom (6-DoF), which has an innovative structural configuration that includes rotary and prismatic joints. Three control strategies are designed for the monitoring and regulation of the joint trajectory tracking problem of this robot under the action of variable loads. Two advanced control strategies—predictive and Fuzzy-Logic Control (FLC)—were simulated and compared with the classical Proportional–Integral–Derivative (PID) controller. The graphic simulator was implemented using tools from the MATLAB/Simulink software to model the behavior of the redundant planar manipulator in a virtual environment before its physical construction, in order to conduct performance tests for its controllers and to anticipate possible damages/faults in the system mechanics before the implementation of control strategies in a real robot. The inverse dynamics were obtained through the Lagrange–Euler (L-E) formulation. According to the property of symmetry, this model was obtained in a simplified way based on the main diagonal of the inertia matrix of the robot. Additionally, the model includes the dynamics of the actuators and the estimation of the friction forces, both with central symmetry present in the joints. The effectiveness of these three control strategies was validated through qualitative comparisons—performance graphs of trajectory tracking—and quantitative comparisons—the Common Mode Rejection Ratio (CMRR) performance indicator and joint error indexes such as the Residual Mean Square (RMS), Residual Standard Deviation (RSD), and Index of Agreement (IA). In this regard, FLC based on the dynamic model was the most-suitable control strategy. Full article