Search Results (23)

This paper presents a class-D outphasing power amplifier (PA) that incorporates a non-isolating balun combiner employing a 180° phase shift. Both isolating and non-isolating outphasing combiners are analyzed for signal restoration and combining efficiency. The proposed non-isolating balun combiner employing the 180° phase shift was experimentally evaluated and compared with a commercial isolating Wilkinson combiner. When two constant-envelope signals derived from a 10 MHz long-term evolution (LTE) signal are applied to the inputs of the outphasing combiners, both combiners demonstrate successful signal reconstruction. The measured adjacent channel leakage ratios (ACLRs) are −47 dBc for the Wilkinson combiner and −46 dBc for the proposed balun combiner. At 6 dB power back-off (PBO), the proposed balun combiner achieves a combining efficiency of 85.1%, representing an improvement of nearly 60% over the Wilkinson combiner. With a center frequency of 650 MHz, targeting 5G FR1 applications, a class-D outphasing PA was designed in a 28 nm CMOS process using the measured S-parameter data from both outphasing combiners. Simulation results show that the class-D outphasing PA incorporating the proposed balun combiner achieves a peak drain efficiency (DE) of 82.9% with an output power of 17.7 dBm. At 6 dB PBO, the DE reaches 61%, which is approximately 37% higher than that of the outphasing PA using the Wilkinson combiner. Moreover, the designed outphasing PA supports broadband operation over the 360–860 MHz range. Full article

This paper extends the quasi-load insensitive (QLI) Class-E Doherty power amplifier (PA) design methodology to address Doherty PA combiners with complex load impedance trajectories. Additionally, the QLI operation is analyzed for generalized class-E output matching networks with input series inductors and finite DC-feed inductors. We demonstrate that the QLI class-E Doherty operation can be achieved for various Doherty combiners by selecting the appropriate combination of class-E outputs matching network resonance factors and input series inductances. Moreover, a modified class-E output network is proposed to overcome the frequency limitation that might be caused by the class-E network resonance factor choice. To validate the proposed methodology, two 40 W Doherty PAs are designed and simulated using commercial GaN HEMT transistors achieving more than 70% efficiency over a 6 dB output power back-off at 3.8 GHz. Full article

This paper presents an X-band high-power GaN MMIC power amplifier (PA). To balance efficiency, output power, and saturated power flatness, the load-line theory is employed to analyze and validate the power variation trends within an extended continuous Class B/J (CCBJ) impedance space. Theoretical constant power contours are plotted within this space. An L-C impedance matching network is used to match the amplifier’s output impedance to the overlapping region of the 0.5 dB constant power contour and the CCBJ impedance space, significantly improving the in-band power flatness of the PA based on the CCBJ design approach. Additionally, an RC parallel structure is integrated into the interstage matching network to maximize gain while ensuring stability. The proposed PA, implemented using a 0.25 µm commercial GaN process, achieves a saturated output power of 47–47.6 dBm with in-band fluctuations within ± 0.3 dB, a power gain of 27.0–27.8 dB, and an efficiency of 40–45.5% across the X-band. Full article

A method of electro-thermal co-optimization design for the Gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) power amplifier (PA) is introduced in this paper. Due to the self-heating effect of the GaN high electron mobility transistor (HEMT), it is necessary to pay attention to the influence of thermal resistance change on circuit performance when designing a high-power RF PA. For this purpose, a three-dimensional finite element analysis model of GaN multi-gate HEMT is developed. The thermal resistance and junction temperature of the device under a RF dynamic current are extracted by heat transfer simulation and can be substituted into the temperature node of the transistor model for PA circuit simulation design. To verify the proposed method, a Class AB MMIC PA was designed and tested using a 0.15-μm GaN-on-SiC process. Through the application of the above methods, the designed PA performance is optimized and achieves the performance of over 60% power-added efficiency (PAE) and 38 dBm saturation power (Psat) within a compact area of 1.6 mm × 2.2 mm. It is demonstrated that the proposed method can effectively improve the consistency of simulation results and measurement results, which can be a valuable reference for high-power MMIC PA design. Full article

Short-range Internet of Things (IoT) sensor nodes operating at 2.4 GHz must provide ubiquitous wireless sensor networks (WSNs) with energy-efficient, wide-range output power (POUT). They must also be fully integrated on a single chip for wireless body area networks (WBANs) and wireless personal area networks (WPANs) using low-power Bluetooth (BLE) and Zigbee standards. The proposed fully integrated transmitter (TX) utilizes a digitally controllable current-mode class-D (CMCD) power amplifier (PA) with a second harmonic distortion (HD2) suppression to reduce VCO pulling in an integrated system while meeting harmonic limit regulations. The CMCD PA is divided into 7-bit slices that can be reconfigured between differential and single-ended topologies. Duty cycle distortion compensation is performed for HD2 suppression, and an HD2 rejection filter and a modified C-L-C low-pass filter (LPF) reduce HD2 further. Implemented in a 28 nm CMOS process, the TX achieves a wide P_OUT range of from 12.1 to −31 dBm and provides a maximum efficiency of 39.8% while consuming 41.1 mW at 12.1 dBm P_OUT. The calibrated HD2 level is −82.2 dBc at 9.93 dBm P_OUT, resulting in a transmitter figure of merit (TX_FoM) of −97.52 dB. Higher-order harmonic levels remain below −41.2 dBm even at 12.1 dBm P_OUT, meeting regulatory requirements. Full article

The proliferation of radar technology has given rise to a growing demand for advanced, high-performance transmitter front-ends operating in the 24 GHz frequency band. This paper presents a design analysis of a radio frequency (RF) transmitter (TX) front-end operated at a 24 GHz frequency and designed using 65 nm complementary metal-oxide-semiconductor (CMOS) technology for radar applications. The proposed TX front-end design includes the integration of an up-conversion mixer and power amplifier (PA). The up-conversion mixer is a Gilbert cell-based design that translates the 2.4 GHz intermediate frequency (IF) signal and 21.6 GHz local oscillator (LO) signal to the 24 GHz RF output signal. The mixer is designed with a novel technique that includes a duplex transconductance path (D_TP) for enhancing the mixer’s linearity. The D_TP of the mixer includes a primary transconductance path (P_TP) and a secondary transconductance path (S_TP). The P_TP incorporates a common source (CS) amplifier, while the S_TP incorporates an improved cross-quad transconductor (I_CQT). The integrated PA in the TX front-end is a class AB tunable two-stage PA that can be tuned with the help of varactors as a synchronous mode to increase the PA bandwidth or stagger mode to obtain a high gain. The PA is tuned to 24 GHz as a synchronous mode PA for the TX front-end operation. The proposed TX front-end showed an excellent output power of 11.7 dBm and dissipated 7.5 mW from a 1.2 V supply. In addition, the TX front-end achieved a power-added efficiency (PAE) of 47% and 1 dB compression point (OP₁dB) of 10.5 dBm. In this case, the output power is 10.5 dBm higher than the linear portion of the response. The methodologies presented herein have the potential to advance the state of the art in 24 GHz radar technology, fostering innovations in fields such as autonomous vehicles, industrial automation, and remote sensing. Full article

In order to meet the increasing demands of wireless communication for ISM bands, a 433 MHz transmitter RF front-end is designed using a 55 nm low-power CMOS technology. The circuits consist of an active mixer, a driver amplifier and a class-E power amplifier (PA). A double-balanced Gilbert active mixer is designed to realize binary phase-shift keying (BPSK) modulation. The driver is used to preamplify the modulated RF signals. The class-E PA adopts a parallel four-branch cascode structure to control the output power level. The load network of the PA is implemented through an off-chip circuit, in which a finite DC-feed inductance load network is selected to reduce the power loss. The mixer and driver are designed with a 1.2 V supply voltage, while the PA is operated at a 1.8 V supply voltage. The area of the chip is 0.206 mm × 0.089 mm, and the measured results show that it achieves a maximum output power of 2.7 dBm, with a total power consumption of 6.72 mW. At a drain efficiency (DE) of 34.5%, an $S_{22}$ less than −10 dB over the frequency ranges from 393.79 MHz to 455.70 MHz can be measured for the PA. With 192 kbps BPSK data modulated at 433 MHz, the measured EVM is about 0.83% rms. Full article

With the development and popularization of the Beidou-3 navigation satellite system (BDS-3), to ensure its unique short message function, it is necessary to integrate a radio frequency (RF) transmitting circuit with high performance in the BDS-3 terminal. As the key device in an RF transmitting circuit, the RF power amplifier (PA) largely determines the comprehensive performance of the circuit with its transmission power, efficiency, linearity, and integration. Therefore, in this paper, an L-band highly integrated PA chip compatible with 3 W and 5 W output power is designed in InGaP/GaAs heterojunction bipolar transistor (HBT) technology combined with temperature-insensitive adaptive bias technology, class-F harmonic suppression technology, analog pre-distortion technology, temperature-insensitive adaptive power detection technology, and land grid array (LGA) packaging technology. Additionally, three auxiliary platforms are proposed, dedicated to the simulation and optimization of the same type of PA designs. The simulation results show that at the supply voltage of 5 V and 3.5 V, the linear gain of the PA chip reaches 39.4 dB and 38.7 dB, respectively; the output power at 1 dB compression point (P1dB) reaches 37.5 dBm and 35.1 dBm, respectively; the saturated output power (Psat) reaches 38.2 dBm and 36.2 dBm, respectively; the power added efficiency (PAE) reaches 51.7% and 48.2%, respectively; and the higher harmonic suppression ratios are less than −62 dBc and −65 dBc, respectively. The size of the PA chip is only 6 × 4 × 1 mm³. The results also show that the PA chip has high gain, high efficiency, and high linearity under both output power conditions, which has obvious advantages over similar PA chip designs and can meet the short message function of the BDS-3 terminal in various application scenarios. Full article

This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)${}^B$, 19 dB (+ 5 dB)${}^B$ and 45% (+ 5% to 10%)${}^B$, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a $732\times 605$ $\mathsf{\mu }$m${}^2$ chip’s surface. (${}^B$: indicates the improved values in the power back-off region). Full article

This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power amplifier (PA). A detailed methodology for the evaluation of the active device’s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting in enhanced performance. A simplified model for the extraction of time-domain intrinsic voltage and current waveforms at the output of the main active core is introduced, enforcing the implementation process of the proposed quasi-inverse class F technique. The PA is fabricated in a 130 nm SiGe BiCMOS technology with $f_T/f_{max}=250/370\mathrm{GHz}$ and it is suitable for 5G applications. It achieves $33\%$ peak power-added efficiency ($PAE$), $18.8\mathrm{dBm}$ saturation output power $P_{sat}$, and $14.7\mathrm{dB}$ maximum large-signal power gain $G$ at the operating frequency of $38\mathrm{GHz}$. The PA’s response is also tested under a modulated-signal excitation and simulation results are denoted in this paper. The chip size is $0.605\times 0.712{\mathrm{mm}}^2$ including all pads. Full article

With the increase in applications of the millimeter wave spectrum for phased array radar systems, mobile 7–13 communication systems, and satellite systems, the demand for a wideband, high-efficiency, high-power monolithic microwave integrated circuit (MMIC) power amplifier (PA) is increasing. In this paper, a 7–13 GHz 10 W high-efficiency MMIC PA is designed. This amplifier consists of a two-stage circuit structure with two high electron mobility transistor (HEMT) cells for the driver stage and four HEMT cells for the power stage. To ensure high efficiency and a certain output power ($P_{out}$), both the driver–stage and power–stage transistors use a deep Class–AB bias. At the same time, in order to further improve the efficiency, low-loss and second–harmonic tuning techniques are used in the output and inter-stage matching networks, respectively. Finally, the electromagnetic simulation results show that within a frequency of 7–13 GHz, the amplifier achieves an average saturated continuous wave (CW) $P_{out}$ of 40 dBm, a small signal gain of 14.5–15.5 dB, a power-added efficiency (PAE) of 30–46%, and the input and output return loss are better than 5 dB and 8 dB, respectively. Full article

This paper presents a compact E-band power amplifier (PA) implemented in a 40 nm CMOS process. The neutralization technique is adopted to improve reverse isolation, stability and power gain. The linearity of the PA is improved by operating the output stage in the deep class-AB region. Transformer-based matching networks (TMNs) are used for impedance transformation, and optimized for output power and efficiency. At 81 GHz, the presented PA achieves a maximum output 1 dB compressed power (P_1dB) of 11.2 dBm and a saturated output power (P_sat) of 12.7 dBm with 1 V supply. The power-added efficiencies at P_1dB (PAE_1dB) and 6 dB power back-off (PBO) are 15.6% and 6.5%, respectively. Full article

A Class-F mode-based power amplifier (PA) with optimized efficiency in triple-band was designed using a simple and systematic approach. By considering the second and third harmonic terminations of the PA, the relationship between the output impedance design space and the drain efficiency (DE) is extracted by large-signal model simulation. Then, a low-pass matching topology is utilized for the triple-band efficiency optimization. The method is justified by both simulation and measurement of a triple-band PA to integrate three functions into one hardware, i.e., 1518–1525 MHz for mobile communication, 2.1 GHz for telemetry and control, and 2.492 GHz for navigation signal transport. The proposed PA achieves a measured result of high DE (63% at 1.52 GHz, 71% at 2.1 GHz, 59% at 2.492 GHz) in the three bands with an output power of at least 40 dBm. Full article

This paper reports a “single-transistor” Class-F⁻¹ power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F⁻¹ harmonic control network, employing a new “parasitic-aware” topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F⁻¹ harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB. Full article

In this paper, the design and implementation of a Doherty power amplifier (DPA) are proposed using gallium nitride high electron mobility transistors (GaN HEMTs). Class-F and Class-C modes are combined to obtain an asymmetric DPA. The precise active load-pull controlling of fundamental and harmonic terminations of the DPA is simulated and analyzed, including the parasitics of the transistors. The measurements of the DPA with the phase difference, input power ratio adjustment, and envelope tracking of the auxiliary PA are discussed in detail in order to achieve a competitive performance. A greater than 63% drain efficiency is obtained within the 10-dB input power dynamic range at 2.1 GHz. The peak of the drain efficiency reaches 73%, with a corresponding output power of 46 dBm. Full article