Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

Abstract

This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)${}^B$, 19 dB (+ 5 dB)${}^B$ and 45% (+ 5% to 10%)${}^B$, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a $732\times 605$ $\mathsf{\mu }$m${}^2$ chip’s surface. (${}^B$: indicates the improved values in the power back-off region).

1. Introduction

The ever-increasing development of radiofrequency and microwave systems, which are widely used in wireless devices such as mobile smartphones, tablets, and laptops, has highlighted the crucial need for efficient power consumption systems [1]. Power amplifiers (PAs) are generally the most dissipative bloc in front-end transceivers, due to their significant gain in power and the strong current drawn by the load. Therefore, several works have aimed to reduce the transceiver power consumption by mainly targeting the power amplifier [2,3]. The design of PAs dedicated for use in mobile systems, essentially those using submicron technologies such as CMOS [4] and BiCMOS, is mainly based on a tradeoff between linearity and efficiency, as adopted for the design of amplitude-modulation transceivers. Power amplifiers can be divided into two main groups. The first, the linear group, is characterized by a very good linearity but a weak efficiency. In contrast, the second one, the switching non-linear group, is defined by a very good efficiency coupled with poor linearity.

Although research on the latter mainly focuses on improving the PA’s performance based on output network tunability, several works have been reported on tuning the output impedance to enhance both the efficiency and output power while minimizing distortions [5,6]. In some cases, a feedback branch constituting series inductance and capacitance was inserted to couple the residue of the RF signal drain, leading to an enhanced in-hand linearity and slightly improving the efficiency of a 3G LTE class-F CMOS power amplifier [7]. By merging the output filter and the output-matching network of a class-F power amplifier, the authors of [8,9] endeavored to reduce the passive components losses, thus obtaining a higher efficiency and higher output power levels. In paper [10], a differential continuous class-F PA with four different output networks based on choke-inductance, transformer-balun, and the second harmonic branch was proposed to enhance the efficiency and output power levels in the desired frequency band. In the same context of shaping drain voltage and current waveforms [11,12,13], second, third or multiple harmonics are kept at GaN, FET and GaAs pHEMT transistor drain levels to make the fundamental and corresponding harmonic components a function of the conduction angle. In [14], the bandwidth was broadened over one octave by using resistive impedance at the second harmonic, resulting in a relative decrease in efficiency while maintaining the same level of output power in a GaN HEMT Class-F power amplifier. Other works have focused on the modulation of the output network by tuning the harmonic resonant and/or the output matching network capacitances, as reported in [15,16,17]. This tunability is ensured by on-chip transformers with parallel variable capacitances, by inserting a high Q varactor to enhance the overall efficiency or by implementing an output matching network based on transmission lines for harmonic control. In this case, the output power is increased by employing a stacked transistor topology and a combiner based on the transformer topology. In [18], a bulk 65 nm CMOS power amplifier based on a Doherty architecture was reported. The amplifier was reconfigured by digitally controlled principal-peaking amplifiers and a power splitter–combiner, providing the option to address the antenna mismatch and enhance the efficiency in the deep back-off region, while respecting the efficiency–linearity trade-off. Mixed non-linear class power amplifiers have also been the subject of research aiming to improve their power efficiency by adding a quarter wave transmission line to the output network, as in [19]. The reported bipolar-based class-FE switching power amplifier was designed using an analytical approach that demonstrated the effects of connecting a parallel transmission line to the collector capacitor on the voltage–current waveforms. Such a structure combines the class-F operating mode with class-E switching conditions, resulting in a high efficiency being achieved at higher frequencies.

Moreover, other reported works have shown the impact of drain waveform shaping on reducing the dissipative power. Mansour, in [20], designed a multi-mode linear (class-AB)/switching (class-F) double-stage cascode PA with an output network constituting of a second–third harmonics network and a series matching network. This structure was mainly employed to drive both sinusoidal and square input signal forms. Dong, in [21], employed a coupled-inductor-based harmonic impedance modulator in order to terminate second and third harmonic load impedances appropriately for an inverse class-F PA operating in mm-wave. Tsai, in [22], proposed a differential power cell class-F PA with a thin oxide MOS ${\mathit{g}}_m$ and a thick oxide HVMOS cascode dedicated to GSM/EDGE/TD-SCDMA/TD-LTE transmitters, where tunability was ensured by transformers and capacitors, designed to maximize the gain and improve linearity .

This paper is organized as follows: In Section 2, the structure of the proposed class-F power amplifier, with an output capacitance in parallel with the cascode stage, will be theoretically analyzed. Then, in Section 3, the class-F power amplifier will be designed and thoroughly compared to existing designs. The conclusion of this work will be outlined in Section 4. Mostly, this work consists of using the analytical approach reinforced by Post-Layout simulations to demonstrate the impact of an additional capacitor on the PA’s performances.

2. Proposed Class-F PA Structure

2.1. Theoretical Study of Class-F Power Amplifiers

In order to reduce the transistor losses and increase the efficiency, the adopted class-F power amplifier is theoretically defined with an infinite number of harmonic resonators at its output to shape the voltage waveform and make it closer to a squared signal [3]. In fact, the class-F structure consists of a capacitor $C_{out}$ in parallel with the cascode transistor stage, as depicted in Figure 1 [3]. This capacitor takes values between [0.1 pF and 1.3 pF] to ensure the PAs’ stability and to avoid huge frequency shifts in the S parameters of the active stage. Note that the bulk sides of all transistors are connected to the ground, except transistor P1, which is connected to ${\mathit{V}}_{DD}$. In addition, a third harmonic resonator is set to combine the third harmonic component with the fundamental one to shape the drain voltage waveform. At the output level, a fundamental resonator is included to bring the fundamental current and voltage components into the load at a central frequency $f_0$ of 2.45 GHz, between [2.4 GHz and 2.5 GHz], for a narrow bandwidth of 100 MHz.

In Figure 2, the parasitic elements of the two transistors $M_1$ and $M_2$ are considered. The output network is composed of an impedance transformation, a third harmonic resonator, a fundamental resonator and a variable capacitor ${\mathit{C}}_{out}$ associated with the parasitic capacitors, ${\mathit{C}}_{gd1}$, ${\mathit{C}}_{gd2}$ the gate-drain capacitances, and ${\mathit{C}}_{db1}$, ${\mathit{C}}_{db2}$ the drain-bulk capacitances. The four capacitors are gathered to make an equivalent capacitor ${\mathit{C}}_{eq}$, defined as

$$C_{eq}=\frac{\left(C_{db2}+C_{gd2}\right)\left(C_{out}\right)}{C_{db1}+C_{gd2}+C_{out}}$$

(1)

The effect of this capacitor on the output impedance ${\mathit{Z}}_{net}$ will determine the behavior of the power amplifier. Transistors ${\mathit{P}}_1$ and ${\mathit{M}}_3$ act as a current mirror that determines the DC current of the power stage by fixing the current gain between the current mirror stage and the power stage. Transistors ${\mathit{P}}_1$ and ${\mathit{M}}_3$ act as a voltage divider that determines the gate voltage of transistor ${\mathit{M}}_1$.

2.2. The Added Output Capacitance’s Effect on the Input Impedance and Stability of the Designed PA

Figure 3 shows the real part of an input impedance ${\mathit{Z}}_{in}$ of a class-F PA, illustrated as follows in expression (2)

$$Z_{in}=\frac{1}{j\omega }\frac{1}{C_{gs1}-\left(C_{gd1}\frac{A}{C-B+D}\right)}$$

(2)

$$A=g_{m1}-j{C}_{gd1}\omega$$

(3)

$$B=\frac{1}{r_{ds1}}+j\left(C_{db1}+C_{gd1}+C_{gs2}\right)\omega$$

(4)

$$C=-g_{m2}+j{C}_{gd2}\omega$$

(5)

$$D=\frac{1}{r_{ds2}}+j\left(C_{out}+C_{gd2}\right)\omega$$

(6)

where the parasitic capacitances ${\mathit{C}}_{gs1}$, ${\mathit{C}}_{gs2}$ and transconductances ${\mathit{g}}_{m1}$, ${\mathit{g}}_{m2}$ are the gate- source capacitances and transconductances of transistors ${\mathit{M}}_1$ and ${\mathit{M}}_2$, respectively.

A, B, C and D are represented in Expressions (2)–(6), respectively. The real part of the impedance ${\mathit{Z}}_{in}$ is strictly positive for different values of ${\mathit{C}}_{out}$; therefore, the designed class-F PA is unconditionally stable.

2.3. Impact of the Added Output Capacitance on the Output Network Impedance

As shown in Figure 2, the output network is composed of the harmonic network and the output matching circuit. The harmonic network, which is mainly formed by combining the proposed output capacitance ${\mathit{C}}_{out}$ with the harmonic circuit (${\mathit{C}}_3$, ${\mathit{L}}_3$) and the fundamental frequency resonator (${\mathit{C}}_0$, ${\mathit{L}}_0$), is responsible for keeping the harmonic components at the drain level, as shown in Figure 2. This structure is expected to guard the voltage third harmonic and current second harmonic components to shape the drain’s voltage and current components, respectively, as well as possible. Analytically, the input impedance of the harmonic network ${\mathit{Z}}_{net}$ can be expressed as a function of the capacitance ${\mathit{C}}_{eq}$ = f(${\mathit{C}}_{out}$), as illustrated in Expression (7).

$$Z_{net}=j\frac{\left(L_0+L_3\right)\left[1-\frac{L_0{L}_3\left(C_0+C_3\right)}{\left(L_0+L_3\right)}{\omega }^2\right]\omega }{\left(1-C_3{L}_3{\omega }^2\right)\left[1-\left(C_0{L}_0+\frac{C_3{C}_{eq}\left(L_0+L_3\right)}{\left(C_3+C_{eq}\right)}\right){\omega }^2\right]}$$

(7)

In this expression, the denominator highlights the existence of two poles corresponding to the third harmonic of the drain voltage and the fundamental component of the drain voltage (which is mainly dependent on ${\mathit{C}}_{eq}$). The nominator exhibits two zeros corresponding to $\omega$ = 0 and $\omega =\mathit{2}{\omega }_0$, with the latter being dependent on ${\mathit{C}}_0$, ${\mathit{C}}_3$, ${\mathit{L}}_0$ and ${\mathit{L}}_3$. Therefore, the impedance ${\mathit{Z}}_{net}$ is responsible for guarding the harmonic components at the drain level.

The magnitude of the purely imaginary output network impedance $\left|Znet\right|$ must be investigated as a function of ${\mathit{C}}_{eq}$ = f(${\mathit{C}}_{out}$) to evaluate its impact on the drain voltage–current waveforms’ shaping and, hence, on the class-F $PA$ performances. As shown in Figure 2, ${\mathit{Z}}_T$ represents the impedance between the optimal resistance of the active stage and the load ${\mathit{R}}_L$, which is equal to the characteristic impedance of the antenna (50 $\Omega$). Applying Thevenin’s theorem, ${\mathit{Z}}_T$ is given by (8),

$$Z_T=-j\left(\frac{L_T}{C_T}\right)\left(L_T\omega -\frac{1}{C_T\omega }\right)$$

(8)

where $L_T$ and $C_T$ are the elements of the output matching network. The total impedance $Z_{tot}$ of the overall output network seen from the active stage, which is a function of the optimal resistance $R_{opt}$ of the power stage, can be expressed as:

$$Z_{tot}=R_{opt}//Z_{net}//Z_T=R_{opt}//\left(j{X}_{net}\right)//\left(j{X}_T\right)$$

(9)

$$Z_{tot}=\frac{R_{opt}{X}_{net}{X}_T}{R_{opt}^2{\left(X_{net}+X_T\right)}^2+X_{net}^2{X}_T^2}\left[X_T{X}_{net}+j{R}_{opt}\left(X_{net}+X_T\right)\right]$$

(10)

where $X_{net}$, $X_T$ represent the reactance parts of impedances $Z_{net}$ and $Z_T$, respectively.

The voltage gain ${\mathit{G}}_v=\frac{V_L}{V_{in}}$, which is the ratio of the load voltage ${\mathit{V}}_L$ to the input voltage ${\mathit{V}}_{in}$, is defined by expression (11). The voltage gain is at the heart of all performance evaluations.

$$G_v=\frac{Z_0{R}_L}{\left(R_L+j{L}_T\omega \right)\left[Z_0+Z_3\left(1+j{Z}_0{C}_T\omega \right)\right]}\frac{A}{C-B+D}$$

(11)

where A, B, C and D are mentioned above and ${\mathit{Z}}_0$ and ${\mathit{Z}}_3$ are the impedances of the fundamental and third harmonic circuits, respectively,

$$Z_0=-j\left(\frac{L_0}{C_0}\right)\left(L_0{\omega }_0-\frac{1}{C_0{\omega }_0}\right)$$

(12)

$$Z_3=-j\left(\frac{L_3}{C_3}\right)\left(L_3\omega -\frac{1}{C_3\omega }\right)$$

(13)

As shown in Figure 4, upon observing the impact of the proposed output capacitor $C_{out}$ on varying fundamental components in Figure 4a, a third harmonic component is clearly demonstrated in Figure 4b of ${\mathit{Z}}_{net}$. This permits the impedance value versus frequency to be shifted, as well as tuning its reactive part. Furthermore, the capacitance $C_{out}$ allows for the total output impedance ${\mathit{Z}}_{tot}$ to be tuned, slightly reinforcing the magnitude of the third harmonic voltage component. Its real part is equal to the optimal resistance $R_{opt}$ = 130 $\Omega$ at the operating frequency $f_0$. In addition, prior calculations have demonstrated that the second harmonic current is dependent on the nominator of ${\mathit{Z}}_{net}$. As a result, the two kept components, i.e., the third harmonic voltage and the second harmonic current, will be merged with the fundamental voltage/current components, respectively. Therefore, designing a class-F PA by modulating the drain–bulk capacitance by varying ${\mathit{C}}_{out}$ looks to be a quite promising and original approach to better shaping the drain waveforms. Although the conventional concept of a class-F PA design leads to an improved drain efficiency and power, in addition to power compression and saturated power points, the proposed approach should improve the complete performance in the entire power back-off region, while maintaining a good linearity.

2.4. Added Output Capacitance’s Impact on Parameters at the Drain Level

Before exploiting the above-mentioned approach, let us set some well-known key design parameters. To establish a relationship between the drain efficiency $\mathsf{\eta }$ and the drain power dissipation of transistor $M_2$, we must begin by illustrating the relation between modules of instantaneous drain dissipative power and instantaneous drain voltage–current, expressed as

$$\left|p_D\left(t\right)\right|=\frac{1}{2\pi }{\int }_0^{2\pi }{v}_{DS}\left(t\right)i_D\left(t\right)d\theta =V_{DD}{I}_D-\frac{V_m{I}_m}{2}$$

(14)

where ${\mathit{V}}_{DS}\left(t\right)$ and ${\mathit{i}}_D\left(t\right)$ are the instantaneous drain voltage and drain current, respectively. Furthermore, ${\mathit{V}}_m$ and ${\mathit{i}}_m$ are fundamental voltage–current components, respectively. Figure 5a represents the amplitude of dissipating power, which exhibits a remarkable decrease with the evolution of $C_{out}$. Expression (14) leads to

$$P_D=P_{DC}\left(1-\eta \right)$$

(15)

where ${\mathit{P}}_{DC}$ is the power supplying the PA. Notice that the drain efficiency $\eta$ has a direct relationship with ${\mathit{C}}_{out}$ through the voltage gain ${\mathit{G}}_v$, as will be demonstrated below in (22)–(28). Thus, from (14) and (15), the maximal drain voltage magnitude has the following expression

$$V_{DS max}=\frac{P_{DC}\left(1-\eta \right)}{I_{D max}}$$

(16)

where ${\mathit{V}}_{DSmax}$ and ${\mathit{I}}_{Dmax}$ are the maximal values of drain voltage and current waveforms, respectively, which are directly deduced from the Fourier transforms of the time-domain drain voltage–current waveforms, expressed as

$$v_{DS}=V_{DD}+V_{m}coscos\left({\theta }_0\right)-V_{m3}coscos\left(3{\theta }_0\right)$$

(17)

$$i_D=I_D-I_{m}coscos\left({\theta }_0\right)+I_{m2}cos\left(2{\theta }_0\right)$$

(18)

where ${\mathit{V}}_m$ and ${\mathit{V}}_{m3}$ are the amplitudes of the fundamental and third voltage components, respectively, whereas ${\mathit{I}}_m$ and ${\mathit{I}}_{m2}$ are the amplitudes of the fundamental and second harmonic current components, respectively. Furthermore, the DC components of $v_{DS}$ and $i_D$ are depicted in Figure 5b and Figure 5c, respectively, where the former increases and latter decreases with the evolution of $C_{out}$. To obtain the optimal resistance $R_{opt}$ of the active stage, we applied the maximally flat drain voltage waveform reported in [3] by calculating the maximal amplitudes at pulsation ${\theta }_0=\pi$. The DC component of the current for the class-F PA is then

$$I_D=\frac{9\left(V_{DD}-V_{DS min}\right)}{4\pi R_{opt}}$$

(19)

where ${\mathit{V}}_{DD}$ is the supplied voltage and ${\mathit{V}}_{DSmin}$ is the knee voltage. Then, from (17) to (19), we have

$$V_m^2-\left(\frac{9}{8}{V}_{DD}-R_{opt}{I}_D\right)V_m+9\frac{R_{opt}}{8}\left(P_{DC}\left(1-\eta \right)-I_D{V}_{DD}\right)=0$$

(20)

As can be noted, this equation is a second-order equation with two solutions, which are

$$V_{m\pm }=\frac{1}{2}\left(\frac{9}{8}{V}_{DD}-R_{opt}{I}_D\right)\pm \sqrt{{(\frac{9}{8}{V}_{DD}-R_{opt}{I}_D)}^2-9\frac{R_{opt}}{8}(P_{DC}(1-\eta )-I_D{V}_{DD})}$$

(21)

Let ${\mathit{V}}_{m3}=\frac{V_m}{5.66}$, ${\mathit{I}}_m=\frac{V_m}{R_{opt}}$ and ${\mathit{I}}_{m2}=\frac{I_m}{4.23}$ be the harmonic component relationships deduced beforehand using the power stage spectra extracted from simulations for ${\mathit{C}}_{out}=0$. They were recalculated through $V_{m\pm }$ values following Formula (21) for ${\mathit{C}}_{out}\ne 0$. According to Figure 6, the fundamental and harmonic forms of drain voltage–current could evolve with a capacitance ${\mathit{C}}_{out}$ to a good shaping, thus enlarging the overlap between drain waveforms and weakening the dissipate power ${\mathit{P}}_D$. More accurately, a third harmonic voltage is merged with a fundamental one and the second harmonic current is merged with the fundamental one at the drain level, where the voltage and current are out-phased at ${180}^{\circ }$. Thus, the added capacitance reduces the current and reinforces the voltage in the first half-period and acts inversely in the second half-period, provoking a drain dissipate power reduction. This operation impacts the PAs’ output parameters, as will be shown in the next section

2.5. The Added Output Capacitor’s Impact on Class-F Power Amplifier Performance

As a result of the added output capacitance ${\mathit{C}}_{out}$ having a considerable impact on the output network impedance and the drain signal waveforms, the whole performance of the designed class-F power amplifier are affected, the parameters of which are summarized in

Table 1. Proposed class-F PA amplifier: design parameters.

Parameter	$VDD$ (V)	$\eta$(max) %	$P_{DC}$ (dBm)	$V_{gs0}$ (V)	$C_{ox}$ (pF/m${}^2$)	$C_{ov}$ (fF)	$CM$ (pF)	$LM$ (nH)	$C_{gs1}$ (pF)	$C_{gs2}$ (pF)	$C_{gd1}$ (pF)	$C_{gd2}$ (pF)	$C_{db1}$ (pF)
Value	1.2	70	8	0.24	0.014	0.14	0.175	7.78	4.24	0.48	0.018	0.056	1.176
Parameter	$C_{db2}$ (pF)	$L_f$ (nH)	$L_3$ (nH)	$C_3$ (pF)	$L_0$ (nH)	$C_0$ (pF)	$L_T$ (nH)	$C_T$ (pF)	$r_{ds1}$ $(\Omega )$	$r_{ds2}$ $(\Omega )$	$gm1$ (mA/V)	$gm2$ (mA/V)	$R_{opt}$ $(\Omega )$
Value	0.424	2.4	0.642	0.736	1.91	2.22	1.26	0.555	1.17.10${}^7$	5.6.10${}^4$	0.38	0.128	130

. Therefore, the intrinsic parasitic components of the two transistors refer to the BSIM 4 model, which simulates the $0.13$ $\mathsf{\mu }$$\mathrm{m}$ BiCMOS process.

To investigate the effect of ${\mathit{C}}_{out}$ on the amplifier, let us begin by expressing its input power ${\mathit{P}}_{in}$ and load power ${\mathit{P}}_L$

$$P_L=\frac{1}{2}\frac{{\left|V_L\right|}^2}{Re\left\{Z_L\right\}}\frac{P_{in}}{P_{in}}$$

(22)

$$P_{in}=\frac{1}{2}\frac{{\left|V_{in}\right|}^2}{Re\left\{Z_{in}\right\}}$$

(23)

where ${\mathit{Z}}_{in}$ and ${\mathit{Z}}_L$ are the input and load impedances, respectively. From the above expressions, we can obtain

$$P_L=\frac{Re\left\{Z_{in}\right\}}{Re\left\{Z_L\right\}}\frac{{\left|V_L\right|}^2}{{\left|V_{in}\right|}^2}{P}_{in}$$

(24)

For the active stage, we can deduce the power gain

$$G_P=\frac{Re\left\{Z_{in}\right\}}{Re\left\{Z_L\right\}}{\left|G_v\right|}^2$$

(25)

Thus, the drain efficiency, $\eta$, and the power-added efficiency, PAE, are

$$\eta =\frac{Re\left\{Z_{in}\right\}}{Re\left\{Z_L\right\}}{\left|G_v\right|}^2\frac{P_{in}}{P_{DC}}$$

(26)

$$PAE=\frac{Re\left\{Z_{in}\right\}}{Re\left\{Z_L\right\}}{\left|G_v\right|}^2\frac{P_{in}^2}{P_{DC}}\left(\frac{1}{P_{in}}-\frac{1}{P_L}\right)$$

(27)

The voltage gain in these equations constitutes a key design parameter from which all the other PA performance metrics can be deduced using the data shown in Table 1. After a theoretical development, ${\mathit{I}}_L$ can be expressed as

$$I_L={\left(\frac{2G_p{P}_{in}}{R_L}\right)}^{\frac{1}{2}}$$

(28)

Analytically, two important parameters are sufficiently demonstrated to illustrate the effect of ${\mathit{C}}_{out}$ on the PA’s performance improvement. In fact, Figure 7a illustrates the output current experienced to the load with frequency evolution for different values of ${\mathit{C}}_{out}$, following the expression (28). This figure demonstrates a substantial consequent increase in the load current and output power. Furthermore, ${\mathit{C}}_{out}$ serves to broaden the PAs bandwidth, as this capacitance permits an overall quality factor degradation. Similarly, the drain efficiency $\eta$ and the added power efficiency PAE as functions of capacitance ${\mathit{C}}_{out}$ (Expressions (26) and (27)), are shown in Figure 7b. These two performances are clearly improved by 5%, from 40% to 45% for the first one, and from 41% to 46% for the second.

3. Class-F Power Amplifier Design with Lossy Components

Before tackling the effect of lossy components in this section, it is necessary to point out that optimizations to the layout have led to the suppression of the inductance ${\mathit{L}}_T$ of the PA because the output matching can only be ensured by the output network effect associated with capacitance ${\mathit{C}}_T$. In addition, post-layout simulations were performed with an extreme capacitance value (${\mathit{C}}_{out}$ = 1.3 pF). As shown in Figure 8a, the added output capacitance ${\mathit{C}}_{out}$ increased the insertion loss in the PA’s input and output by 16 dB and 5 dB, respectively, even when considering an impedance transformation between an optimal resistance ${\mathit{R}}_{opt}$ and an ${\mathit{R}}_L$ of 50 ohm. This would be essentially due to the mismatches in the input–output impedances while varying ${\mathit{C}}_{out}$. Such an effect could be overcome using variable capacitances as varactors in the input–output matching networks. In contrast to real component simulations, where ${\mathit{S}}_{22}$ is superior to 0, as seen in Figure 8b, PLSs reveal ${\mathit{S}}_{22}\approx -$6 dB (${\mathit{C}}_{out}$ = 1.3 pF) without ${\mathit{L}}_T$. Moreover, an advantage of this work is the improvement in $S_{21}$ by 4 dB, as shown in Figure 8c, while tuning the added capacitor. A maximal value of ${\mathit{C}}_{out}$ = 1.3 pF should decrease in hand the harmonic network impedance ${\mathit{Z}}_{net}$ and therefore decrease the total output impedance ${\mathit{Z}}_{tot}$ to reduce the dissipate power in the other hand. However, ${\mathit{C}}_{out}$ causes mismatches in the output matching network as a drawback of the added capacitor. The effect of ${\mathit{C}}_{out}$ is also significant for the drain waveforms, as shown in Figure 9a,b. In fact, during the positive half-cycle, the drain voltage attains a maximal value of 1.8 V whereas the minimal value of the drain current is 0 mA. In the second half-period, the maximal value of the drain current is 26 mA while the minimal value of the drain voltage is $0.48$ V. As a result, the dissipate power will decrease, allowing for the efficiency to increase. Furthermore, the load current is large with the added capacitor ${\mathit{C}}_{out}$, as illustrated in Figure 9c, leading to a higher output power and power gain. However, the only observed drawback in Figure 9 is a fast shift in the operating frequency between the waveforms extracted by ${\mathit{C}}_{out}$ null and ${\mathit{C}}_{out}$, equal to 1.3 pF. Such a shift is the effect of ${\mathit{C}}_{out}$ in the output matching network.

3.1. Performance of Real Class-F Power PAs

The most important results of this work are demonstrated in this section, where the key output parameters of the designed class-F power amplifier are presented. In Figure 10a, we can observe that, in the back-off region between −30 dBm and −10 dBm, the maximum PAE increased by 10% for Pin = −20 dBm. This can be observed while taking the input–output impedance mismatches due to $C_{out}$ into consideration. Moreover, the saturated efficiency PAE also increased from 43% ($C_{out}=0$) to 45% ($C_{out}$= 1.3 pF). In Figure 10b, the power gain is shown to be quite flat. Second, the added output capacitor $C_{out}$ did not have any effect on the compressed output power $P_L$(−1 dB), which remains practically constant. Furthermore, it increases for $P_{in}$ = −40 dBm, from −21 dBm ($C_{out}=0$) to −16 dBm ($C_{out}$ = 1.3 pF) and for $P_{in}$ = −20 dBm from −1 dBm ($C_{out}$ = 0) to 3 dBm ($C_{out}$ = 1.3 pF). Similarly, for $P_{in}$= −20 dBm, the power gain increased from 18 dB ($C_{out}$ = 0) to 23.7 dB ($C_{out}$ = 1.3 pF). In other words, the output power is enhanced in the power back-off region.

Post-layout simulations showed a compressed load power point $P_L$(−1 dB) of around 4.56 dBm and an output third-order intercept point OIP3 at 12.5 dBm, respectively, compared to the only article [17] that considers linearity as a criterion, which reported an OIP3 equal to 25.4 dBm for a $P_L$(−1 dB) of 20.2 dBm. These two parameters indicate the good linearity of the designed PA, as depicted in Figure 10c. Furthermore, a power gain $G_p$ of 20 dB and a significant degradation in the added power efficiency (PAE) to 28% are noted, due to the resistive losses in implemented inductances in the layout. Such a phenomenon is observed in other reported designs, such as [5,16,19].

3.2. Layout of the Designed Class-F Power Amplifier

Simulations were carried out using the Cadence virtuoso 6 Calibre simulator, with the $0.13$ $\mathsf{\mu }$$\mathrm{m}$ BiCMOS design kit as a process. As shown in Figure 11, the designed class-F PA has an active area of $732\times 605$ $\mathsf{\mu }{\mathrm{m}}^2$. Unfortunately, the four inductances occupy most of that surface, especially the seven-turn inductance $L_M$ of $7.78$ nH with a series resistance $R_S\approx 5$ Ohm. In reality, the surface occupied by the inductances represents more than 60% of the total chip area, which leads to more resistive losses and more restrictions during the design rules check (DRC step), the reason for the inductance $L_T$ suppression. Parasitic extraction was performed by quantus QRC instead of EM simulations to display RLC parasitics.

In this layout, we utilized all six metallic levels that were allowed with $0.13$ $\mathsf{\mu }$$\mathrm{m}$ BiCMOS technology. More precisely, thin metals 1 and 2 were employed to ensure the (ground and supply) connections of the circuit. Thick metal 6 was used to transport the RF signal from the input to the output of the PA while ensuring the shortest connection. Metals 3, 4 and 5 were used to connect the different components in the circuit. Note that pads were not used in this layout because the designed PA was intended to be implemented on an overall transmitter dedicated to IoT application. Therefore, post-layout simulations were ensured through specific input/output layers.

Table 2. Comparison of this work with state-of-the-art methods (***: measured values, **: post-layout simulation values. *: ITRS FOM = PSAT (dBm) + Gain (dB) + 20log10 (Freq (GHz)) + 10log10 (PAE)) [23].

Ref.	Technology	Frequency (GHz)	VDD (V)	PDC (mW)	PL (dBm)	GP (dB)	PAE (%)	Area (mm${}^2$)	Class	ITRS FOM	Technique
[5]	$0.18$ $\mathsf{\mu }$$\mathrm{m}$ CMOS	2.4	3–4	-	18.7 ** 19.5 *** (Sat)	10.2 ** 11.5 ***	28.9 ** 26 ***	2.56	F	32.75	- Reconfigurable load-impedance matching.
[7]	0.18 $\mathsf{\mu }$m CMOS	0.869	3.3	-	26.7 *** (max)	31.2 ***	34.2 ***	1.496	F	-	- Off-chip OMN and feedback.
[8]	40 nm CMOS	2.4	0.56–0.2	-	−20 *** (Sat)	-	42 ***	0.3	F	-	- Merging OMN and Filter to improve an output power.
[10]	40 nm CMOS	2.4	2.7	-	27 ** (Sat)	-	68 ** (Sat)	-	F	-	- Design of CCF PA with Transformer Balun, RF Shock, 2nd Harmonic Branch.
[17]	0.18 $\mathsf{\mu }$m CMOS	2.6	1.8	716.4	≈21 *** (sat)	13.1 ***	24.4 ***	0.998	F	36.27	- Tunable harmonic termination.
[20]	$0.13$ $\mathsf{\mu }$$\mathrm{m}$ CMOS	4.8	3	136/26	23/22.3 ** (Sat)	24/27 **	29.5/28.6 ** (Sat)	0.53	F	55.32	- Linear/switching modes with tuning output network.
[22]	153 nm CMOS	2.4	3.5	-	31.5 *** (Sat)	35.3 ***	35 ***	2.9	F	-	- GSM/EDGE/TD- SCDMA/TD-LTE by transformer combination.
[24]	65 nm CMOS	2.4	0.3–0.7	15.3 (Sat)	6 *** (Sat)	–	26.1 *** (Sat)	0.39	F	-	- Function reuse class-F DCO-PA + ADPLL.
[25]	$0.18$ $\mathsf{\mu }$$\mathrm{m}$ CMOS	4.6	3.6	158	27.8 *** (Sat)	11.6 ***	32 *** (Sat)	2.32	F	47.71	- Differential topology based on the transformer combiner.
This work	$\mathbf{0.13}$ $\mathsf{\mu }$$\mathbf{m}$ BiCMOS	2.4	1.2	5–8	8 **(Sat) (+5 PBO) 4.56 ** ${\mathit{P}}_{\mathit{L}}$ (−1 dB)	20 ** (+5 PBO)	28 ** (+10 PBO)	0.43	F	35.05	- Tuned output network by cascode stage output capacitor modulation.

compares the performance of the designed class-F power amplifier and existing designs reported in the technical literature. All the presented PAs are based on a class-F CMOS, except for the work reported in [21], which was designed with SiGe 0.13 um technology and adopts an inverse class-F as the operating class.

Furthermore, all reported works adopted the tuned output network approach (via harmonic or matching circuits).

In the results, the PAE of the designed PA attained a good saturated level of 45% (28% for the post-layout simulations), allowing for an increase in the overall efficiency in the back-off region of between 5% and 10%. This is slightly significant compared to the PA in [5], designed using $0.18$ $\mathsf{\mu }$$\mathrm{m}$ CMOS technology, where inductances cover a small area, consequently causing a weak loss. Otherwise, the maximal output power reaches 19.5 dBm for a power gain of 11.5 dB and a higher supply voltage of 4 V. Employing feedback formed of an inductance–capacitance series in [7] allows for the preservation of the drain voltage in a saturated region, enhancing the efficiency to attain 34.2 for an LTE output power level of 26.7 dBm and a power gain of 31.2 dB. This performance is good regarding the operating frequency and supply voltage.

Compared to [8], a high efficiency of 42% was observed for a switching class-F PA designed with CMOS 40 nm technology. Conversely, a very low debited power of −20 dBm was observed, even if the output-matching network and filter were merged. As for the results in [10], post-layout simulations demonstrated a higher peak efficiency of 68% for a saturated output power of 27 dBm, thanks to an output network based on multi-mode operation using RF choke inductance, a second harmonic branch, and a transformer-balun, permitting a decrease in the drain impedance. However, the only drawback is the area occupied by the whole circuit. The design reported in [17], adopting a class-AB driver and class-F power stage structures, expressed a measured efficiency of 24.4% for a saturated output power of 21 dBm and a power gain of 13.1 dB to meet WiMAX features. Therefore, a PA of an output network designed with transformer lines was implemented over a chip area of 0.99 mm${}^2$, except the third harmonic branch, which was mounted off-chip. Nevertheless, the consumption power of 716 mW is very high for this kind of application. Similar to our PA, a reported work [20] designed differential class-F modes under two blocs (Driver + Power stage); the saturated efficiency was 29.5% for a saturated output power of 23 dBm and a power gain of 24 dB. The circuit was totally integrated and implemented over a chip area of 0.53 mm${}^2$, which seems acceptable. Otherwise, this circuit consumes a huge amount of power at 136 mW. Ref. [22] reported a class-F PA designed with CMOS 0.153 $\mathsf{\mu }$m technology that expressed a saturated efficiency of 35% for a peak output power of 31.3 dBm and a power gain of 35.3 dB, constituting a very high performance regarding the power splitting–combining technique that experiences high power at the load level in order to cover different transmission standards. The PA is implemented on a chip area of under 2.9 mm${}^2$, taking into account the employed transformers. The switching class-F PA reported in [24] demonstrated a measured saturated efficiency of 26.1% for a saturated output power of 6 dBm, drawing a weak power consumption of 15.3 mW with a small chip surface of 0.39 mm${}^2$. Finally, article [25], where the class-F PA is based on a splitter–combiner transformer topology, showed important results in the measured efficiency, which equalled 32% for an output power and power gain of 27.8 dBm and 11.6 dB, respectively. However, this circuit has a significant power consumption of 158 mW and occupies a large chip surface of 2.32 mm${}^2$. In summary, compared with the different works reported in Table 2, this contribution, in addition to adding a current harmonic component, presents the advantage of improving the PA performance by modulating the drain–bulk capacitance, with an efficiency of 10%, an output power of 5 dBm and a power gain of 5 dB in the back-off region. Moreover, our circuit consumes a small amount of power (about 6 mW) and is implemented on a surface of 0.43 mm${}^2$, representing a good performance. Upon analysis of the figure of merit (ITRS FOM) related to our PA, which is equal to 35.05, it seems very low compared to the others reported in Table 2, which can be attributed to the weak output power and low operating frequency values of our design.

4. Conclusions

In this work, an integrated class-F power amplifier, dedicated to low-power I-Q amplitude modulation wireless transceivers with a modulated added output capacitor parallel with cascode transistor, was successfully designed. At first, a theoretical analysis was performed, considering lossless components, to investigate the effect of an added capacitor on the PA performance. In fact, adding and varying this capacitor led to the creation of a new second current harmonic that participates in shaping the drain’s voltage-current waveforms at the cascode transistor level to reduce the dissipative drain power. By using cadence tools to simulate the added capacitor’s impact on the PA, the results demonstrated an enhancement of output power by 8 dBm, power gain of 19 dB, and power-added efficiency from 40 to 45, and again by (+5 dBm), (+5 dB) and (+5% to 10%) in the power back-off region from −30 to −10 dBm, respectively. Post-layout simulations (PLS) were performed on the designed class-F PA to reveal an improvement in load power of 5 dBm $(-50\mathrm{dBm}\le PBO\le -20\mathrm{dBm},8\mathrm{dBm})$ power gain of 20 dB (+5 dB in the same PBO), overall efficiency of from 5 to 10% ($-50\mathrm{dBm}\le PBO\le -15\mathrm{dBm}$, and 28% for $C_{out}$ = 1.3 pF. The designed class-F PA was implemented over a chip area of $732\times 605$ $\mathsf{\mu }$m${}^2$. Accordingly, the previously highlighted trade-offs can be avoided by designing miniaturized efficient class-F PA useful in the linear transceivers.