A Compact Transformer-Based E-Band CMOS Power Amplifier with Enhanced Efficiencies of 15.6% PAE_1dB and 6.5% PAE at 6 dB Power Back-Off

Abstract

This paper presents a compact E-band power amplifier (PA) implemented in a 40 nm CMOS process. The neutralization technique is adopted to improve reverse isolation, stability and power gain. The linearity of the PA is improved by operating the output stage in the deep class-AB region. Transformer-based matching networks (TMNs) are used for impedance transformation, and optimized for output power and efficiency. At 81 GHz, the presented PA achieves a maximum output 1 dB compressed power (P_1dB) of 11.2 dBm and a saturated output power (P_sat) of 12.7 dBm with 1 V supply. The power-added efficiencies at P_1dB (PAE_1dB) and 6 dB power back-off (PBO) are 15.6% and 6.5%, respectively.

1. Introduction

Driven by the exponential increase in data traffic, millimeter-wave frequency bands of 57–66 GHz, 71–76 GHz and 81–86 GHz have been proposed for 5G communication owing to their large available bandwidth [1,2]. Several types of E-band RF circuits have been reported [3,4,5,6], and the high-efficiency power amplifier (PA) is an essential component in the transmitter. High-order modulation schemes with a high peak-to-average power ratio (PAPR) are employed to realize higher data rates. In order to preserve signal integrity and linearity, PA has to operate in power back-off (PBO) mode [5,6].

High output 1 dB compressed power (P_1dB) and power-added efficiency at P_1dB (PAE_1dB) are among the major difficulties for the PA design, due to the lossy substrate, low supply voltage, and low gain of transistors based on the CMOS process at millimeter-wave frequencies [7]. The power-combining technique has been proposed to achieve a higher output power [8,9,10] with the drawback of degraded efficiency.

Doherty [11], outphasing [12] and balanced structures [13] have been proposed to improve PA linearity. In [11], a transformer-based Doherty PA at the E-band is presented with a P_1dB of 19.2 dBm and a PAE_1dB of 12.4% at 1.5 V supply voltage. A 60 GHz transmitter incorporating an outphasing PA is proposed in [12], achieving 12.5 dBm average output power and 15% average PAE. A class-F balanced power amplifier with input and output couplers is proposed in [13] to improve the linearity and efficiency; however, PAs based on the above design schemes require complex output matching networks, leading to a larger chip area.

Power amplifiers with P_1dB close to the saturated power (P_sat) are preferred for power performance in the PBO mode [6]. Recently, several compact PA structures with a high saturated output power have been implemented [2,3,5], yet they suffer from soft saturation with P_1dB severely lower than P_sat, with a P_1dB/P_sat ratio about 75% in dBm [2].

In this paper, we present a compact E-band CMOS PA with high efficiency and P_1dB close to P_sat. The transformer-based matching networks (TMNs) are used for impedance transformation and optimized for output power and efficiency. Fabricated in the 40 nm CMOS process, the presented PA achieves 11.2 dBm P_1dB and 12.7 dBm P_sat, with a P_1dB/P_sat ratio of 88% in dBm. The power-added efficiencies at P_1dB and 6 dB PBO are 15.6% and 6.5%, respectively.

This paper is organized as follows. Section 2 presents the topology of the PA. Section 3 provides the theoretical analyses and design considerations for the TMNs. Section 4 presents the measurement results of the presented PA, and Section 5 concludes the paper.

2. E-Band PA Circuit Topology

The schematic of the presented single-path PA is illustrated in Figure 1. Each stage employs a common-source pseudo-differential pair with neutralization capacitors [14]. The gate of the common-source stage is biased through resistors to improve the common-mode stability of the amplifier [8]. The neutralization capacitors in the PA are implemented with mimcap. The driver stage is sized down by a factor of two to provide sufficient driving power to the output stage. On-chip transformers are used to perform desired impedance transformations in the output and inter-stage matching networks. The common-mode gain of the differential pair is reduced by using bypass capacitors (not shown in Figure 1) to improve the common-mode stability.

Figure 2 shows the simulation results of P_1dB, P_sat, and the gain of the output and driver stages versus the transistor current density. P_sat and gain of the output stage both increase as the current density increases, while a valley exists in the P_1dB curve. The difference between the P_1dB and P_sat of the output stage can be reduced when the transistors are biased in the deep Class-AB region with a current density lower than 30 μA/μm. This is due to the internal harmonic cancelations of the deep Class-AB operation, which forms a minimum linear point when the output power increases close to P_sat [15]. To compensate the gain degradation of the output stage, the driver stage is biased for a high gain.

3. PA Circuit Design with Transformer-Based Matching Network

To improve output power and efficiency, the output and inter-stage matching networks are designed to provide optimal load impedances for the transistors they are connected to [7]. The circuit design and parameter optimization are carried out with the guidance of following impedance formulations and demonstrated by the output matching network.

3.1. Impedance Formulations for TMN

The circuit model of the TMN for output matching is illustrated in Figure 3a, where k_o is the magnetic coupling coefficient and L_o1 and L_o2 are the transformer inductances. R_o1 and R_o2 are the transformer parasitic resistances. The source of the output matching network is the output impedance of the output stage, which can be simplified as resistance R_oS and capacitance C_oS in parallel. The above circuit model can also be applied to the load in the output matching network, as well as the source in the inter-stage matching network.

The TMN circuit model for inter-stage matching is illustrated in Figure 3b, where k_i is the magnetic coupling coefficient, L_i1 and L_i2 are the transformer inductances, and R_i1 and R_i2 are the transformer parasitic resistances. The source of the inter-stage matching network is modeled as resistance R_iS and capacitance C_iS in parallel, and the load is the input impedance of the output stage, which can be represented by resistance R_iL and capacitance C_iL in series.

An optimal load impedance is required at the transistor-cell output to achieve a larger output power and higher power-added efficiency. As the source capacitance and resistance are retrieved according to the load–pull characteristics of the transistor cell, the design target for the output matching network is equivalent to achieving Z_oin = Z_oopt, where Z_oin is the input impedance of the transformer in the TMN for output matching and Z_oopt is the optimal load impedance of the output stage.

The load of the output matching network is modeled as capacitance C_oL and resistance R_oL in parallel; thus, Z_oin becomes:

$$\begin{array}{cc}{Z}_{\mathrm{oin}}& =R_{\mathrm{o}1}+\frac{{\omega }^2{k}_{\mathrm{o}}^2{L}_{\mathrm{o}1}{L}_{\mathrm{o}2}({\omega }^2{R}_{\mathrm{o}2}{R}_{\mathrm{oL}}^2{C}_{\mathrm{oL}}^2+R_{\mathrm{o}2}+R_{\mathrm{oL}})}{{(R_{\mathrm{o}2}+R_{\mathrm{oL}}-{\omega }^2{C}_{\mathrm{oL}}{R}_{\mathrm{oL}}{L}_{\mathrm{o}2})}^2+{\omega }^2{(C_{\mathrm{oL}}{R}_{\mathrm{oL}}{R}_{\mathrm{o}2}+L_{\mathrm{o}2})}^2}\hfill \\ & +j\omega [L_{\mathrm{o}1}+\frac{{\omega }^2{k}_{\mathrm{o}}^2{L}_{\mathrm{o}1}{L}_{\mathrm{o}2}(C_{\mathrm{oL}}{R}_{\mathrm{oL}}^2-L_{\mathrm{o}2}-{\omega }^2{C}_{\mathrm{oL}}^2{R}_{\mathrm{oL}}^2{L}_{\mathrm{o}2})}{{(R_{\mathrm{o}2}+R_{\mathrm{oL}}-{\omega }^2{C}_{\mathrm{oL}}{R}_{\mathrm{oL}}{L}_{\mathrm{o}2})}^2+{\omega }^2{(C_{\mathrm{oL}}{R}_{\mathrm{oL}}{R}_{\mathrm{o}2}+L_{\mathrm{o}2})}^2}]\hfill \end{array}$$

(1)

L_o1 and k_o can be obtained according to Z_oin = Z_oopt:

$$L_{\mathrm{o}1}=\frac{\mathrm{Im}[Z_{\mathrm{oopt}}]}{\omega }-(\mathrm{Re}[Z_{\mathrm{oopt}}]-R_{\mathrm{o}1})\frac{C_{\mathrm{oL}}{R}_{\mathrm{oL}}^2-L_{\mathrm{o}2}-{\omega }^2{C}_{\mathrm{oL}}^2{R}_{\mathrm{oL}}^2{L}_{\mathrm{o}2}}{{\omega }^2{R}_{\mathrm{o}2}{R}_{\mathrm{oL}}^2{C}_{\mathrm{oL}}^2+R_{\mathrm{o}2}+R_{\mathrm{oL}}}$$

(2)

$$k_{\mathrm{o}}=\sqrt{(\mathrm{Re}[Z_{\mathrm{oopt}}]-R_{\mathrm{o}1})\frac{{(R_{\mathrm{o}2}+R_{\mathrm{oL}}-{\omega }^2{C}_{\mathrm{oL}}{R}_{\mathrm{oL}}{L}_{\mathrm{o}2})}^2+{\omega }^2{(C_{\mathrm{oL}}{R}_{\mathrm{oL}}{R}_{\mathrm{o}2}+L_{\mathrm{o}2})}^2}{{\omega }^2{L}_{\mathrm{o}1}{L}_{\mathrm{o}2}({\omega }^2{R}_{\mathrm{o}2}{R}_{\mathrm{oL}}^2{C}_{\mathrm{oL}}^2+R_{\mathrm{o}2}+R_{\mathrm{oL}})}}$$

(3)

Equations (2) and (3) provide the values for L_o1 and k_o as a function of L_o2, which can serve as a guideline for the design of transformer layout in the output matching network. Transformer layouts can be simulated using a 3D electromagnetic (EM) simulator.

The design target for the inter-stage matching network is equivalent to achieving Z_iin = Z_dopt, where Z_iin is the input impedance of the transformer in the TMN for inter-stage matching, and Z_dopt is the optimal load impedance of the driver stage.

The load of the inter-stage matching network is modeled as resistance R_iL and capacitance C_iL in series; thus, Z_iin becomes:

$$\begin{array}{cc}{Z}_{\mathrm{iin}}& =R_{\mathrm{i}1}+\frac{{\omega }^4{k}_{\mathrm{i}}^2{L}_{\mathrm{i}1}{L}_{\mathrm{i}2}{C}_{\mathrm{iL}}^2(R_{\mathrm{i}2}+R_{\mathrm{iL}})}{{\omega }^2{C}_{\mathrm{iL}}^2{(R_{\mathrm{i}2}+R_{\mathrm{iL}})}^2+{({\omega }^2{C}_{\mathrm{iL}}{L}_{\mathrm{i}2}-1)}^2}\hfill \\ & +j\omega [L_{\mathrm{i}1}+\frac{{\omega }^2{k}_{\mathrm{i}}^2{L}_{\mathrm{i}1}{L}_{\mathrm{i}2}{C}_{\mathrm{iL}}(1-{\omega }^2{C}_{\mathrm{iL}}{L}_{\mathrm{i}2})}{{\omega }^2{C}_{\mathrm{iL}}^2{(R_{\mathrm{i}2}+R_{\mathrm{iL}})}^2+{({\omega }^2{C}_{\mathrm{iL}}{L}_{\mathrm{i}2}-1)}^2}]\hfill \end{array}$$

(4)

L_i1 and k_i can be obtained according to Z_iin = Z_dopt:

$$L_{\mathrm{i}1}=\frac{\mathrm{Im}[Z_{\mathrm{dopt}}]}{\omega }-(\mathrm{Re}[Z_{\mathrm{dopt}}]-R_{\mathrm{i}1})\frac{{\omega }^2{k}_{\mathrm{i}}^2{L}_{\mathrm{i}1}{L}_{\mathrm{i}2}{C}_{\mathrm{iL}}(1-{\omega }^2{C}_{\mathrm{iL}}{L}_{\mathrm{i}2})}{{\omega }^4{k}_{\mathrm{i}}^2{L}_{\mathrm{i}1}{L}_{\mathrm{i}2}{C}_{\mathrm{iL}}^2(R_{\mathrm{i}2}+R_{\mathrm{iL}})}$$

(5)

$$k_{\mathrm{i}}=\sqrt{(\mathrm{Re}[Z_{\mathrm{dopt}}]-R_{\mathrm{i}1})\frac{{\omega }^2{C}_{\mathrm{iL}}^2{(R_{\mathrm{i}2}+R_{\mathrm{iL}})}^2+{({\omega }^2{C}_{\mathrm{iL}}{L}_{\mathrm{i}2}-1)}^2}{{\omega }^4{L}_{\mathrm{i}1}{L}_{\mathrm{i}2}{C}_{\mathrm{iL}}^2(R_{\mathrm{i}2}+R_{\mathrm{iL}})}}$$

(6)

3.2. Design of Output Matching Network

According to Equations (2) and (3), the calculation of L_o1 and k_o requires the knowledge of load capacitance C_oL and resistance R_oL, as well as parasitic resistances R_o1 and R_o2. C_oL and R_oL can be calculated based on the EM simulation of output GSG pads. As the transformer windings are usually implemented with the top two metal layers to reduce insertion loss, the typical values of R_o1 and R_o2 are usually assumed to be 1 Ω and 1.5 Ω, respectively.

The optimal load impedance of the output stage can be derived by load–pull analysis. In our design, Z_oopt is (16.5 + j21.1) Ω at 81 GHz. According to Equations (2) and (3), the calculated k_o and n_o for L_o2 ranging from 30 to 400 pH are shown in Figure 4, where n_o is the turn ratio and defined as $n_{\mathrm{o}}=\sqrt{L_{\mathrm{o}2}/L_{\mathrm{o}1}}$. When L_o2 is selected to be 70 pH, the calculated turn ratio n_o is 1.03 and the magnetic coupling coefficient k_o is 0.78.

The top two metal layers are used to construct the transformer windings, and the selected parameters L_o2, k_o and n_o are realized by adjusting the transformer dimensions.

4. Experimental Results

The PA prototype was designed and implemented in a 40 nm CMOS process, and the chip micrograph is shown in Figure 5. The core area of the presented PA is 330 μm × 93 μm, excluding the RF and DC pads. The DC power dissipation is 47 mW at 1 V supply. The supply and bias voltages of the PA are wire-bonded to the printed circuit board (PCB) and the input and output RF pads are accessed using millimeter-wave GSG probes.

The S-parameter and output power measurement setup is shown in Figure 6. The S-parameters are measured from 200 MHz to 110 GHz using a N5251A network analyzer with frequency extenders. The output power is measured using a E8257D signal generator and a E4416A power meter.

The measured S-parameters are shown in Figure 7. The PA achieves a peak small signal gain of 16.8 dB at 70 GHz and a 3 dB bandwidth of about 9 GHz. The S₁₁ is below −10 dB from about 68 to 72 GHz, and S₂₂ is below −13 dB from 71 to 86 GHz. The measured stability factor K is larger than unity, as shown in Figure 8, indicating that the PA is unconditionally stable. Figure 9 shows the simulated S₂₁ at 81 GHz due to the neutralization capacitor variations from the Monte Carlo simulation.

The measured gain, output power, and PAE at 81 GHz are shown in Figure 10. The PA achieved 11.2 dBm P_1dB and 12.7 dBm P_sat with a P_1dB/P_sat ratio of 88% in dBm compared to 75% in [2]. The PA exhibited a PAE_1dB of 15.6% and a PAE_max of 17.5%. The measured PAE at 6 dB PBO is 6.5%. Figure 11 plots the large-signal performance over 75–85 GHz; the measured P_1dB ranges from 9.2 to 11.2 dBm and P_sat ranges from 11.3 to 12.7 dBm.

Table 1. E-band PA performance comparison.

Ref. Year	Tech.	Freq. (GHz)	Supply Voltage (V)	Num. of Stages	Gain (dB)	P1dB (dBm)	Psat (dBm)	PAE1dB (%)	PAEmax (%)	PAE@Psat- 6 dB (%)	Core Area (mm2)
[2], 2019	22 nm FD-SOI	76	2	2	17.8	13.3	17.8	8.1 *	17.3	4.3 *	0.02
[3], 2019	22 nm Fin-FET	75	1	2	16.6	5.7	12.8	11.6	26.3	-	0.054
[5], 2020	65 nm CMOS	73	1.2	3	26–31	12.0	14.3	13.3	22.4	5.6	0.025
[16], 2021	28 nm FD-SOI	77	1	3	26.5	10.0	13.5	8.0 *	14.5	-	0.15
[17], 2021	40 nm CMOS	70	2	2	10.9	10.8	14.0	11.0	15.0	4.0 *	0.075
[18], 2017	65 nm CMOS	75	1.3	3	21.4	14.6	17.3	11.2 *	18.9	5.0	0.09
[19], 2015	28 nm CMOS	60	0.9	3	24.3	7.4	10.8	-	22.4 **	5.3 *	0.18
This work	40 nm CMOS	81	1	2	12.5	11.2	12.7	15.6	17.5	6.5	0.031

* Estimated from reported figures; ** drain efficiency.

summarizes the performance of the E-band PA and compares it with similar works previously published. The PA achieves higher efficiencies at P_1dB and 6 dB PBO, as well as a higher P_1dB/P_sat ratio compared to the previously reported millimeter-wave PAs based on a more advanced CMOS process, indicating that the PA exhibits good linearity. The PA occupies a core area of only 0.031 mm².

5. Conclusions

A compact E-band PA has been designed and implemented with 40 nm CMOS technology. The output stage of the PA is biased in the deep class-AB region to achieve high efficiencies at P_1dB and 6 dB PBO. The circuit design and parameter optimization were carried out with the guidance of impedance formulations. The E-band PA exhibited a P_1dB of 11.2 dBm, only 1.5 dB lower than the P_sat of 12.7 dBm, with a P_1dB/P_sat ratio of 88% in dBm compared to the previously reported 75% in [2]. The PA achieved 15.6% PAE_1dB, 17.5% PAE_max, and 6.5% PAE at 6 dB PBO with 1 V supply. The comparison with other E-band PAs showed higher efficiencies both at P_1dB and 6 dB PBO, with a larger P_1dB/P_sat ratio.