Search Results (168)

A battery charger for solid-state lithium battery packs was developed and implemented. The power stage used a phase-shifted full-bridge converter integrated with a current-doubler rectifier and synchronous rectification. Dual voltage and current control loops were employed to enable constant-voltage and constant-current charging modes. To improve the lifespan of the output filter capacitor, the current-doubler rectifier was adopted to effectively reduce output current ripple. During the initial start-up phase, as the charger transitions from constant-voltage to constant-current output mode, the use of proportional–integral control in the voltage and current loop error amplifiers may cause current overshoot during the step-rising phase, primarily due to the integral action. Therefore, this study incorporated fuzzy control, proportional control, and proportional–integral control strategies into the current-loop error amplifier. This approach effectively reduced the current overshoot during the step-rising phase, preventing the charger from mistakenly triggering the overcurrent protection mode. The analysis and design considerations of the proposed circuit topology and control loop are presented. Experimental results agree with theoretical predictions, thereby confirming the validity of the proposed approach. Full article

When connecting a renewable energy source to a medium-voltage grid, it has to fulfil grid codes and be able to work in a medium-voltage range (>10 kV). Multilevel converters (MLCs) are recognized for their low total harmonic distortion (THD) and ability to work at high voltage compared to other converter types, making them ideal for applications connected to medium-voltage grids whilst being compliant with grid codes and voltage ratings. Cascaded H-bridge multilevel converters (CHBs-MLC) are a type of MLC topology, and they does not need any capacitors or diodes for clamping like other MLC topologies. One of the problems in these types of converters involves the double-frequency harmonics in the DC linking voltage and power, which can increase the size of the capacitors and converters. The use of line frequency transformers for isolation is another factor that increases the system’s size. This paper proposes an isolated CHBs-MLC topology that effectively overcomes double-line frequency harmonics and offers isolation. In the proposed topology, each DC source (renewable energy source) supplies a three-phase load rather than a single-phase load that is seen in conventional MLCs. This is achieved by employing a multi-winding high-frequency transformer (HFT). The primary winding consists of a winding connected to the DC sources. The secondary windings consist of three windings, each supplying one phase of the load. This configuration reduces the DC voltage link ripples, thus improving the power quality. Photovoltaic (PV) renewable energy sources are considered as the DC sources. A case study of a 1.0 MW and 13.8 kV photovoltaic (PV) system is presented, considering two scenarios: variations in solar irradiation and 25% partial panel shedding. The simulations and design results show the benefits of the proposed topology, including a seven-fold reduction in capacitor volume, a 2.7-fold reduction in transformer core volume, a 50% decrease in the current THD, and a 30% reduction in the voltage THD compared to conventional MLCs. The main challenge of the proposed topology is the use of more switches compared to conventional MLCs. However, with advancing technology, the cost is expected to decrease over time. Full article

This paper introduces a high-conversion ratio multiphase nonisolated converter built from generic LC cells. The unique architecture that hinges on a generic capacitor inductor switching module enables the high modularity of the topology, providing a quick extension of the converter design in an interleaved configuration for lower ripple and higher current output. The generic module comprises the basic power components of a nonisolated DC–DC converter, where the unique interaction between the capacitor and the inductor results in a soft charging operation, which curbs the losses of the converter, and contributes to a higher efficiency. Additional features of the new converter include a significantly extended effective duty ratio, and a lower voltage stress on the switches, a very high output current, and architecture-inherent output current sharing that balances the loading between the phases. In addition, a power extension using a paralleling and interleaving approach is presented to provide higher output current capabilities. Simulation and experimental results of a modular interleaved three-phase prototype demonstrate an excellent proof of concept and agree well with the theoretical analyzes developed in this study. Full article

Modular multilevel converter (MMC)-based power electronic transformers (PETs) present a promising solution for connecting AC/DC microgrids to facilitate renewable energy access. However, the capacitor ripple voltage in MMC-based PET submodules hinders volume optimization and power density enhancement, significantly limiting their application in distribution networks. To address this issue, this study introduces an optimized method for suppressing the submodule capacitor ripple voltage in MMC-based PET systems under normal and grid fault conditions. First, an MMC–PET topology featuring upper and lower arm coupling is proposed. Subsequently, a double-frequency circulating current injection strategy is incorporated on the MMC side to eliminate the double-frequency ripple voltage of the submodule capacitor. Furthermore, a phase-shifting control strategy is applied in the isolation stage of the dual-active bridge (DAB) to transfer the submodule capacitor selective ripple voltages to the isolation stage coupling link, effectively eliminating the fundamental frequency ripple voltage. The optimized approach successfully suppresses capacitor ripples without increasing current stress on the isolated-stage DAB switches, even under grid fault conditions, which are not addressed by existing ripple suppression methods, thereby reducing device size and cost while ensuring reliable operation. Specifically, the peak-to-peak submodule capacitor ripple voltage is reduced from 232 V to 10 V, and the peak current of the isolation-stage secondary-side switch is limited to ±90 A. The second harmonic ripple voltage on the LVDC bus can be decreased from ±5 V to ±1 V with the proposed method under the asymmetric grid voltage condition. Subsequently, a system simulation model is developed in MATLAB/Simulink. The simulation results validated the accuracy of the theoretical analysis and demonstrated the effectiveness of the proposed method. Full article

Inductor parameter variations often affect the control performance of digital current mode (CM)-controlled buck converters as their high performance relies on accurate converter modeling. However, recent studies have shown that reliably monitoring inductance with current sensors and high-frequency sampling greatly increases the overall cost of this process. To address this issue, an online inductance monitoring method without a current sensor is proposed in this study. First, an inductance calculation model is derived by applying the dynamic characteristics of a buck converter with inductor volt-second and capacitor charge balance principles. The model’s accuracy is guaranteed by considering inductor current switching ripple characteristics. Nevertheless, output capacitor equivalent series resistance (ESR) can degrade the accuracy of the proposed calculation model. Thus, to enhance the tolerance of the inductance calculation model to capacitor ESR, the ESR effect on inductance monitoring is investigated. With the proposed capacitor ESR estimation method, inductance monitoring achieves reliable accuracy, even for a buck converter with high capacitor ESR. The effectiveness of the proposed method is verified by simulations and experiments on a buck converter with digital sensorless current mode (SCM) control. Full article

The LLC converter achieves the highest efficiency in resonant operation. Conventionally, the input DC-link voltage is controlled to operate the LLC converter at resonance for the given operating point. However, the DC-link capacitor voltage shows a low-frequency voltage ripple (typically the second harmonic of grid frequency) in cascaded converters so that the LLC has to adapt its switching frequency within the grid period. Conventionally, the LLC converter operates 50% of the time above the resonant frequency of 40 kHz and 50% below resonance. Both operating conditions cause additional losses. However, experimental measurements indicate that the below-resonance operation causes significantly higher losses than above-resonance operation due to much higher primary and secondary transformer currents. It is better to increase the DC-link voltage by 30% of the peak-to-peak low-frequency voltage ripple to mostly avoid below-resonance operation (i.e., from 650 V to 680 V in this case). With the proposed control, the LLC converter operates about 75% of time over resonance and only 25% of time below resonance. The overall efficiency increases from 97.66% to 97.7% for the average operating point with an 80% load current. This corresponds to a 2% total loss reduction. Finally, the peak resonance capacitor voltage decreases from 910 V to 790 V (−13%). Full article

Conventional operational amplifier designs often experience parameter performance issues during the transition between complementary input differential stages, which restricts the full rail-to-rail common mode voltage swing. This paper presents an innovative charge pump architecture featuring a feedback supply selector that optimizes the transition performance. The proposed approach employs a switched-capacitor technique to boost the supply voltage by 1.5 V relative to the input voltage, thereby enabling the use of a single pMOS differential input stage. The novel supply selector dynamically chooses the maximum available voltage between the external supply and the boosted output, ensuring efficient transistor switching and improved biasing. Schematic-level and post-layout simulations in a 250 nm CMOS process validate the design under varied load currents, supply voltages, temperatures, and process corners. Results show a significant reduction in output voltage ripple, with a maximum value of 48 mV achieved post-layout, and enhanced overall efficiency, even under higher load currents. This architecture provides a robust and scalable solution for advanced operational amplifiers, particularly in fields where high performance and stability are critical. Full article

In this article, a new high step-up interleaved DC–DC converter is presented for renewable energy systems. The converter circuit is based on the interleaved two-phase boost converter and integrates a voltage-lift capacitor and a voltage multiplier cell. A high voltage gain of the converter can be achieved with a reasonable duty ratio and the voltage stresses of semiconductor devices are reduced. Because of low voltage stress, the switches with low on-resistance and the diodes with low forward voltage drops can be adopted to minimize the conduction losses. Additionally, the switching losses are reduced because the switches are turned on under zero-current switching (ZCS) conditions. Due to the existence of leakage inductances of the coupled inductors, the diode reverse-recovery problem is alleviated. Moreover, the leakage energy is recycled and the voltage spikes during switch turn-off are avoided. The parallel input architecture and interleaved operation reduce the input current ripple. The operating principles, steady-state characteristics, and design considerations of the presented converter are proposed in detail. Furthermore, a closed-loop control is designed to maintain a well-regulated output voltage despite variations in input voltage and output load. A prototype converter with a rated 1000 W output power is realized for demonstration. Finally, experimental results show the converter effectiveness and verify the theoretical analysis. Full article

A Buck converter in the DC microgrid is often used to transform high DC voltage to meet the requirements of low voltage loads, where electrolytic capacitors are commonly regarded as the most vulnerable components. A lot of studies have shown that equivalent series resistance (ESR) is the best health indicator for electrolytic capacitors, which means that it is significant to monitor the variation in ESR values for health evaluation. This paper presents a non-intrusive online ESR estimation method of the output capacitor for a Buck converter based on inductor current ripple fitting. In this method, only output voltage is sampled and inductor/capacitor current ripple is fitted by use of the characteristics of output voltage ripple. ESR calculation is implemented based on the orthogonality of the voltage ripple and the fitted current ripple, which has high-precision and anti-noise characteristics. Compared to existing methods, the proposed scheme does not require additional current sensors or high-precision trigger sampling devices, making it a cost-effective solution. Based on the proposed scheme, accurate ESR estimation is achieved for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). An experimental ESR monitoring system platform is built and experimental estimation results are provided to verify the effectiveness and the precision. Full article

In modern marine vessels equipped with electric propulsion systems, rectifiers are commonly used as part of the setup. However, the conventional deadbeat predictive direct power control strategy for three-phase voltage source pulse-width modulation (PWM) rectifiers tends to underperform when subjected to load variations and external disturbances. To address these limitations, this paper proposes an enhanced linear active disturbance rejection control (LADRC), incorporating virtual capacitance and an improved equivalent input disturbance strategy. The integration of virtual capacitance in the LADRC is specifically applied during load transitions. Virtual capacitance is a capacitor element simulated through the control strategy. It enhances voltage stability and dynamic response capability by compensating for voltage fluctuations and power deficits in the system. By providing a virtual active power, this approach substantially improves power tracking performance, reducing the DC voltage drop and settling time by 60% and 74%, respectively. In addition, the proposed strategy is easy to implement and does not add complexity to the LADRC. Moreover, the equivalent input disturbance is refined through virtual capacitance, enabling accurate disturbance estimation. As a result, the active power ripple and current total harmonic distortion under disturbances are reduced by 44% and 40%, respectively. The stability of the proposed strategy is comprehensively analyzed, and experimental results from a prototype system validate its effectiveness and accuracy. Full article

This paper conducts an in-depth study on the application of inductor-capacitor-inductor (LCL) filters in grid-connected photovoltaic (PV) inverters. First, the resonance issues associated with LCL filters are analyzed, and solutions are discussed, with a focus on the implementation of passive damping strategies. Various passive damping schemes, based on the placement of resistors (R), are compared and analyzed, ultimately selecting the capacitor branch series resistor as the optimal solution. During the design process, multiple parameters, such as total inductance, inverter-side inductance, grid-side inductance, capacitance, and damping resistors, are considered in light of their mutual constraints. Detailed analysis and optimization of these parameters are performed based on steady-state operation, current ripple, and power loss limitations. Finally, it is concluded that the passive damping solution using a series resistor in the capacitor branch meets the requirements for stable operation and efficient filtering. The optimal solutions are identified as R₁ = 0, R₂ = ∞, R₃ ≠ 0, and R₄ = ∞, providing a reliable and effective filtering solution for grid-connected PV inverter systems. Full article

This paper presents a carrier waves phase shifting method to reduce the dc-link capacitor current for a dual three-phase permanent magnet synchronous motor drive system. Dc-link capacitors absorb the ripple current generated at the input due to the harmonics of the pulse width modulation (PWM). The size, cost, reliability, and lifetime of the dc-link capacitor are negatively affected by this ripple current flowing through it. The proposed method is especially appropriate for common dc-link capacitors for a dual inverter system driving two PMSMs. In this paper, the input current of each inverter is analyzed using Double Fourier Analysis, and the harmonic components of the dc-link capacitor current are determined. The carrier wave phase shifting method is proposed to reduce the magnitude of the harmonics and thus reduce the dc-link capacitor current. Furthermore, the optimum angle between the carrier waves for the maximum reduction in the dc-link capacitor current is analyzed and simulated for different scenarios considering the speed and load torque of the PMSMs. The proposed method is verified through experiments and PMSMs are driven by three-phase voltage source inverters (VSIs) modulated with Space Vector Pulse Width Modulation (SVPWM), which is the most common PWM strategy. The proposed method reduces the dc-link capacitor current by 60%, thereby significantly decreasing the required dc-link capacitance, the volume of the drive system, and its cost. Full article

The Cuk power factor correction (PFC) converter with an input inductor operating discontinuous conduction mode (DCM) is widely utilized for its advantages of continuous input and output currents, low output voltage ripple, and simple control. However, the conventional Cuk PFC converter encounters issues such as the inability to achieve high power factor (PF) because of input current distortion and high intermediate capacitor voltage, especially at high input voltage. To achieve high PF, high efficiency, and low intermediate capacitor voltage simultaneously, by operating the output inductor at critical conduction mode (CRM) and adjusting input inductance from 170 µH to 930 µH within the half-line cycle dynamically with the transient rectified input voltage, a DCM-CRM Cuk PFC converter utilizing variable inductor control is proposed in this paper. The topology operational principle, control strategy, and key characteristics of the proposed converter have been studied. A 108 W experimental prototype was built and tested to validate the proposed converter. According to the comparative experimental results between the conventional converter and the proposed converter, it can be concluded that the proposed converter utilizing variable inductor control can enhance the PF and efficiency and reduce the intermediate capacitor voltage and total harmonic distortion (THD) of input current with universal 90~240 Vac input voltage range. Full article

Flash memory, as the core unit of a compute-in-memory (CIM) array, requires multiple positive and negative (PN) high voltages (HVs) for word lines (WLs) to operate during storage and computation. A traditional WL driver generates these voltages using several charge pumps (CPs), leading to significant area overhead. This paper presents a novel multi-mode CP (MMCP) that generates all required HVs for a CIM array under a single CP, supporting CIM unit operation in programming, readout, and erase modes. Unlike traditional voltage multipliers, the MMCP eliminates the need for multiple CPs, reducing area and pump capacitor usage. Compared to a PN CP that drives a common load, the MMCP can provide multiple PN HVs by using level shifters (LSs) and switches. The MMCP is designed in a 55 nm standard CMOS process with an area of only 0.021 mm². Additionally, this paper proposes global PN HV switches, which can correctly deliver the PN HVs generated by the MMCP from the same port (at different times) to the upper and lower power rails of WL driver circuits. Simulation results show that with a 2.5 V supply, 100 pF load, and 50 $\mathsf{\mu }$A current, the maximum error due to ripple is only 0.28%. Full article

The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm²), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs. Full article